/art/compiler/dex/quick/x86/ |
H A D | utility_x86.cc | 25 LIR* X86Mir2Lir::OpFpRegCopy(int r_dest, int r_src) { argument 28 DCHECK_EQ(X86_DOUBLEREG(r_dest), X86_DOUBLEREG(r_src)); 33 if (X86_SINGLEREG(r_src)) { 39 DCHECK(X86_SINGLEREG(r_src)); 44 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest, r_src); 45 if (r_dest == r_src) { 269 LIR* X86Mir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src, argument 273 return NewLIR3(opcode, r_dest, r_src, value); 275 if (value == 0xFF && r_src < 4) { 276 return NewLIR2(kX86Movzx8RR, r_dest, r_src); 463 StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_src, int r_src_hi, OpSize size, int s_reg) argument 544 StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) argument 550 StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) argument [all...] |
H A D | codegen_x86.h | 41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size); 43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size); 45 int r_src, int r_src_hi, OpSize size, int s_reg); 144 LIR* OpFpRegCopy(int r_dest, int r_src); 149 LIR* OpRegCopy(int r_dest, int r_src); 150 LIR* OpRegCopyNoInsert(int r_dest, int r_src);
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H A D | int_x86.cc | 112 LIR* X86Mir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) { argument 113 if (X86_FPREG(r_dest) || X86_FPREG(r_src)) 114 return OpFpRegCopy(r_dest, r_src); 116 r_dest, r_src); 117 if (r_dest == r_src) { 123 LIR* X86Mir2Lir::OpRegCopy(int r_dest, int r_src) { argument 124 LIR *res = OpRegCopyNoInsert(r_dest, r_src);
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/art/compiler/dex/quick/mips/ |
H A D | utility_mips.cc | 24 LIR* MipsMir2Lir::OpFpRegCopy(int r_dest, int r_src) { argument 27 DCHECK_EQ(MIPS_DOUBLEREG(r_dest), MIPS_DOUBLEREG(r_src)); 32 if (MIPS_SINGLEREG(r_src)) { 36 int t_opnd = r_src; 37 r_src = r_dest; 42 DCHECK(MIPS_SINGLEREG(r_src)); 46 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_src, r_dest); 47 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 388 LIR* MipsMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src, argument 395 if (MIPS_FPREG(r_src)) { 543 StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size) argument 625 StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) argument 645 StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_src, int r_src_hi, OpSize size, int s_reg) argument [all...] |
H A D | codegen_mips.h | 41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size); 43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size); 45 int r_src, int r_src_hi, OpSize size, int s_reg); 144 LIR* OpFpRegCopy(int r_dest, int r_src); 149 LIR* OpRegCopy(int r_dest, int r_src); 150 LIR* OpRegCopyNoInsert(int r_dest, int r_src); 166 LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size);
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H A D | int_mips.cc | 164 LIR* MipsMir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) { argument 165 if (MIPS_FPREG(r_dest) || MIPS_FPREG(r_src)) 166 return OpFpRegCopy(r_dest, r_src); 168 r_dest, r_src); 169 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 175 LIR* MipsMir2Lir::OpRegCopy(int r_dest, int r_src) { argument 176 LIR *res = OpRegCopyNoInsert(r_dest, r_src);
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/art/compiler/dex/quick/arm/ |
H A D | utility_arm.cc | 706 LIR* ArmMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src, argument 708 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_src); 714 if (ARM_FPREG(r_src)) { 715 if (ARM_SINGLEREG(r_src)) { 720 DCHECK(ARM_DOUBLEREG(r_src)); 722 DCHECK_EQ((r_src & 0x1), 0); 741 store = NewLIR3(opcode, r_src, reg_ptr, 0); 759 store = NewLIR3(opcode, r_src, rBase, r_index); 761 store = NewLIR4(opcode, r_src, rBase, r_index, scale); 903 int r_src, in 902 StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size) argument 1005 StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) argument 1015 OpFpRegCopy(int r_dest, int r_src) argument 1045 StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_src, int r_src_hi, OpSize size, int s_reg) argument [all...] |
H A D | codegen_arm.h | 40 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size); 42 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size); 44 int r_src, int r_src_hi, OpSize size, int s_reg); 143 LIR* OpFpRegCopy(int r_dest, int r_src); 148 LIR* OpRegCopy(int r_dest, int r_src); 149 LIR* OpRegCopyNoInsert(int r_dest, int r_src); 166 LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size);
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H A D | int_arm.cc | 337 LIR* ArmMir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) { argument 340 if (ARM_FPREG(r_dest) || ARM_FPREG(r_src)) 341 return OpFpRegCopy(r_dest, r_src); 342 if (ARM_LOWREG(r_dest) && ARM_LOWREG(r_src)) 344 else if (!ARM_LOWREG(r_dest) && !ARM_LOWREG(r_src)) 350 res = RawLIR(current_dalvik_offset_, opcode, r_dest, r_src); 351 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 357 LIR* ArmMir2Lir::OpRegCopy(int r_dest, int r_src) { argument 358 LIR* res = OpRegCopyNoInsert(r_dest, r_src);
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/art/compiler/dex/quick/ |
H A D | gen_loadstore.cc | 83 LIR* Mir2Lir::StoreWordDisp(int rBase, int displacement, int r_src) { argument 84 return StoreBaseDisp(rBase, displacement, r_src, kWord);
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H A D | mir_to_lir.h | 514 LIR* StoreWordDisp(int rBase, int displacement, int r_src); 539 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0; 541 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0; 543 int r_src, int r_src_hi, OpSize size, int s_reg) = 0; 664 virtual LIR* OpFpRegCopy(int r_dest, int r_src) = 0; 669 virtual LIR* OpRegCopy(int r_dest, int r_src) = 0; 670 virtual LIR* OpRegCopyNoInsert(int r_dest, int r_src) = 0;
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H A D | gen_common.cc | 279 int r_src = AllocTemp(); local 298 OpRegRegImm(kOpAdd, r_src, TargetReg(kSp), SRegOffset(rl_first.s_reg_low)); 307 LoadBaseIndexed(r_src, r_idx, r_val, 2, kWord);
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