| /dalvik/libdex/ |
| H A D | DexOpcodes.cpp | 295 const char* dexGetOpcodeName(Opcode op) argument
297 assert(op >= 0 && op < kNumPackedOpcodes);
298 return gOpNames[op];
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| /dalvik/vm/compiler/template/armv5te-vfp/ |
| H A D | funop.S | 3 * "instr" line that specifies an instruction that performs "s1 = op s0".
13 $instr @ s1<- op s0
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| H A D | funopNarrower.S | 3 * "instr" line that specifies an instruction that performs "s0 = op d0".
13 $instr @ s0<- op d0
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| H A D | funopWider.S | 3 * "instr" line that specifies an instruction that performs "d0 = op s0".
13 $instr @ d0<- op s0
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| /dalvik/vm/mterp/mips/ |
| H A D | OP_IGET_QUICK.S | 4 # op vA, vB, offset /* CCCC */
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| H A D | unop.S | 4 * specifies an instruction that performs "result = op a0".
15 $preinstr # optional op
16 $instr # a0 <- op, a0-a3 changed
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| H A D | binop.S | 4 * specifies an instruction that performs "result = a0 op a1".
29 $preinstr # optional op
30 $instr # $result <- op, a0-a3 changed
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| H A D | binop2addr.S | 4 * that specifies an instruction that performs "result = a0 op a1".
25 $preinstr # optional op
26 $instr # $result <- op, a0-a3 changed
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| H A D | unflop.S | 4 * specifies an instruction that performs "result = op a0".
17 $preinstr # optional op
20 $instr # a0 <- op, a0-a3 changed
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| H A D | unopWide.S | 4 * specifies an instruction that performs "result = op a0/a1".
16 $preinstr # optional op
17 $instr # a0/a1 <- op, a2-a3 changed
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| H A D | unopWider.S | 4 * that specifies an instruction that performs "result = op a0", where
15 $preinstr # optional op
16 $instr # result <- op, a0-a3 changed
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| /dalvik/vm/compiler/template/mips/ |
| H A D | funop.S | 4 * specifies an instruction that performs "result = op a0".
19 $preinstr # optional op
20 $instr # v0<- op, a0-a3 changed
25 $preinstr # optional op
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| H A D | funopNarrower.S | 4 * that specifies an instruction that performs "result = op a0/a1", where
22 $preinstr # optional op
23 $instr # v0<- op, a0-a3 changed
28 $preinstr # optional op
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| H A D | funopWider.S | 4 * "instr" line that specifies an instruction that performs "d0 = op s0".
16 $preinstr # optional op
17 $instr # result<- op, a0-a3 changed
23 $preinstr # optional op
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| H A D | fbinopWide.S | 4 * specifies an instruction that performs "result = a0-a1 op a2-a3".
30 $preinstr # optional op
31 $instr # result<- op, a0-a3 changed
41 $preinstr # optional op
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| H A D | fbinop.S | 3 * Generic 32-bit binary float operation. a0 = a1 op a2.
22 $preinstr # optional op
34 $preinstr # optional op
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| /dalvik/vm/compiler/codegen/arm/FP/ |
| H A D | Thumb2VFP.cpp | 21 int op = kThumbBkpt; local
31 op = kThumb2Vadds;
35 op = kThumb2Vsubs;
39 op = kThumb2Vdivs;
43 op = kThumb2Vmuls;
57 newLIR3(cUnit, (ArmOpcode)op, rlResult.lowReg, rlSrc1.lowReg,
67 int op = kThumbBkpt; local
73 op = kThumb2Vaddd;
77 op = kThumb2Vsubd;
81 op
114 int op = kThumbBkpt; local
[all...] |
| /dalvik/vm/mterp/armv5te/ |
| H A D | unop.S | 4 * specifies an instruction that performs "result = op r0".
15 $preinstr @ optional op; may set condition codes
17 $instr @ r0<- op, r0-r3 changed
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| /dalvik/vm/mterp/armv6t2/ |
| H A D | unop.S | 4 * specifies an instruction that performs "result = op r0".
14 $preinstr @ optional op; may set condition codes
16 $instr @ r0<- op, r0-r3 changed
|
| H A D | unopNarrower.S | 4 * that specifies an instruction that performs "result = op r0/r1", where
18 $preinstr @ optional op; may set condition codes
19 $instr @ r0<- op, r0-r3 changed
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| H A D | unopWider.S | 4 * that specifies an instruction that performs "result = op r0", where
14 $preinstr @ optional op; may set condition codes
16 $instr @ r0<- op, r0-r3 changed
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| /dalvik/vm/compiler/codegen/mips/FP/ |
| H A D | MipsFP.cpp | 72 int op = kMipsNop; local
82 op = kMipsFadds;
86 op = kMipsFsubs;
90 op = kMipsFdivs;
94 op = kMipsFmuls;
107 newLIR3(cUnit, (MipsOpCode)op, rlResult.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
162 int op = kMipsNop; local
168 op = kMipsFaddd;
172 op = kMipsFsubd;
176 op
254 int op = kMipsNop; local
[all...] |
| /dalvik/vm/compiler/codegen/x86/libenc/ |
| H A D | enc_base.cpp | 463 const Operand& op = opnds[idx]; local
464 assert(op.is_mem());
476 RegName base = op.base();
478 if (base == RegName_Null && op.index() == RegName_Null) {
479 assert(op.scale() == 0); // 'scale!=0' has no meaning without index
496 *(unsigned*)stream = (unsigned)op.disp();
505 const bool disp_fits8 = CHAR_MIN <= op.disp() && op.disp() <= CHAR_MAX;
506 /*&& op.base() != RegName_Null - just checked above*/
507 if (op
[all...] |
| /dalvik/opcode-gen/ |
| H A D | opcode-gen.awk | 268 if (cmd == "op") {
357 function deriveOpcodeChains(i, op) {
358 # locals: i, op
367 op = findNextOpcode(i);
368 nextOpcode[i] = op;
369 if (op != -1) {
370 isFirst[op] = "false";
401 function createPackedTables(i, op) {
402 # locals: i, op
404 op
[all...] |
| /dalvik/vm/compiler/codegen/arm/ |
| H A D | Codegen.h | 32 static ArmLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
34 static ArmLIR *opRegReg(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
|