Searched refs:rm (Results 1 - 15 of 15) sorted by relevance

/dalvik/tests/004-annotations/
H A Dbuild26 rm classes/android/test/anno/MissingAnnotation.class
/dalvik/vm/compiler/codegen/x86/libenc/
H A Dencoder.inl80 inline static void add_rm(EncoderBase::Operands & args, const RM_Opnd & rm, Opnd_Size sz, OpndExt ext = OpndExt_None) {
81 rm.is_reg() ? add_r(args, (R_Opnd &)rm, sz, ext) : add_m(args, (M_Opnd &)rm, sz, ext);
110 ENCODER_DECLARE_EXPORT char * push(char * stream, const RM_Opnd & rm, Opnd_Size sz) {
112 add_rm(args, rm, sz);
127 ENCODER_DECLARE_EXPORT char * pop(char * stream, const RM_Opnd & rm, Opnd_Size sz) {
129 add_rm(args, rm, sz);
134 ENCODER_DECLARE_EXPORT char * cmpxchg(char * stream, const RM_Opnd & rm, const R_Opnd & r, Opnd_Size sz) {
136 add_rm(args, rm, s
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H A Dencoder.h468 ENCODER_DECLARE_EXPORT char * push(char * stream, const RM_Opnd & rm, Opnd_Size sz = size_platf);
470 ENCODER_DECLARE_EXPORT char * pop(char * stream, const RM_Opnd & rm, Opnd_Size sz = size_platf);
473 ENCODER_DECLARE_EXPORT char * cmpxchg(char * stream, const RM_Opnd & rm, const R_Opnd & r, Opnd_Size sz = size_platf);
474 ENCODER_DECLARE_EXPORT char * xchg(char * stream, const RM_Opnd & rm, const R_Opnd & r, Opnd_Size sz = size_platf);
477 ENCODER_DECLARE_EXPORT char * inc(char * stream, const RM_Opnd & rm, Opnd_Size sz = size_platf);
478 ENCODER_DECLARE_EXPORT char * dec(char * stream, const RM_Opnd & rm, Opnd_Size sz = size_platf);
479 ENCODER_DECLARE_EXPORT char * _not(char * stream, const RM_Opnd & rm, Opnd_Size sz = size_platf);
480 ENCODER_DECLARE_EXPORT char * neg(char * stream, const RM_Opnd & rm, Opnd_Size sz = size_platf);
485 ENCODER_DECLARE_EXPORT char * alu(char * stream, ALU_Opcode opc, const RM_Opnd & rm, const Imm_Opnd & imm, Opnd_Size sz = size_platf);
487 ENCODER_DECLARE_EXPORT char * alu(char * stream, ALU_Opcode opc, const R_Opnd & r, const RM_Opnd & rm, Opnd_Siz
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H A Ddec_base.cpp478 RegName reg = getRegName(okind, opndDesc.size, EXTEND_REG(modrm.rm, b));
486 if (modrm.rm == 4) {
505 if (modrm.mod != 0 || modrm.rm != 5) {
506 base = getRegName(OpndKind_GPReg, OpndSize_32, EXTEND_REG(modrm.rm, b)); //Android x86: OpndDesc.size
509 // mod=0 && rm == 5 => only disp32
526 if (modrm.rm == 5) {
531 else if (modrm.rm == 4 && sib.base == 5) {
H A Denc_base.cpp137 modrm.rm = getHWRegIndex(opnds[memidx].reg());
171 modrm.rm = getHWRegIndex(opnds[idx].reg());
485 modrm.rm = 4; // 100 - have SIB
494 modrm.rm = 5;
527 modrm.rm = getHWRegIndex(op.base());
546 modrm.rm = 4; // r/m = 100, means 'we have SIB here'
H A Denc_prvt.h278 unsigned char rm:3; member in struct:ModRM
/dalvik/tests/003-omnibus-opcodes/
H A Dbuild22 rm classes/UnresClass.class
/dalvik/vm/mterp/
H A Drebuild.sh29 rm -f out/InterpAsm-portable.S
/dalvik/opcode-gen/
H A Dopcode-gen63 rm "$tmpfile"
/dalvik/dx/tests/
H A Drun-test106 rm -rf "$tmpdir"
133 rm -rf "$tmpdir"
/dalvik/vm/alloc/TEST/HeapBitmapTest/
H A DMakefile25 rm -rf out
/dalvik/tests/
H A Drun-test184 rm -rf "$tmp_dir"
236 rm -rf "$tmp_dir"
/dalvik/dx/src/com/android/dx/ssa/back/
H A DIdenticalBlockCombiner.java40 * @param rm {@code non-null;} instance to process
42 public IdenticalBlockCombiner(RopMethod rm) { argument
43 ropMethod = rm;
/dalvik/vm/compiler/codegen/mips/
H A DAssemble.cpp1948 kMemOpStrRRR = 0x28, // str(2) [0101000] rm[8..6] rn[5..3] rd[2..0]
1949 kMemOpStrhRRR = 0x29, // strh(2) [0101001] rm[8..6] rn[5..3] rd[2..0]
1950 kMemOpStrbRRR = 0x2A, // strb(2) [0101010] rm[8..6] rn[5..3] rd[2..0]
1951 kMemOpLdrsbRRR = 0x2B, // ldrsb [0101011] rm[8..6] rn[5..3] rd[2..0]
1952 kMemOpLdrRRR = 0x2C, // ldr(2) [0101100] rm[8..6] rn[5..3] rd[2..0]
1953 kMemOpLdrhRRR = 0x2D, // ldrh(2) [0101101] rm[8..6] rn[5..3] rd[2..0]
1954 kMemOpLdrbRRR = 0x2E, // ldrb(2) [0101110] rm[8..6] rn[5..3] rd[2..0]
1955 kMemOpLdrshRRR = 0x2F, // ldrsh [0101111] rm[8..6] rn[5..3] rd[2..0]
1964 kMemOp2StrbRRR = 0xF80, /* str rt,[rn,rm,LSL #imm] [111110000000]
1965 rn[19-16] rt[15-12] [000000] imm[5-4] rm[
2020 int rm = insn & 0xF; local
2188 int rm = (insn >> 6) & 0x7; local
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/dalvik/vm/compiler/codegen/arm/
H A DAssemble.cpp2575 kMemOpStrRRR = 0x28, // str(2) [0101000] rm[8..6] rn[5..3] rd[2..0]
2576 kMemOpStrhRRR = 0x29, // strh(2) [0101001] rm[8..6] rn[5..3] rd[2..0]
2577 kMemOpStrbRRR = 0x2A, // strb(2) [0101010] rm[8..6] rn[5..3] rd[2..0]
2578 kMemOpLdrsbRRR = 0x2B, // ldrsb [0101011] rm[8..6] rn[5..3] rd[2..0]
2579 kMemOpLdrRRR = 0x2C, // ldr(2) [0101100] rm[8..6] rn[5..3] rd[2..0]
2580 kMemOpLdrhRRR = 0x2D, // ldrh(2) [0101101] rm[8..6] rn[5..3] rd[2..0]
2581 kMemOpLdrbRRR = 0x2E, // ldrb(2) [0101110] rm[8..6] rn[5..3] rd[2..0]
2582 kMemOpLdrshRRR = 0x2F, // ldrsh [0101111] rm[8..6] rn[5..3] rd[2..0]
2591 kMemOp2StrbRRR = 0xF80, /* str rt,[rn,rm,LSL #imm] [111110000000]
2592 rn[19-16] rt[15-12] [000000] imm[5-4] rm[
2646 int rm = insn & 0xF; local
2814 int rm = (insn >> 6) & 0x7; local
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