Searched refs:CP0SRSC3_SRS11 (Results 1 - 2 of 2) sorted by relevance

/external/qemu/target-mips/
H A Dcpu.h255 #define CP0SRSC3_SRS11 10 macro
H A Dtranslate_init.c300 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),

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