/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypes.h | 164 SDValue JoinIntegers(SDValue Lo, SDValue Hi); 173 void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi); 175 SDValue &Lo, SDValue &Hi); 298 /// of Op are exactly equal to the bits of Lo; the high bits exactly equal Hi. 300 /// method returns the two i32's, with Lo being equal to the lower 32 bits of 302 void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi); 303 void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi); 308 SDValue &Lo, SDValue &Hi); 309 void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi); 310 void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValu 693 GetSplitOp(SDValue Op, SDValue &Lo, SDValue &Hi) argument 726 GetExpandedOp(SDValue Op, SDValue &Lo, SDValue &Hi) argument [all...] |
H A D | LegalizeTypesGeneric.cpp | 14 // computation in two identical registers of a smaller type. The Lo/Hi part 30 // These routines assume that the Lo/Hi part is stored first in memory on 31 // little/big-endian machines, followed by the Hi/Lo part. This means that 32 // they cannot be used as is on vectors, for which Lo is always stored first. 34 SDValue &Lo, SDValue &Hi) { 36 GetExpandedOp(Op, Lo, Hi); 39 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) { argument 53 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi); local 54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 33 ExpandRes_MERGE_VALUES(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi) argument 184 ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo, SDValue &Hi) argument 191 ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 203 ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 243 ExpandRes_NormalLoad(SDNode *N, SDValue &Lo, SDValue &Hi) argument 285 ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) argument 356 SDValue Lo, Hi; local 374 SDValue Lo, Hi; local 398 SDValue Lo, Hi; local 446 SDValue Lo, Hi; local 476 SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi) argument 482 SplitRes_SELECT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 506 SplitRes_SELECT_CC(SDNode *N, SDValue &Lo, SDValue &Hi) argument 519 SplitRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi) argument [all...] |
H A D | LegalizeFloatTypes.cpp | 773 SDValue Lo, Hi; local 774 Lo = Hi = SDValue(); 788 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 789 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 790 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 792 case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 793 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; 794 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 795 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 796 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, H 832 SetExpandedFloat(SDValue(N, ResNo), Lo, Hi); local 835 ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, SDValue &Hi) argument 849 ExpandFloatRes_FABS(SDNode *N, SDValue &Lo, SDValue &Hi) argument 863 ExpandFloatRes_FADD(SDNode *N, SDValue &Lo, SDValue &Hi) argument 873 ExpandFloatRes_FCEIL(SDNode *N, SDValue &Lo, SDValue &Hi) argument 883 ExpandFloatRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi) argument 895 ExpandFloatRes_FCOS(SDNode *N, SDValue &Lo, SDValue &Hi) argument 905 ExpandFloatRes_FDIV(SDNode *N, SDValue &Lo, SDValue &Hi) argument 919 ExpandFloatRes_FEXP(SDNode *N, SDValue &Lo, SDValue &Hi) argument 929 ExpandFloatRes_FEXP2(SDNode *N, SDValue &Lo, SDValue &Hi) argument 939 ExpandFloatRes_FFLOOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument 949 ExpandFloatRes_FLOG(SDNode *N, SDValue &Lo, SDValue &Hi) argument 959 ExpandFloatRes_FLOG2(SDNode *N, SDValue &Lo, SDValue &Hi) argument 969 ExpandFloatRes_FLOG10(SDNode *N, SDValue &Lo, SDValue &Hi) argument 979 ExpandFloatRes_FMA(SDNode *N, SDValue &Lo, SDValue &Hi) argument 993 ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1007 ExpandFloatRes_FNEARBYINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1019 ExpandFloatRes_FNEG(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1027 ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1035 ExpandFloatRes_FPOW(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1045 ExpandFloatRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1055 ExpandFloatRes_FREM(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1065 ExpandFloatRes_FRINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1075 ExpandFloatRes_FSIN(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1085 ExpandFloatRes_FSQRT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1095 ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1109 ExpandFloatRes_FTRUNC(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1119 ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1152 ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1331 SDValue Lo, Hi; local 1444 SDValue Lo, Hi; local [all...] |
H A D | LegalizeIntegerTypes.cpp | 237 SDValue Lo, Hi; local 238 GetSplitVector(N->getOperand(0), Lo, Hi); 239 Lo = BitConvertToInteger(Lo); 243 std::swap(Lo, Hi); 248 JoinIntegers(Lo, Hi)); 906 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); local 908 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 913 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 1082 SDValue Lo, H local 1120 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; local 1177 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); local 1268 ExpandShiftByConstant(SDNode *N, unsigned Amt, SDValue &Lo, SDValue &Hi) argument 1360 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1448 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1522 ExpandIntRes_ADDSUB(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1584 ExpandIntRes_ADDSUBC(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1610 ExpandIntRes_ADDSUBE(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1630 ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo, SDValue &Lo, SDValue &Hi) argument 1636 ExpandIntRes_ANY_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1659 ExpandIntRes_AssertSext(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1680 ExpandIntRes_AssertZext(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1700 ExpandIntRes_BSWAP(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1708 ExpandIntRes_Constant(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1717 ExpandIntRes_CTLZ(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1736 ExpandIntRes_CTPOP(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1747 ExpandIntRes_CTTZ(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1766 ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1777 ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1788 ExpandIntRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi) argument 1903 ExpandIntRes_Logical(SDNode *N, SDValue &Lo, SDValue &Hi) argument 1913 ExpandIntRes_MUL(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2004 ExpandIntRes_SADDSUBO(SDNode *Node, SDValue &Lo, SDValue &Hi) argument 2046 ExpandIntRes_SDIV(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2066 ExpandIntRes_Shift(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2166 ExpandIntRes_SIGN_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2198 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2224 ExpandIntRes_SREM(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2244 ExpandIntRes_TRUNCATE(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2255 ExpandIntRes_UADDSUBO(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2278 ExpandIntRes_XMULO(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2364 ExpandIntRes_UDIV(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2384 ExpandIntRes_UREM(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2404 ExpandIntRes_ZERO_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2432 ExpandIntRes_ATOMIC_LOAD(SDNode *N, SDValue &Lo, SDValue &Hi) argument 2668 SDValue Lo, Hi; local 2677 SDValue Lo, Hi; local 2706 SDValue Lo, Hi; local 2819 SDValue Lo, Hi; local [all...] |
H A D | LegalizeVectorTypes.cpp | 480 SDValue Lo, Hi; local 496 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 498 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 499 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 500 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 501 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 502 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; 503 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 504 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; 505 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, H 511 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); local 517 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); local 582 SetSplitVector(SDValue(N, ResNo), Lo, Hi); local 585 SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi) argument 597 SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi) argument 613 SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) argument 661 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi); local 669 SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument 682 SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi) argument 703 SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument 719 SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi) argument 727 SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi) argument 742 SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi) argument 793 SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) argument 802 SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi) argument 843 SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) argument 873 SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi) argument 916 SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo, SDValue &Hi) argument 1112 SDValue Lo, Hi; local 1155 SDValue Lo, Hi; local 1173 SDValue Lo, Hi; local 1190 SDValue Lo, Hi; local 1252 SDValue Lo, Hi; local 1391 SDValue Lo, Hi; local [all...] |
H A D | LegalizeTypes.cpp | 768 void DAGTypeLegalizer::GetExpandedInteger(SDValue Op, SDValue &Lo, argument 774 Lo = Entry.first; 778 void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo, argument 780 assert(Lo.getValueType() == 782 Hi.getValueType() == Lo.getValueType() && 784 // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant. 785 AnalyzeNewValue(Lo); 791 Entry.first = Lo; 795 void DAGTypeLegalizer::GetExpandedFloat(SDValue Op, SDValue &Lo, argument 801 Lo 805 SetExpandedFloat(SDValue Op, SDValue Lo, SDValue Hi) argument 822 GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi) argument 832 SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi) argument 977 GetPairElements(SDValue Pair, SDValue &Lo, SDValue &Hi) argument 1005 JoinIntegers(SDValue Lo, SDValue Hi) argument 1088 SplitInteger(SDValue Op, EVT LoVT, EVT HiVT, SDValue &Lo, SDValue &Hi) argument 1102 SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi) argument [all...] |
H A D | LegalizeVectorOps.cpp | 450 SDValue Lo, Hi, ShAmt; local 454 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt); 455 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask); 471 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi); 476 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT); 479 Lo = DAG.getZExtOrTrunc(Lo, d [all...] |
/external/llvm/include/llvm/Support/ |
H A D | SwapByteOrder.h | 34 uint16_t Lo = value >> 8; 35 return Hi | Lo; 66 uint32_t Lo = SwapByteOrder_32(uint32_t(value >> 32)); 67 return (Hi << 32) | Lo;
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H A D | GCOV.h | 138 uint64_t Lo = readInt(); local 140 uint64_t Result = Lo | (Hi << 32);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsJITInfo.cpp | 179 int Lo = (int)(NewVal & 0xffff); local 182 *(intptr_t *)(StubAddr + 4) = 9 << 26 | 25 << 21 | 25 << 16 | Lo; 219 int Lo = (int)(EmittedAddr & 0xffff); local 227 JCE.emitWordLE(9 << 26 | 25 << 21 | 25 << 16 | Lo); 232 JCE.emitWordBE(9 << 26 | 25 << 21 | 25 << 16 | Lo);
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H A D | Mips16ISelDAGToDAG.cpp | 47 SDNode *Lo = 0, *Hi = 0; local 54 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag); 55 InFlag = SDValue(Lo, 1); 61 return std::make_pair(Lo, Hi); 212 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
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H A D | MipsSEISelLowering.cpp | 164 // multHi/Lo: product of multiplication 165 // Lo0: initial value of Lo register 240 // multHi/Lo: product of multiplication 241 // Lo0: initial value of Lo register 574 SDValue Lo, Hi; local 577 Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult, 584 return HasLo ? Lo : Hi; 586 SDValue Vals[] = { Lo, Hi }; 600 SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op, local 604 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, H [all...] |
H A D | MipsISelLowering.cpp | 106 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO); local 109 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 123 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag)); local 124 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 155 case MipsISD::Lo: return "MipsISD::Lo"; 670 SDValue Lo = Add.getOperand(1); 672 if ((Lo 1581 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); local 1604 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); local 1886 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); local 1917 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); local 2417 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, local [all...] |
H A D | MipsLongBranch.cpp | 268 int64_t Lo = SignExtend64<16>(Offset & 0xffff); local 300 .addReg(Mips::AT).addImm(Lo); 356 .addReg(Mips::AT_64).addImm(Lo);
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/external/llvm/include/llvm/IR/ |
H A D | MDBuilder.h | 81 /// \brief Return metadata describing the range [Lo, Hi). 82 MDNode *createRange(const APInt &Lo, const APInt &Hi) { argument 83 assert(Lo.getBitWidth() == Hi.getBitWidth() && "Mismatched bitwidths!"); 85 if (Hi == Lo) 88 // Return the range [Lo, Hi). 89 Type *Ty = IntegerType::get(Context, Lo.getBitWidth()); 90 Value *Range[2] = { ConstantInt::get(Ty, Lo), ConstantInt::get(Ty, Hi) };
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 158 unsigned Lo = Imm & 0xFFFF; local 168 else if (Lo) { 169 // Both Lo and Hi have nonzero bits. 176 .addReg(TmpReg).addImm(Lo); 224 unsigned TmpReg3, Hi, Lo; local 232 if ((Lo = Remainder & 0xFFFF)) { 235 ResultReg).addReg(TmpReg3).addImm(Lo);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 101 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 106 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 127 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 128 Addr.getOperand(1).getOpcode() == SPISD::Lo)
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H A D | SparcISelLowering.h | 36 Hi, Lo, // Hi/Lo operations, typically on a global address. enumerator in enum:llvm::SPISD::__anon22425
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/external/clang/lib/CodeGen/ |
H A D | TargetInfo.cpp | 1105 /// Post merger cleanup, reduces a malformed Hi and Lo pair to 1111 /// \param Lo - The classification for the parts of the type 1117 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const; 1122 /// \param Lo - The classification for the parts of the type 1136 /// be passed in Memory then at least the classification of \arg Lo 1139 /// The \arg Lo class will be NoClass iff the argument is ignored. 1141 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will 1143 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi, 1348 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo, argument 1372 Lo 1421 classify(QualType Ty, uint64_t OffsetBase, Class &Lo, Class &Hi, bool isNamedArg) const argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | AsmPrinter.h | 346 /// EmitLabelDifference - Emit something like ".long Hi-Lo" where the size 347 /// in bytes of the directive is specified by Size and Hi/Lo specify the 349 void EmitLabelDifference(const MCSymbol *Hi, const MCSymbol *Lo, 352 /// EmitLabelOffsetDifference - Emit something like ".long Hi+Offset-Lo" 353 /// where the size in bytes of the directive is specified by Size and Hi/Lo 356 const MCSymbol *Lo, unsigned Size) const;
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 526 SDValue Lo(Hi.getNode(), 1); 527 SDValue Ops[] = { Lo, Hi }; 543 SDValue Lo(Hi.getNode(), 1); 544 SDValue Ops[] = { Lo, Hi }; 640 SDValue Lo(Hi.getNode(), 1); 641 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 648 SDValue Lo(Hi.getNode(), 1); 649 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 659 SDValue Lo(Hi.getNode(), 1); 664 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, H 696 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), local 1462 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3); local [all...] |
/external/chromium_org/third_party/skia/src/core/ |
H A D | SkMath.cpp | 162 uint32_t Lo = C + (B << 16); local 163 uint32_t Hi = A + (B >>16) + (Lo < C); 167 int32_t R = (Hi << 2) + (Lo >> 30);
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/external/skia/src/core/ |
H A D | SkMath.cpp | 162 uint32_t Lo = C + (B << 16); local 163 uint32_t Hi = A + (B >>16) + (Lo < C); 167 int32_t R = (Hi << 2) + (Lo >> 30);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.h | 43 Hi, Lo, // Hi/Lo operations, typically on a global address. enumerator in enum:llvm::HexagonISD::__anon22325
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/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DIE.h | 333 DIEDelta(const MCSymbol *Hi, const MCSymbol *Lo) argument 334 : DIEValue(isDelta), LabelHi(Hi), LabelLo(Lo) {}
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