/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInst.h | 24 // MCID is set during instruction lowering. 27 const MCInstrDesc *MCID; member in class:llvm::HexagonMCInst 34 MCInst(), MCID(0), packetStart(0), packetEnd(0) {}; 36 MCInst(), MCID(&mcid), packetStart(0), packetEnd(0) {}; 50 void setDesc(const MCInstrDesc& mcid) { MCID = &mcid; }; 51 const MCInstrDesc& getDesc(void) const { return *MCID; };
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H A D | HexagonMCInst.cpp | 33 const uint64_t F = MCID->TSFlags; 40 return (!MCID->isPseudo() && 52 const uint64_t F = MCID->TSFlags; 58 const uint64_t F = MCID->TSFlags; 64 const uint64_t F = MCID->TSFlags; 70 const uint64_t F = MCID->TSFlags; 118 const uint64_t F = MCID->TSFlags; 124 const uint64_t F = MCID->TSFlags; 130 const uint64_t F = MCID->TSFlags; 136 const uint64_t F = MCID [all...] |
/external/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 98 namespace MCID { namespace in namespace:llvm 191 return Flags & (1 << MCID::Variadic); 197 return Flags & (1 << MCID::HasOptionalDef); 204 return Flags & (1 << MCID::Pseudo); 209 return Flags & (1 << MCID::Return); 214 return Flags & (1 << MCID::Call); 221 return Flags & (1 << MCID::Barrier); 231 return Flags & (1 << MCID::Terminator); 239 return Flags & (1 << MCID::Branch); 245 return Flags & (1 << MCID [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrBuilder.h | 31 const MCInstrDesc &MCID = MI->getDesc(); local 33 if (MCID.mayLoad()) 35 if (MCID.mayStore())
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H A D | SystemZInstrInfo.cpp | 92 const MCInstrDesc &MCID = MI->getDesc(); local 93 if ((MCID.TSFlags & Flag) && 421 const MCInstrDesc &MCID = MI->getDesc(); local 422 return ((MCID.TSFlags & Flag) && 739 const MCInstrDesc &MCID = get(Opcode); local 740 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset); 758 if (MCID.TSFlags & SystemZII::Has20BitOffset)
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/external/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); local 23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; 26 unsigned Opcode = MCID.getOpcode(); 43 const MCInstrDesc &MCID = MI->getDesc(); local 44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
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H A D | ARMCodeEmitter.cpp | 101 const MCInstrDesc &MCID, 107 const MCInstrDesc &MCID) const; 281 const MCInstrDesc &MCID = MI.getDesc(); local 284 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ? 487 const MCInstrDesc &MCID = MI.getDesc(); local 489 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 823 const MCInstrDesc &MCID = MI.getDesc(); local 831 Binary |= getAddrModeSBit(MI, MCID); 850 const MCInstrDesc &MCID = MI.getDesc(); local 859 Binary |= getAddrModeSBit(MI, MCID); 1016 getMachineSoRegOpValue(const MachineInstr &MI, const MCInstrDesc &MCID, const MachineOperand &MO, unsigned OpIdx) argument 1099 const MCInstrDesc &MCID = MI.getDesc(); local 1202 const MCInstrDesc &MCID = MI.getDesc(); local 1286 const MCInstrDesc &MCID = MI.getDesc(); local 1371 const MCInstrDesc &MCID = MI.getDesc(); local [all...] |
H A D | Thumb2SizeReduction.cpp | 213 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { argument 214 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) 551 const MCInstrDesc &MCID = MI->getDesc(); local 552 if (MCID.hasOptionalDef() && 553 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) 700 const MCInstrDesc &MCID = MI->getDesc(); local 701 if (MCID.hasOptionalDef()) { 702 unsigned NumOps = MCID.getNumOperands(); 728 unsigned NumOps = MCID.getNumOperands(); 730 if (i < NumOps && MCID 764 const MCInstrDesc &MCID = MI->getDesc(); local [all...] |
H A D | MLxExpansionPass.cpp | 186 const MCInstrDesc &MCID = MI->getDesc(); local 187 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; 190 unsigned Opcode = MCID.getOpcode(); 343 const MCInstrDesc &MCID = MI->getDesc(); local 351 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; 361 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
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H A D | Thumb2ITBlockPass.cpp | 140 const MCInstrDesc &MCID = MI->getDesc(); local 142 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
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H A D | Thumb1RegisterInfo.cpp | 241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); 243 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg) 291 const MCInstrDesc &MCID = TII.get(ExtraOpc); local 292 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)) 319 const MCInstrDesc &MCID = TII.get(ARM::tRSB); 320 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 225 const MCInstrDesc &MCID) { 226 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)); 234 const MCInstrDesc &MCID, 236 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)) 247 const MCInstrDesc &MCID, 250 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); 258 const MCInstrDesc &MCID, 261 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); 269 const MCInstrDesc &MCID, 273 return BuildMI(BB, MII, DL, MCID, DestRe 223 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID) argument 232 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument 244 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument 255 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument 266 BuildMI(MachineBasicBlock &BB, MachineInstr *I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument 284 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID) argument 294 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, DebugLoc DL, const MCInstrDesc &MCID) argument 304 BuildMI(MachineBasicBlock &BB, MachineInstr *I, DebugLoc DL, const MCInstrDesc &MCID) argument 321 BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID) argument 331 BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument 343 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID, bool IsIndirect, unsigned Reg, unsigned Offset, const MDNode *MD) argument 368 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID, bool IsIndirect, unsigned Reg, unsigned Offset, const MDNode *MD) argument [all...] |
H A D | MachineInstr.h | 70 const MCInstrDesc *MCID; // Instruction descriptor. member in class:llvm::MachineInstr 112 MachineInstr(MachineFunction&, const MCInstrDesc &MCID, 257 const MCInstrDesc &getDesc() const { return *MCID; } 261 int getOpcode() const { return MCID->Opcode; } 329 return hasProperty(MCID::Variadic, Type); 335 return hasProperty(MCID::HasOptionalDef, Type); 342 return hasProperty(MCID::Pseudo, Type); 346 return hasProperty(MCID::Return, Type); 350 return hasProperty(MCID::Call, Type); 357 return hasProperty(MCID [all...] |
/external/llvm/lib/CodeGen/ |
H A D | ScoreboardHazardRecognizer.cpp | 128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local 129 if (MCID == NULL) { 133 unsigned idx = MCID->getSchedClass(); 184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local 185 assert(MCID && "The scheduler must filter non-machineinstrs"); 186 if (DAG->TII->isZeroCost(MCID->Opcode)) 193 unsigned idx = MCID->getSchedClass();
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H A D | TargetInstrInfo.cpp | 39 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, argument 42 if (OpNum >= MCID.getNumOperands()) 45 short RegClass = MCID.OpInfo[OpNum].RegClass; 46 if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) 120 const MCInstrDesc &MCID = MI->getDesc(); local 121 bool HasDef = MCID.getNumDefs(); 185 const MCInstrDesc &MCID = MI->getDesc(); local 186 if (!MCID.isCommutable()) 190 SrcOpIdx1 = MCID.getNumDefs(); 220 const MCInstrDesc &MCID local [all...] |
H A D | MachineInstr.cpp | 521 if (MCID->ImplicitDefs) 522 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 524 if (MCID->ImplicitUses) 525 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses) 534 : MCID(&tid), Parent(0), Operands(0), NumOperands(0), 538 if (unsigned NumOps = MCID->getNumOperands() + 539 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) { 551 : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0), 623 assert(MCID 1084 const MCInstrDesc &MCID = getDesc(); local [all...] |
H A D | MachineVerifier.cpp | 767 const MCInstrDesc &MCID = MI->getDesc(); local 768 if (MI->getNumOperands() < MCID.getNumOperands()) { 770 *OS << MCID.getNumOperands() << " operands expected, but " 811 const MCInstrDesc &MCID = MI->getDesc(); local 813 // The first MCID.NumDefs operands must be explicit register defines 814 if (MONum < MCID.getNumDefs()) { 815 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; 822 } else if (MONum < MCID.getNumOperands()) { 823 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; 827 !(MI->isVariadic() && MONum == MCID [all...] |
H A D | PeepholeOptimizer.cpp | 421 const MCInstrDesc &MCID = MI->getDesc(); local 422 if (MCID.getNumDefs() != 1) 441 const MCInstrDesc &MCID = MI->getDesc(); local 444 if (MCID.getNumDefs() != 1)
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.cpp | 27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local 28 if (!MCID) 94 const MCInstrDesc &MCID = TM.getInstrInfo()->get(Opcode); local 96 isLoad = MCID.mayLoad(); 97 isStore = MCID.mayStore(); 99 uint64_t TSFlags = MCID.TSFlags;
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 152 const MCInstrDesc &MCID = MI->getDesc(); local 154 if (MCID.mayLoad()) 156 if (MCID.mayStore())
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGFast.cpp | 257 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local 258 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { 259 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { 264 if (MCID.isCommutable()) 435 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local 436 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); 437 unsigned NumRes = MCID.getNumDefs(); 438 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { 513 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); local 514 if (!MCID [all...] |
H A D | InstrEmitter.cpp | 308 const MCInstrDesc &MCID = MIB->getDesc(); local 309 bool isOptDef = IIOpNum < MCID.getNumOperands() && 310 MCID.OpInfo[IIOpNum].isOptionalDef(); 345 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; 808 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); 809 UsedRegs.append(MCID.getImplicitUses(), 810 MCID.getImplicitUses() + MCID.getNumImplicitUses());
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H A D | ScheduleDAGSDNodes.cpp | 299 const MCInstrDesc &MCID = TII->get(Opc); 300 if (MCID.mayLoad()) 434 const MCInstrDesc &MCID = TII->get(Opc); 435 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { 436 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { 441 if (MCID.isCommutable())
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/external/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 99 const MCInstrDesc &MCID = get(Opc); local 100 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
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/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 445 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); local 447 if (MCID.hasDelaySlot() && Options.isReorder()) { 460 if (MCID.mayLoad() || MCID.mayStore()) { 463 for (unsigned i = 0; i < MCID.getNumOperands(); i++) { 464 const MCOperandInfo &OpInfo = MCID.OpInfo[i]; 472 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true); 482 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false); 486 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
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