Searched refs:RRS (Results 1 - 5 of 5) sorted by relevance
/external/valgrind/main/none/tests/s390x/ |
H A D | opcodes.h | 47 #define RRS(op1,r1,r2,b4,d4,m3,u0,op2) \ macro 132 #define CGRB(r1,r2,b4,d4,m3) RRS(ec,r1,r2,b4,d4,m3,0,e4) 153 #define CLGRB(r1,r2,b4,d4,m3) RRS(ec,r1,r2,b4,d4,m3,0,e5) 166 #define CLRB(r1,r2,b4,d4,m3) RRS(ec,r1,r2,b4,d4,m3,0,f7) 171 #define CRB(r1,r2,b4,d4,m3) RRS(ec,r1,r2,b4,d4,m3,0,f6)
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/external/valgrind/main/VEX/priv/ |
H A D | host_arm_defs.h | 139 } RRS; member in union:__anon27492::__anon27493
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H A D | guest_s390_toIR.c | 12919 } RRS; member in union:__anon27388 13705 case 0xec00000000e4ULL: s390_format_RRS(s390_irgen_CGRB, ovl.fmt.RRS.r1, 13706 ovl.fmt.RRS.r2, ovl.fmt.RRS.b4, 13707 ovl.fmt.RRS.d4, ovl.fmt.RRS.m3); 13709 case 0xec00000000e5ULL: s390_format_RRS(s390_irgen_CLGRB, ovl.fmt.RRS.r1, 13710 ovl.fmt.RRS.r2, ovl.fmt.RRS.b4, 13711 ovl.fmt.RRS [all...] |
H A D | host_arm_defs.c | 230 am->ARMam1.RRS.base = base; 231 am->ARMam1.RRS.index = index; 232 am->ARMam1.RRS.shift = shift; 246 ppHRegARM(am->ARMam1.RRS.base); 248 ppHRegARM(am->ARMam1.RRS.index); 249 vex_printf(",%u)", am->ARMam1.RRS.shift); 262 // addHRegUse(u, HRmRead, am->ARMam1.RRS.base); 263 // addHRegUse(u, HRmRead, am->ARMam1.RRS.index);
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H A D | host_arm_isel.c | 661 toBool( hregClass(am->ARMam1.RRS.base) == HRcInt32 662 && hregIsVirtual(am->ARMam1.RRS.base) 663 && hregClass(am->ARMam1.RRS.index) == HRcInt32 664 && hregIsVirtual(am->ARMam1.RRS.index) 665 && am->ARMam1.RRS.shift >= 0 666 && am->ARMam1.RRS.shift <= 3 ); 684 /* FIXME: add RRS matching */
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