/external/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 29 namespace RegState { namespace in namespace:llvm 69 flags & RegState::Define, 70 flags & RegState::Implicit, 71 flags & RegState::Kill, 72 flags & RegState::Dead, 73 flags & RegState::Undef, 74 flags & RegState::EarlyClobber, 76 flags & RegState::Debug, 77 flags & RegState::InternalRead)); 237 .addReg(DestReg, RegState [all...] |
/external/llvm/lib/Target/R600/ |
H A D | AMDGPUIndirectAddressing.cpp | 122 MOV.addReg(DstReg, RegState::Define | RegState::Implicit); 273 .addReg(Reg, RegState::Implicit); 310 Mov.addReg(IndirectReg, RegState::Implicit | RegState::Kill); 311 Mov.addReg(LiveAddressRegisterMap[Address], RegState::Implicit);
|
H A D | SIInstrInfo.cpp | 166 Builder.addReg(DestReg, RegState::Define | RegState::Implicit); 204 MIB.addReg(DstReg, RegState::Define);
|
H A D | SILowerControlFlow.cpp | 384 .addReg(AMDGPU::M0, RegState::Implicit) 385 .addReg(Vec, RegState::Implicit); 401 .addReg(TRI->getSubReg(Dst, AMDGPU::sub0) + Off, RegState::Define) 403 .addReg(AMDGPU::M0, RegState::Implicit) 404 .addReg(Dst, RegState::Implicit);
|
H A D | R600InstrInfo.cpp | 70 RegState::Define | RegState::Implicit); 84 MIB.addReg(DstReg, RegState::Define); 727 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 742 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 949 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); 1055 RegState::Implicit | RegState::Kill); 1073 RegState::Implicit | RegState [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | SIInstrInfo.cpp | 56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
|
H A D | R600InstrInfo.cpp | 59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) 63 .addReg(DestReg, RegState::Define | RegState::Implicit); 82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); 281 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 291 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 463 MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
|
H A D | R600ISelLowering.cpp | 173 .addReg(t0, RegState::Implicit) 174 .addReg(t1, RegState::Implicit); 195 .addReg(t0, RegState::Implicit) 196 .addReg(t1, RegState::Implicit); 215 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 229 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
|
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | SIInstrInfo.cpp | 56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
|
H A D | R600InstrInfo.cpp | 59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) 63 .addReg(DestReg, RegState::Define | RegState::Implicit); 82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); 281 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 291 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 463 MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
|
H A D | R600ISelLowering.cpp | 173 .addReg(t0, RegState::Implicit) 174 .addReg(t1, RegState::Implicit); 195 .addReg(t0, RegState::Implicit) 196 .addReg(t1, RegState::Implicit); 215 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); 229 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
|
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 146 .addReg(SrcReg, RegState::Kill) 155 .addReg(SrcReg, RegState::Kill) 164 .addReg(SrcReg, RegState::Kill) 168 .addReg(DstReg, RegState::Kill) 421 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 506 .addReg(PPC::R0, RegState::Kill) 512 .addReg(PPC::R12, RegState::Kill) 515 .addReg(PPC::R0, RegState::Kill) 516 .addReg(PPC::R12, RegState::Kill); 519 .addReg(PPC::R1, RegState [all...] |
H A D | PPCRegisterInfo.cpp | 318 .addReg(NegSizeReg1, RegState::Kill); 323 .addReg(Reg, RegState::Kill) 343 .addReg(NegSizeReg1, RegState::Kill); 348 .addReg(Reg, RegState::Kill) 398 .addReg(Reg1, RegState::Kill) 405 .addReg(Reg, RegState::Kill), 443 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 448 .addReg(Reg, RegState::Kill); 472 .addReg(Reg, RegState::Kill), 499 .addReg(Reg, RegState [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 1227 .addReg(Op0, Op0IsKill * RegState::Kill); 1230 .addReg(Op0, Op0IsKill * RegState::Kill); 1247 .addReg(Op0, Op0IsKill * RegState::Kill) 1248 .addReg(Op1, Op1IsKill * RegState::Kill); 1251 .addReg(Op0, Op0IsKill * RegState::Kill) 1252 .addReg(Op1, Op1IsKill * RegState::Kill); 1269 .addReg(Op0, Op0IsKill * RegState::Kill) 1270 .addReg(Op1, Op1IsKill * RegState::Kill) 1271 .addReg(Op2, Op2IsKill * RegState::Kill); 1274 .addReg(Op0, Op0IsKill * RegState [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | Thumb2InstrInfo.cpp | 199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 205 MIB.addReg(DestReg, RegState::ImplicitDefine); 244 .addReg(BaseReg, RegState::Kill) 245 .addReg(DestReg, RegState::Kill) 250 .addReg(DestReg, RegState::Kill) 251 .addReg(BaseReg, RegState::Kill) 316 .addReg(BaseReg, RegState::Kill)
|
H A D | ARMBaseInstrInfo.cpp | 985 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 986 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 995 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); 996 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); 1000 MIB.addReg(DestReg, RegState::ImplicitDefine); 1029 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 1030 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 1031 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 1033 MIB.addReg(DestReg, RegState::ImplicitDefine); 1049 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState [all...] |
H A D | Thumb1RegisterInfo.cpp | 123 .addReg(LdReg, RegState::Kill).setMIFlags(MIFlags); 135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); 137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); 245 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); 248 .addReg(BaseReg, RegState::Kill)) 293 .addReg(DestReg, RegState::Kill) 321 .addReg(DestReg, RegState::Kill)); 522 .addReg(ARM::R12, RegState::Define) 523 .addReg(Reg, RegState::Kill)); 552 addReg(Reg, RegState [all...] |
H A D | ARMExpandPseudoInsts.cpp | 391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 522 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 524 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 526 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 528 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 570 MIB.addReg(DstReg, RegState [all...] |
H A D | ARMFrameLowering.cpp | 300 .addReg(ARM::SP, RegState::Kill) 310 .addReg(ARM::SP, RegState::Kill)); 313 .addReg(ARM::R4, RegState::Kill) 316 .addReg(ARM::R4, RegState::Kill)); 464 addReg(JumpTarget.getReg(), RegState::Kill); 712 .addReg(ARM::SP, RegState::Define) 785 .addReg(ARM::R4, RegState::Kill) 811 .addReg(ARM::R4, RegState::Kill).addImm(16) 813 .addReg(SupReg, RegState::ImplicitKill)); 829 .addReg(SupReg, RegState [all...] |
H A D | ARMFastISel.cpp | 311 .addReg(Op0, Op0IsKill * RegState::Kill)); 314 .addReg(Op0, Op0IsKill * RegState::Kill)); 331 .addReg(Op0, Op0IsKill * RegState::Kill) 332 .addReg(Op1, Op1IsKill * RegState::Kill)); 335 .addReg(Op0, Op0IsKill * RegState::Kill) 336 .addReg(Op1, Op1IsKill * RegState::Kill)); 354 .addReg(Op0, Op0IsKill * RegState::Kill) 355 .addReg(Op1, Op1IsKill * RegState::Kill) 356 .addReg(Op2, Op2IsKill * RegState::Kill)); 359 .addReg(Op0, Op0IsKill * RegState [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 174 .addReg(ScratchReg, RegState::Kill); 180 .addReg(ScratchReg, RegState::Kill); 185 .addReg(ScratchReg, RegState::Kill);
|
/external/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.cpp | 94 MIB.addReg(DestReg, RegState::Define); 281 MIB2.addReg(Mips::SP, RegState::Kill); 284 MIB3.addReg(Reg2, RegState::Kill); 287 MIB4.addReg(Reg1, RegState::Kill); 408 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill) 413 .addReg(Reg, RegState::Kill);
|
H A D | MipsSERegisterInfo.cpp | 126 .addReg(Reg, RegState::Kill);
|
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZElimCompare.cpp | 208 .addReg(SystemZ::CC, RegState::ImplicitDefine); 222 .addReg(SystemZ::CC, RegState::ImplicitDefine); 412 .addReg(SystemZ::CC, RegState::ImplicitDefine);
|
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64FrameLowering.cpp | 230 MIB.addReg(JumpTarget.getReg(), RegState::Kill); 472 StLow = RegState::Define; 473 StHigh = RegState::Define; 487 State = RegState::Define;
|