Searched refs:RegWidth (Results 1 - 8 of 8) sorted by relevance

/external/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp66 template<unsigned RegWidth>
68 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth);
84 unsigned RegWidth);
92 template<unsigned RegWidth>
94 return SelectTSTBOperand(N, FixedPos, RegWidth);
97 bool SelectTSTBOperand(SDValue N, SDValue &FixedPos, unsigned RegWidth);
117 unsigned RegWidth) {
141 if (FBits == 0 || FBits > RegWidth) return false;
179 uint32_t RegWidth = N.getValueType().getSizeInBits(); local
184 if (!A64Imms::isLogicalImm(RegWidth, C
116 SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned RegWidth) argument
343 SelectTSTBOperand(SDValue N, SDValue &FixedPos, unsigned RegWidth) argument
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/external/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp946 bool A64Imms::isLogicalImm(unsigned RegWidth, uint64_t Imm, uint32_t &Bits) { argument
955 for (RepeatWidth = RegWidth; RepeatWidth > 1; RepeatWidth /= 2) {
964 for (unsigned i = RepeatWidth; i < RegWidth; i += RepeatWidth) {
979 Rotation = RegWidth == 64 ? CountLeadingOnes_64(Imm)
1021 bool A64Imms::isLogicalImmBits(unsigned RegWidth, uint32_t Bits, argument
1029 if (RegWidth == 32 && N != 0) return false;
1062 for (unsigned i = 1; i < RegWidth / Width; ++i) {
1070 bool A64Imms::isMOVZImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) { argument
1072 if (RegWidth == 32 && (Value & ~0xffffffffULL))
1075 for (int i = 0; i < RegWidth;
1087 isMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) argument
1101 isOnlyMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift) argument
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H A DAArch64BaseInfo.h1062 bool isLogicalImm(unsigned RegWidth, uint64_t Imm, uint32_t &Bits);
1063 bool isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t &Imm);
1065 bool isMOVZImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift);
1066 bool isMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift);
1070 bool isOnlyMOVNImm(int RegWidth, uint64_t Value, int &UImm16, int &Shift);
/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp330 template<unsigned RegWidth> bool isBitfieldWidth() const {
336 return CE->getValue() >= 1 && CE->getValue() <= RegWidth;
339 template<int RegWidth>
346 return CE->getValue() >= 1 && CE->getValue() <= RegWidth;
402 template<unsigned RegWidth> bool isLogicalImm() const {
409 return A64Imms::isLogicalImm(RegWidth, CE->getValue(), Bits);
412 template<unsigned RegWidth> bool isLogicalImmMOV() const {
413 if (!isLogicalImm<RegWidth>()) return false;
420 return !A64Imms::isMOVZImm(RegWidth, CE->getValue(), UImm16, Shift)
421 && !A64Imms::isMOVNImm(RegWidth, C
561 isMoveWideImm(unsigned RegWidth, const AArch64MCExpr::VariantKind *PermittedModifiers, unsigned NumModifiers) const argument
1857 int64_t RegWidth = 0; local
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/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp122 template<unsigned RegWidth> void
126 unsigned LSB = ImmROp.getImm() == 0 ? 0 : RegWidth - ImmROp.getImm();
231 template<unsigned RegWidth> void
236 A64Imms::isLogicalImmBits(RegWidth, MO.getImm(), Val);
H A DAArch64InstPrinter.h57 template<unsigned RegWidth>
89 template<unsigned RegWidth>
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp116 template<int RegWidth>
122 template<int RegWidth>
418 template<int RegWidth>
426 if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
433 template<int RegWidth>
439 if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
/external/llvm/include/llvm/Target/
H A DTargetLowering.h643 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); local
644 return (BitWidth + RegWidth - 1) / RegWidth;

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