| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| H A D | Execution.cpp | 50 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
53 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, argument
64 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, argument
75 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, argument
86 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, argument
97 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, argument
101 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal);
104 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal);
114 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
119 assert(Src1
136 executeICMP_EQ(GenericValue Src1, GenericValue Src2, Type *Ty) argument
150 executeICMP_NE(GenericValue Src1, GenericValue Src2, Type *Ty) argument
164 executeICMP_ULT(GenericValue Src1, GenericValue Src2, Type *Ty) argument
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | R600ExpandSpecialInstrs.cpp | 98 unsigned Src1 = 0; local
102 Src1 = MI.getOperand(2).getReg();
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
153 .addReg(Src1)
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | R600ExpandSpecialInstrs.cpp | 98 unsigned Src1 = 0; local
102 Src1 = MI.getOperand(2).getReg();
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
153 .addReg(Src1)
|
| /external/llvm/lib/Target/R600/ |
| H A D | R600ExpandSpecialInstrs.cpp | 198 unsigned Src1 = BMI->getOperand( local
202 (void) Src1;
204 (TRI.getEncodingValue(Src1) & 0xff) < 127)
205 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
249 unsigned Src1 = 0; local
255 Src1 = MI.getOperand(Src1Idx).getReg();
261 Src1 = TRI.getSubReg(Src1, SubRegIndex);
266 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
301 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
[all...] |
| H A D | R600InstrInfo.cpp | 1179 MachineOperand &Src1 = MI->getOperand(
1182 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 159 MachineOperand &Src1 = MI->getOperand(1); local
161 if (Src1.getImm() != 0)
176 MachineOperand &Src1 = MI->getOperand(1); local
181 unsigned SrcReg = Src1.getReg();
|
| H A D | HexagonISelDAGToDAG.cpp | 1328 SDNode* Src1 = N->getOperand(0).getNode(); local
1329 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
1330 || Src1->getValueType(0) != MVT::i32) {
1338 Src1->getOperand(0),
1339 Src1->getOperand(1));
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 2895 SDValue Src1 = getValue(I.getOperand(0)); local
2904 EVT SrcVT = Src1.getValueType();
2908 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2919 // First check for Src1 in low and Src2 in high
2924 VT, Src1, Src2));
2927 // Then check for Src2 in low and Src1 in high
2932 VT, Src2, Src1));
2939 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2945 MOps1[0] = Src1;
2948 Src1
[all...] |
| H A D | LegalizeVectorTypes.cpp | 1107 SDValue Src1 = N->getOperand(2); local
1134 SDValue LoOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoOpVT, Src1, Zero);
1137 SDValue HiOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiOpVT, Src1, LoElts);
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 6660 unsigned Src1 = MI->getOperand(1).getReg(); local
6675 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
|