Searched refs:TCG_AREG0 (Results 1 - 18 of 18) sorted by relevance

/external/qemu/tcg/sparc/
H A Dtcg-target.h134 #define TCG_AREG0 TCG_REG_G2 macro
136 #define TCG_AREG0 TCG_REG_G5 macro
138 #define TCG_AREG0 TCG_REG_G6 macro
H A Dtcg-target.c781 tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
811 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
814 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
993 tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
1026 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1029 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1159 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1162 tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
/external/qemu/tcg/ppc64/
H A Dtcg-target.h106 #define TCG_AREG0 TCG_REG_R27 macro
H A Dtcg-target.c583 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
601 tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0));
/external/qemu/tcg/i386/
H A Dtcg-target.h119 #define TCG_AREG0 TCG_REG_R14 macro
123 #define TCG_AREG0 TCG_REG_EBP macro
H A Dtcg-target.c1028 tcg_out_modrm_sib_offset(s, OPC_LEA + P_REXW, r1, TCG_AREG0, r1, 0,
/external/qemu/tcg/arm/
H A Dtcg-target.h80 TCG_AREG0 = TCG_REG_R7, enumerator in enum:__anon25983
H A Dtcg-target.c997 tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
1218 TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
/external/qemu/tcg/ppc/
H A Dtcg-target.h96 #define TCG_AREG0 TCG_REG_R27 macro
H A Dtcg-target.c564 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
760 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
/external/qemu/tcg/x86_64/
H A Dtcg-target.h89 #define TCG_AREG0 TCG_REG_R14 macro
H A Dtcg-target.c596 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
791 tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
/external/qemu/tcg/hppa/
H A Dtcg-target.h106 #define TCG_AREG0 TCG_REG_R17 macro
H A Dtcg-target.c914 tcg_out_arith(s, r1, r1, TCG_AREG0, INSN_ADDL);
/external/qemu/
H A Dtranslate-all.c89 tcg_set_frame(&tcg_ctx, TCG_AREG0, offsetof(CPUState, temp_buf),
/external/qemu/target-mips/
H A Dtranslate.c8538 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
8541 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
8544 cpu_PC = tcg_global_mem_new(TCG_AREG0,
8547 cpu_HI[i] = tcg_global_mem_new(TCG_AREG0,
8550 cpu_LO[i] = tcg_global_mem_new(TCG_AREG0,
8553 cpu_ACX[i] = tcg_global_mem_new(TCG_AREG0,
8557 cpu_dspctrl = tcg_global_mem_new(TCG_AREG0,
8560 bcond = tcg_global_mem_new(TCG_AREG0,
8562 btarget = tcg_global_mem_new(TCG_AREG0,
8564 hflags = tcg_global_mem_new_i32(TCG_AREG0,
[all...]
/external/qemu/target-i386/
H A Dtranslate.c7583 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7584 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
7586 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src),
7588 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
7590 cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_tmp),
/external/qemu/target-arm/
H A Dtranslate.c117 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
120 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
124 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
126 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
128 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
131 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
133 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,

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