Searched refs:VT (Results 1 - 25 of 167) sorted by relevance

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/external/llvm/lib/Target/X86/Utils/
H A DX86ShuffleDecode.h38 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
40 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
42 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
46 /// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicates
49 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
52 /// and punpckh*. VT indicates the type of the vector allowing it to handle
54 void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
57 /// and punpckl*. VT indicates the type of the vector allowing it to handle
59 void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
62 void DecodeVPERM2X128Mask(MVT VT, unsigne
[all...]
H A DX86ShuffleDecode.cpp64 void DecodePALIGNRMask(MVT VT, unsigned Imm, argument
66 unsigned NumElts = VT.getVectorNumElements();
67 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8);
69 unsigned NumLanes = VT.getSizeInBits() / 128;
83 /// VT indicates the type of the vector allowing it to handle different
85 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument
86 unsigned NumElts = VT.getVectorNumElements();
88 unsigned NumLanes = VT.getSizeInBits() / 128;
101 void DecodePSHUFHWMask(MVT VT, unsigned Imm, argument
103 unsigned NumElts = VT
117 DecodePSHUFLWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
136 DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
158 DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) argument
178 DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) argument
195 DecodeVPERM2X128Mask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument
[all...]
/external/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp103 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x]; local
105 setOperationAction(ISD::ADD, VT, Expand);
106 setOperationAction(ISD::AND, VT, Expand);
107 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
108 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
109 setOperationAction(ISD::MUL, VT, Expand);
110 setOperationAction(ISD::OR, VT, Expand);
111 setOperationAction(ISD::SHL, VT, Expand);
112 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
113 setOperationAction(ISD::SRL, VT, Expan
215 EVT VT = Op.getValueType(); local
255 EVT VT = Op.getValueType(); local
267 EVT VT = Op.getValueType(); local
282 EVT VT = Op.getValueType(); local
343 EVT VT = Op.getValueType(); local
[all...]
H A DR600RegisterInfo.h44 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
H A DSIRegisterInfo.h43 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp106 EVT VT = Op.getValueType(); local
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, O
154 EVT VT = Op.getValueType(); local
167 EVT VT = Op.getValueType(); local
184 EVT VT = Op.getValueType(); local
[all...]
H A DSIRegisterInfo.cpp53 MVT VT) const
55 switch(VT.SimpleTy) {
H A DR600ISelLowering.cpp277 EVT VT = Op.getValueType(); local
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
288 return LowerImplicitParameter(DAG, VT, DL, 0);
290 return LowerImplicitParameter(DAG, VT, DL, 1);
292 return LowerImplicitParameter(DAG, VT, DL, 2);
294 return LowerImplicitParameter(DAG, VT, DL, 3);
296 return LowerImplicitParameter(DAG, VT, DL, 4);
298 return LowerImplicitParameter(DAG, VT, DL, 5);
300 return LowerImplicitParameter(DAG, VT, DL, 6);
302 return LowerImplicitParameter(DAG, VT, D
357 LowerImplicitParameter(SelectionDAG &DAG, EVT VT, DebugLoc DL, unsigned DwordOffset) const argument
377 EVT VT = Op.getValueType(); local
390 EVT VT = Op.getValueType(); local
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H A DSIRegisterInfo.h48 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
H A DAMDILISelLowering.cpp106 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x]; local
110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
111 setOperationAction(ISD::SUBE, VT, Expand);
112 setOperationAction(ISD::SUBC, VT, Expand);
113 setOperationAction(ISD::ADDE, VT, Expand);
114 setOperationAction(ISD::ADDC, VT, Expand);
115 setOperationAction(ISD::BRCOND, VT, Custom);
116 setOperationAction(ISD::BR_JT, VT, Expand);
117 setOperationAction(ISD::BRIND, VT, Expand);
119 setOperationAction(ISD::SREM, VT, Expan
127 MVT::SimpleValueType VT = (MVT::SimpleValueType)FloatTypes[x]; local
142 MVT::SimpleValueType VT = (MVT::SimpleValueType)IntTypes[x]; local
163 MVT::SimpleValueType VT = (MVT::SimpleValueType)VectorTypes[ii]; local
356 EVT VT = Op.getValueType(); local
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp106 EVT VT = Op.getValueType(); local
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, O
154 EVT VT = Op.getValueType(); local
167 EVT VT = Op.getValueType(); local
184 EVT VT = Op.getValueType(); local
[all...]
H A DSIRegisterInfo.cpp53 MVT VT) const
55 switch(VT.SimpleTy) {
H A DR600ISelLowering.cpp277 EVT VT = Op.getValueType(); local
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
288 return LowerImplicitParameter(DAG, VT, DL, 0);
290 return LowerImplicitParameter(DAG, VT, DL, 1);
292 return LowerImplicitParameter(DAG, VT, DL, 2);
294 return LowerImplicitParameter(DAG, VT, DL, 3);
296 return LowerImplicitParameter(DAG, VT, DL, 4);
298 return LowerImplicitParameter(DAG, VT, DL, 5);
300 return LowerImplicitParameter(DAG, VT, DL, 6);
302 return LowerImplicitParameter(DAG, VT, D
357 LowerImplicitParameter(SelectionDAG &DAG, EVT VT, DebugLoc DL, unsigned DwordOffset) const argument
377 EVT VT = Op.getValueType(); local
390 EVT VT = Op.getValueType(); local
[all...]
H A DSIRegisterInfo.h48 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
H A DAMDILISelLowering.cpp106 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x]; local
110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
111 setOperationAction(ISD::SUBE, VT, Expand);
112 setOperationAction(ISD::SUBC, VT, Expand);
113 setOperationAction(ISD::ADDE, VT, Expand);
114 setOperationAction(ISD::ADDC, VT, Expand);
115 setOperationAction(ISD::BRCOND, VT, Custom);
116 setOperationAction(ISD::BR_JT, VT, Expand);
117 setOperationAction(ISD::BRIND, VT, Expand);
119 setOperationAction(ISD::SREM, VT, Expan
127 MVT::SimpleValueType VT = (MVT::SimpleValueType)FloatTypes[x]; local
142 MVT::SimpleValueType VT = (MVT::SimpleValueType)IntTypes[x]; local
163 MVT::SimpleValueType VT = (MVT::SimpleValueType)VectorTypes[ii]; local
356 EVT VT = Op.getValueType(); local
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/external/llvm/include/llvm/Target/
H A DTargetLowering.h176 virtual bool shouldSplitVectorElementType(EVT /*VT*/) const { return false; }
208 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
244 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
245 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
257 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
258 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
264 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
265 return RepRegClassCostForVT[VT.SimpleTy];
271 bool isTypeLegal(EVT VT) const {
272 assert(!VT
291 setTypeAction(MVT VT, LegalizeTypeAction Action) argument
930 addRegisterClass(MVT VT, const TargetRegisterClass *RC) argument
958 setOperationAction(unsigned Op, MVT VT, LegalizeAction Action) argument
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/external/llvm/lib/CodeGen/
H A DCallingConvLower.cpp72 MVT ArgVT = Ins[i].VT;
90 MVT VT = Outs[i].VT; local
92 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
104 MVT VT = Outs[i].VT; local
106 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
109 << EVT(VT)
158 MVT VT = Ins[i].VT; local
172 AnalyzeCallResult(MVT VT, CCAssignFn Fn) argument
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/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.h25 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
35 EVT VT) const {
39 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
40 if (VT == MVT::Untyped)
44 return TargetLowering::getRepRegClassFor(VT);
/external/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h349 SDVTList getVTList(EVT VT);
358 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false);
359 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false);
360 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false);
362 SDValue getTargetConstant(uint64_t Val, EVT VT) { argument
363 return getConstant(Val, VT, true);
365 SDValue getTargetConstant(const APInt &Val, EVT VT) { argument
366 return getConstant(Val, VT, true);
368 SDValue getTargetConstant(const ConstantInt &Val, EVT VT) { argument
369 return getConstant(Val, VT, tru
376 getTargetConstantFP(double Val, EVT VT) argument
379 getTargetConstantFP(const APFloat& Val, EVT VT) argument
382 getTargetConstantFP(const ConstantFP &Val, EVT VT) argument
388 getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset = 0, unsigned char TargetFlags = 0) argument
394 getTargetFrameIndex(int FI, EVT VT) argument
399 getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags = 0) argument
405 getTargetConstantPool(const Constant *C, EVT VT, unsigned Align = 0, int Offset = 0, unsigned char TargetFlags = 0) argument
413 getTargetConstantPool(MachineConstantPoolValue *C, EVT VT, unsigned Align = 0, int Offset = 0, unsigned char TargetFlags=0) argument
435 getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset = 0, unsigned char TargetFlags = 0) argument
464 getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT) argument
473 getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT, SDValue Glue) argument
539 getUNDEF(EVT VT) argument
545 getGLOBAL_OFFSET_TABLE(EVT VT) argument
607 getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond) argument
620 getSelect(SDLoc DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS) argument
951 EVTToAPFloatSemantics(EVT VT) argument
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H A DValueTypes.h423 /// Return true if this has more bits than VT.
424 bool bitsGT(MVT VT) const {
425 return getSizeInBits() > VT.getSizeInBits();
428 /// Return true if this has no less bits than VT.
429 bool bitsGE(MVT VT) const {
430 return getSizeInBits() >= VT.getSizeInBits();
433 /// Return true if this has less bits than VT.
434 bool bitsLT(MVT VT) const {
435 return getSizeInBits() < VT.getSizeInBits();
438 /// Return true if this has no more bits than VT
480 getVectorVT(MVT VT, unsigned NumElements) argument
591 getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements) argument
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/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp95 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
96 unsigned PPCMaterializeInt(const Constant *C, MVT VT);
117 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) { argument
119 if (VT != MVT::f32 && VT != MVT::f64)
126 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
132 (VT == MVT::f32) ? 4 : 8, Align);
141 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
245 unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT) { argument
247 if (VT !
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/external/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.cpp81 EVT ArgVT = Ins[i].VT;
117 EVT VT = Outs[i].VT; local
119 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this, -1, -1, false)){
121 << VT.getEVTString() << "\n";
147 EVT ArgVT = Outs[i].VT;
185 EVT VT = Ins[i].VT; local
187 if (Fn(i, VT, V
197 AnalyzeCallResult(EVT VT, Hexagon_CCAssignFn Fn) argument
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
263 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
336 /// legalization or if the specified VT is legal.
337 bool isTypeLegal(const EVT &VT) { argument
339 return TLI.isTypeLegal(VT);
344 EVT getSetCCResultType(EVT VT) const {
345 return TLI.getSetCCResultType(*DAG.getContext(), VT);
587 EVT VT = N0.getValueType(); local
592 DAG.FoldConstantArithmetic(Opc, VT,
595 return DAG.getNode(Opc, DL, VT, N
719 EVT VT = Load->getValueType(0); local
1364 EVT VT = N0.getValueType(); local
1388 EVT VT = N0.getValueType(); local
1558 EVT VT = N0.getValueType(); local
1615 tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT, SelectionDAG &DAG, bool LegalOperations, bool LegalTypes) argument
1643 EVT VT = N0.getValueType(); local
1734 EVT VT = N0.getValueType(); local
1793 EVT VT = N0.getValueType(); local
1909 EVT VT = N->getValueType(0); local
1993 EVT VT = N->getValueType(0); local
2045 EVT VT = N->getValueType(0); local
2087 EVT VT = N->getValueType(0); local
2139 EVT VT = N->getValueType(0); local
2177 EVT VT = N->getValueType(0); local
2363 EVT VT = N0.getValueType(); local
2485 EVT VT = N1.getValueType(); local
2583 EVT VT = Vector->getValueType(0); local
3099 EVT VT = N1.getValueType(); local
3273 EVT VT = LHS.getValueType(); local
3415 EVT VT = N0.getValueType(); local
3620 EVT VT = N0.getValueType(); local
3750 EVT VT = N0.getValueType(); local
3895 EVT VT = N0.getValueType(); local
4087 EVT VT = N->getValueType(0); local
4097 EVT VT = N->getValueType(0); local
4107 EVT VT = N->getValueType(0); local
4117 EVT VT = N->getValueType(0); local
4127 EVT VT = N->getValueType(0); local
4142 EVT VT = N->getValueType(0); local
4246 EVT VT = LHS.getValueType(); local
4394 EVT VT = N->getValueType(0); local
4651 EVT VT = N->getValueType(0); local
4923 EVT VT = N->getValueType(0); local
5127 EVT VT = N->getValueType(0); local
5288 EVT VT = N->getValueType(0); local
5397 EVT VT = N->getValueType(0); local
5574 CombineConsecutiveLoads(SDNode *N, EVT VT) argument
5608 EVT VT = N->getValueType(0); local
5756 EVT VT = N->getValueType(0); local
5776 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, local
5853 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); local
5862 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, local
5900 EVT VT = N->getValueType(0); local
6110 EVT VT = N->getValueType(0); local
6201 EVT VT = N->getValueType(0); local
6266 EVT VT = N->getValueType(0); local
6340 EVT VT = N->getValueType(0); local
6394 EVT VT = N->getValueType(0); local
6408 EVT VT = N->getValueType(0); local
6456 EVT VT = N->getValueType(0); local
6513 EVT VT = N->getValueType(0); local
6557 EVT VT = N->getValueType(0); local
6569 EVT VT = N->getValueType(0); local
6582 EVT VT = N->getValueType(0); local
6615 EVT VT = N->getValueType(0); local
6631 EVT VT = N->getValueType(0); local
6678 EVT VT = N->getValueType(0); local
6722 EVT VT = N->getValueType(0); local
6734 EVT VT = N->getValueType(0); local
6746 EVT VT = N->getValueType(0); local
6758 EVT VT = N->getValueType(0); local
6981 EVT VT; local
7028 EVT VT; local
7259 EVT VT; local
7648 EVT VT = Value.getValueType(); local
7771 EVT VT = LD->getMemoryVT(); local
8647 EVT VT = InVec.getValueType(); local
8866 EVT VT = N->getValueType(0); local
9033 EVT VT = N->getValueType(0); local
9278 EVT VT = N->getValueType(0); local
9329 EVT VT = N->getValueType(0); local
9481 EVT VT = N->getValueType(0); local
9561 EVT VT = LHSOp.getValueType(); local
10059 SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, SDLoc DL, bool foldBooleans) argument
[all...]
H A DSelectionDAG.cpp78 bool ConstantFPSDNode::isValueValidForType(EVT VT, argument
80 assert(VT.isFloatingPoint() && "Can only convert between FP types");
85 (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT),
669 EVT VT = cast<VTSDNode>(N)->getVT(); local
670 if (VT.isExtended()) {
671 Erased = ExtendedValueTypeNodes.erase(VT);
673 Erased = ValueTypeNodes[VT.getSimpleVT().SimpleTy] != 0;
674 ValueTypeNodes[VT.getSimpleVT().SimpleTy] = 0;
789 EVT VT = N->getValueType(0); local
791 assert(!VT
917 getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) argument
923 getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) argument
929 getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) argument
935 getZeroExtendInReg(SDValue Op, SDLoc DL, EVT VT) argument
949 getNOT(SDLoc DL, SDValue Val, EVT VT) argument
956 getConstant(uint64_t Val, EVT VT, bool isT) argument
964 getConstant(const APInt &Val, EVT VT, bool isT) argument
968 getConstant(const ConstantInt &Val, EVT VT, bool isT) argument
1019 getConstantFP(const APFloat& V, EVT VT, bool isTarget) argument
1023 getConstantFP(const ConstantFP& V, EVT VT, bool isTarget) argument
1057 getConstantFP(double Val, EVT VT, bool isTarget) argument
1074 getGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t Offset, bool isTargetGA, unsigned char TargetFlags) argument
1117 getFrameIndex(int FI, EVT VT, bool isTarget) argument
1132 getJumpTable(int JTI, EVT VT, bool isTarget, unsigned char TargetFlags) argument
1152 getConstantPool(const Constant *C, EVT VT, unsigned Alignment, int Offset, bool isTarget, unsigned char TargetFlags) argument
1180 getConstantPool(MachineConstantPoolValue *C, EVT VT, unsigned Alignment, int Offset, bool isTarget, unsigned char TargetFlags) argument
1207 getTargetIndex(int Index, EVT VT, int64_t Offset, unsigned char TargetFlags) argument
1239 getValueType(EVT VT) argument
1253 getExternalSymbol(const char *Sym, EVT VT) argument
1261 getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags) argument
1299 getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, const int *Mask) argument
1389 getConvertRndSat(EVT VT, SDLoc dl, SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code) argument
1413 getRegister(unsigned RegNo, EVT VT) argument
1457 getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset, bool isTarget, unsigned char TargetFlags) argument
1527 CreateStackTemporary(EVT VT, unsigned minAlign) argument
1556 FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, SDLoc dl) argument
1922 EVT VT = LD->getMemoryVT(); local
1990 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); local
2129 EVT VT = Op.getValueType(); local
2407 getNode(unsigned Opcode, SDLoc DL, EVT VT) argument
2424 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue Operand) argument
2688 FoldConstantArithmetic(unsigned Opcode, EVT VT, SDNode *Cst1, SDNode *Cst2) argument
2797 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2) argument
3260 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3) argument
3365 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4) argument
3372 getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) argument
3404 getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG, SDLoc dl) argument
3431 getMemsetStringVal(EVT VT, SDLoc dl, SelectionDAG &DAG, const TargetLowering &TLI, StringRef Str) argument
3475 EVT VT = Base.getValueType(); local
3521 EVT VT = TLI.getOptimalMemOpType(Size, DstAlign, SrcAlign, local
3668 EVT VT = MemOps[i]; local
3772 EVT VT = MemOps[i]; local
3788 EVT VT = MemOps[i]; local
3854 EVT VT = MemOps[i]; local
4117 EVT VT = Cmp.getValueType(); local
4189 EVT VT = Val.getValueType(); local
4211 getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, const Value* PtrVal, unsigned Alignment, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
4242 getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
4388 getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo, const MDNode *Ranges) argument
4421 getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue Offset, EVT MemVT, MachineMemOperand *MMO) argument
4468 getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo, const MDNode *Ranges) argument
4481 getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo) argument
4536 EVT VT = Val.getValueType(); local
4588 EVT VT = Val.getValueType(); local
4652 getVAArg(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align) argument
4660 getNode(unsigned Opcode, SDLoc DL, EVT VT, const SDUse *Ops, unsigned NumOps) argument
4676 getNode(unsigned Opcode, SDLoc DL, EVT VT, const SDValue *Ops, unsigned NumOps) argument
4849 getVTList(EVT VT) argument
5056 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT) argument
5062 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1) argument
5069 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2) argument
5077 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument
5085 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, const SDValue *Ops, unsigned NumOps) argument
5278 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT) argument
5284 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1) argument
5291 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2) argument
5299 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument
5307 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, ArrayRef<SDValue> Ops) argument
5439 getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand) argument
5450 getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT, SDValue Operand, SDValue Subreg) argument
5912 GlobalAddressSDNode(unsigned Opc, unsigned Order, DebugLoc DL, const GlobalValue *GA, EVT VT, int64_t o, unsigned char TF) argument
5965 getValueTypeList(EVT VT) argument
6117 EVT VT = N->getValueType(0); local
6289 EVT VT = getValueType(0); local
6349 isSplatMask(const int *Mask, EVT VT) argument
[all...]
H A DLegalizeVectorOps.cpp319 MVT VT = Op.getSimpleValueType(); local
322 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
335 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
341 EVT VT = Op.getOperand(0).getValueType(); local
352 unsigned NumElts = VT.getVectorNumElements();
353 EVT EltVT = VT.getVectorElementType();
576 EVT VT = Op.getValueType(); local
583 assert(VT.isVector() && !Mask.getValueType().isVector()
586 unsigned NumElem = VT.getVectorNumElements();
593 if (TLI.getOperationAction(ISD::AND, VT)
633 EVT VT = Op.getValueType(); local
661 EVT VT = Mask.getValueType(); local
700 EVT VT = Op.getOperand(0).getValueType(); local
749 EVT VT = Op.getValueType(); local
[all...]

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