/external/llvm/include/llvm/MC/ |
H A D | MCInstrAnalysis.h | 32 return Info->get(Inst.getOpcode()).isBranch(); 36 return Info->get(Inst.getOpcode()).isConditionalBranch(); 40 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); 44 return Info->get(Inst.getOpcode()).isIndirectBranch(); 48 return Info->get(Inst.getOpcode()).isCall(); 52 return Info->get(Inst.getOpcode()).isReturn(); 56 return Info->get(Inst.getOpcode()).isTerminator();
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/external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
H A D | FixedSizeInsn.java | 53 return getOpcode().getFormat().codeSize(); 59 getOpcode().getFormat().writeTo(out, this); 71 return getOpcode().getFormat().listingString(this, noteIndices);
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/external/llvm/lib/MC/ |
H A D | MCInstrAnalysis.cpp | 16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
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H A D | MCInst.cpp | 43 OS << "<MCInst " << getOpcode(); 54 OS << "<MCInst #" << getOpcode(); 58 OS << ' ' << Printer->getOpcodeName(getOpcode());
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/external/dexmaker/src/dx/java/com/android/dx/ssa/ |
H A D | NormalSsaInsn.java | 128 public Rop getOpcode() { method in class:NormalSsaInsn 129 return insn.getOpcode(); 143 if (insn.getOpcode().getOpcode() == RegOps.MARK_LOCAL) { 180 return insn.getOpcode().getOpcode() == RegOps.MOVE; 186 return insn.getOpcode().getOpcode() == RegOps.MOVE_EXCEPTION; 218 Rop opcode = getOpcode(); 227 switch (opcode.getOpcode()) { [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCBranchSelector.cpp | 116 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm()) 118 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ || 119 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) && 158 if (I->getOpcode() == PPC::BCC) { 169 } else if (I->getOpcode() == PPC::BDNZ) { 171 } else if (I->getOpcode() == PPC::BDNZ8) { 173 } else if (I->getOpcode() == PPC::BDZ) { 175 } else if (I->getOpcode() [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonNewValueJump.cpp | 130 if (II->getOpcode() == TargetOpcode::KILL) 180 if (MII->getOpcode() == Hexagon::CALLv3) 194 if (MII->getOpcode() == TargetOpcode::KILL || 195 MII->getOpcode() == TargetOpcode::PHI || 196 MII->getOpcode() == TargetOpcode::COPY) 203 if (MII->getOpcode() == Hexagon::TFR_condset_rr || 204 MII->getOpcode() == Hexagon::TFR_condset_ii || 205 MII->getOpcode() == Hexagon::TFR_condset_ri || 206 MII->getOpcode() == Hexagon::TFR_condset_ir || 207 MII->getOpcode() [all...] |
H A D | HexagonRegisterInfo.cpp | 146 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && 154 if (!TII.isValidOffset(MI.getOpcode(), Offset)) { 163 if ( (MI.getOpcode() == Hexagon::LDriw) || 164 (MI.getOpcode() == Hexagon::LDrid) || 165 (MI.getOpcode() == Hexagon::LDrih) || 166 (MI.getOpcode() == Hexagon::LDriuh) || 167 (MI.getOpcode() == Hexagon::LDrib) || 168 (MI.getOpcode() == Hexagon::LDriub) || 169 (MI.getOpcode() == Hexagon::LDriw_f) || 170 (MI.getOpcode() [all...] |
H A D | HexagonSplitTFRCondSets.cpp | 93 switch(MI->getOpcode()) { 101 if (MI->getOpcode() == Hexagon::TFR_condset_rr || 102 MI->getOpcode() == Hexagon::TFR_condset_rr_f) { 106 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) { 137 if (MI->getOpcode() == Hexagon::TFR_condset_ri ) { 142 } else if (MI->getOpcode() == Hexagon::TFR_condset_ri_f ) { 158 if (MI->getOpcode() == Hexagon::TFR_condset_ir ) { 163 } else if (MI->getOpcode() == Hexagon::TFR_condset_ir_f ) { 186 if (MI->getOpcode() == Hexagon::TFR_condset_ii ) { 195 } else if (MI->getOpcode() [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 82 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 83 Addr.getOpcode() == ISD::TargetGlobalAddress) 86 if (Addr.getOpcode() == ISD::ADD) { 101 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 106 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 118 if (Addr.getOpcode() == ISD::FrameIndex) return false; 119 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 120 Addr.getOpcode() == ISD::TargetGlobalAddress) 123 if (Addr.getOpcode() == ISD::ADD) { 127 if (Addr.getOperand(0).getOpcode() [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600EmitClauseMarkers.cpp | 38 switch (MI->getOpcode()) { 51 TII->isCubeOp(MI->getOpcode()) || 52 TII->isReductionOp(MI->getOpcode())) 66 if (TII->isALUInstr(MI->getOpcode())) 68 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode())) 70 switch (MI->getOpcode()) { 84 switch (MI->getOpcode()) { 112 assert((TII->isALUInstr(MI->getOpcode()) || 113 MI->getOpcode() == AMDGPU::DOT_4) && "Can't assign Const"); 175 if (I->getOpcode() [all...] |
H A D | R600Packetizer.cpp | 72 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) 80 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write); 83 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); 92 if (BI->getOpcode() == AMDGPU::DOT4_r600 || 93 BI->getOpcode() == AMDGPU::DOT4_eg) { 130 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]); 160 if (!TII->isALUInstr(MI->getOpcode())) 162 if (MI->getOpcode() == AMDGPU::GROUP_BARRIER) 166 if (TII->isLDSInstr(MI->getOpcode())) 178 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGP [all...] |
/external/llvm/include/llvm/IR/ |
H A D | Operator.h | 49 /// getOpcode - Return the opcode for this Instruction or ConstantExpr. 51 unsigned getOpcode() const { function in class:llvm::Operator 53 return I->getOpcode(); 54 return cast<ConstantExpr>(this)->getOpcode(); 57 /// getOpcode - If V is an Instruction or ConstantExpr, return its 60 static unsigned getOpcode(const Value *V) { function in class:llvm::Operator 62 return I->getOpcode(); 64 return CE->getOpcode(); 112 return I->getOpcode() == Instruction::Add || 113 I->getOpcode() [all...] |
H A D | Instruction.h | 82 /// getOpcode() returns a member of one of the enums like Instruction::Add. 83 unsigned getOpcode() const { return getValueID() - InstructionVal; } function in class:llvm::Instruction 85 const char *getOpcodeName() const { return getOpcodeName(getOpcode()); } 86 bool isTerminator() const { return isTerminator(getOpcode()); } 87 bool isBinaryOp() const { return isBinaryOp(getOpcode()); } 88 bool isShift() { return isShift(getOpcode()); } 89 bool isCast() const { return isCast(getOpcode()); } 109 return getOpcode() == Shl || getOpcode() == LShr; 114 return getOpcode() [all...] |
/external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
H A D | PlainInsn.java | 92 return new PlainInsn(getOpcode(), getPosition(), 115 Rop newRop = Rops.ropFor(getOpcode().getOpcode(), getResult(), 130 int opcode = getOpcode().getOpcode(); 152 return new PlainInsn(getOpcode(), getPosition(),
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H A D | ThrowingCstInsn.java | 84 return new ThrowingCstInsn(getOpcode(), getPosition(), 92 return new ThrowingCstInsn(getOpcode(), getPosition(), 103 return new ThrowingCstInsn(getOpcode(), getPosition(),
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H A D | ThrowingInsn.java | 99 return new ThrowingInsn(getOpcode(), getPosition(), 106 return new ThrowingInsn(getOpcode(), getPosition(), 116 return new ThrowingInsn(getOpcode(), getPosition(),
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/external/dexmaker/src/dx/java/com/android/dx/io/instructions/ |
H A D | ZeroRegisterDecodedInstruction.java | 41 getFormat(), getOpcode(), newIndex, getIndexType(),
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/external/llvm/unittests/Transforms/Utils/ |
H A D | IntegerDivision.cpp | 41 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SDiv); 46 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr); 49 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::Sub); 71 EXPECT_TRUE(BB->front().getOpcode() == Instruction::UDiv); 76 EXPECT_TRUE(BB->front().getOpcode() == Instruction::ICmp); 79 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::PHI); 101 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem); 106 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr); 109 EXPECT_TRUE(Remainder && Remainder->getOpcode() == Instruction::Sub); 131 EXPECT_TRUE(BB->front().getOpcode() [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 89 switch (MI.getOpcode()) { 133 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS) 180 if (LastInst->getOpcode() == NVPTX::GOTO) { 183 } else if (LastInst->getOpcode() == NVPTX::CBranch) { 201 if (SecondLastInst->getOpcode() == NVPTX::CBranch && 202 LastInst->getOpcode() == NVPTX::GOTO) { 211 if (SecondLastInst->getOpcode() == NVPTX::GOTO && 212 LastInst->getOpcode() == NVPTX::GOTO) { 229 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() ! [all...] |
/external/llvm/lib/Target/R600/MCTargetDesc/ |
H A D | R600MCCodeEmitter.cpp | 92 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 93 if (MI.getOpcode() == AMDGPU::RETURN || 94 MI.getOpcode() == AMDGPU::FETCH_CLAUSE || 95 MI.getOpcode() == AMDGPU::ALU_CLAUSE || 96 MI.getOpcode() == AMDGPU::BUNDLE || 97 MI.getOpcode() == AMDGPU::KILL) { 174 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) {
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/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 145 inline unsigned getOpcode() const; 365 /// getOpcode - Return the SelectionDAG opcode value for this node. For 369 unsigned getOpcode() const { return (unsigned short)NodeType; } function in class:llvm::SDNode 838 inline unsigned SDValue::getOpcode() const { function in class:llvm::SDValue 839 return Node->getOpcode(); 1039 return getOperand(getOpcode() == ISD::STORE ? 2 : 1); 1046 return N->getOpcode() == ISD::LOAD || 1047 N->getOpcode() == ISD::STORE || 1048 N->getOpcode() == ISD::PREFETCH || 1049 N->getOpcode() [all...] |
/external/llvm/lib/Analysis/ |
H A D | CostModel.cpp | 112 switch (I->getOpcode()) { 121 return TTI->getCFInstrCost(I->getOpcode()); 145 return TTI->getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, 151 return TTI->getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy); 156 return TTI->getCmpSelInstrCost(I->getOpcode(), ValTy); 161 return TTI->getMemoryOpCost(I->getOpcode(), ValTy, 167 return TTI->getMemoryOpCost(I->getOpcode(), I->getType(), 184 return TTI->getCastInstrCost(I->getOpcode(), I->getType(), SrcTy); 192 return TTI->getVectorInstrCost(I->getOpcode(), 201 return TTI->getVectorInstrCost(I->getOpcode(), [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineShifts.cpp | 106 switch (I->getOpcode()) { 201 switch (I->getOpcode()) { 314 bool isLeftShift = I.getOpcode() == Instruction::Shl; 319 if (I.getOpcode() != Instruction::AShr && 337 if (I.getOpcode() != Instruction::AShr) 346 if (BO->getOpcode() == Instruction::Mul && isLeftShift) 372 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName()); 386 if (I.getOpcode() == Instruction::Shl) 389 assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift"); 408 switch (Op0BO->getOpcode()) { [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 58 int Opcode = MI->getOpcode(); 80 int Opcode = MI->getOpcode(); 209 if (IsBRU(LastInst->getOpcode())) { 214 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 235 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 241 && IsBRU(LastInst->getOpcode())) { 253 if (IsBRU(SecondLastInst->getOpcode()) && 254 IsBRU(LastInst->getOpcode())) { 263 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) { [all...] |