| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetMachine.cpp | 88 if (getOptLevel() != CodeGenOpt::None) {
130 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
135 addPass(createHexagonISelDag(TM, getOptLevel()));
146 if (getOptLevel() != CodeGenOpt::None)
154 if (getOptLevel() != CodeGenOpt::None)
166 if (getOptLevel() != CodeGenOpt::None)
177 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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| H A D | HexagonFrameLowering.cpp | 153 if (hasFP(MF) || MF.getTarget().getOptLevel() == CodeGenOpt::None) {
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| H A D | HexagonCopyToCombine.cpp | 426 MF.getTarget().getOptLevel() <= CodeGenOpt::Default;
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| H A D | HexagonISelDAGToDAG.cpp | 1626 if (TM.getOptLevel() == CodeGenOpt::Aggressive)
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| /external/llvm/include/llvm/MC/ |
| H A D | MCCodeGenInfo.h | 44 CodeGenOpt::Level getOptLevel() const { return OptLevel; } function in class:llvm::MCCodeGenInfo
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetMachine.cpp | 75 addPass(createAArch64ISelDAG(getAArch64TargetMachine(), getOptLevel()));
78 if (getAArch64Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
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| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTargetMachine.cpp | 57 addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
91 if (getOptLevel() != CodeGenOpt::None)
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| /external/llvm/lib/Target/X86/ |
| H A D | X86TargetMachine.cpp | 173 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
176 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
205 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
215 if (getOptLevel() != CodeGenOpt::None &&
220 if (getOptLevel() != CodeGenOpt::None &&
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMTargetMachine.cpp | 152 if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
159 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
170 if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
172 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
176 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
185 if (getOptLevel() != CodeGenOpt::None) {
198 if (getOptLevel() != CodeGenOpt::None) {
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| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430TargetMachine.cpp | 65 addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetMachine.cpp | 108 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
128 if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
136 if (getOptLevel() != CodeGenOpt::None)
143 if (getOptLevel() != CodeGenOpt::None)
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| H A D | PPCISelDAGToDAG.cpp | 1388 if (TM.getOptLevel() == CodeGenOpt::None)
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreTargetMachine.cpp | 65 addPass(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
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| /external/llvm/lib/CodeGen/ |
| H A D | Passes.cpp | 378 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
420 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
484 if (getOptLevel() != CodeGenOpt::None) {
512 if (getOptLevel() != CodeGenOpt::None)
524 if (getOptLevel() != CodeGenOpt::None) {
536 if (getOptLevel() != CodeGenOpt::None)
589 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
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| H A D | LLVMTargetMachine.cpp | 124 (TM->getOptLevel() == CodeGenOpt::None &&
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| H A D | PostRASchedulerList.cpp | 273 if (!ST.enablePostRAScheduler(PassConfig->getOptLevel(), AntiDepMode,
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| H A D | TwoAddressInstructionPass.cpp | 1490 OptLevel = TM.getOptLevel();
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | Passes.h | 140 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); } function in class:llvm::TargetPassConfig
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| /external/llvm/lib/Target/ |
| H A D | TargetMachine.cpp | 159 /// getOptLevel - Returns the optimization level: None, Less,
161 CodeGenOpt::Level TargetMachine::getOptLevel() const { function in class:TargetMachine
164 return CodeGenInfo->getOptLevel();
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| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 141 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
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| /external/llvm/include/llvm/Target/ |
| H A D | TargetMachine.h | 207 /// getOptLevel - Returns the optimization level: None, Less,
209 CodeGenOpt::Level getOptLevel() const;
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsDelaySlotFiller.cpp | 503 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | AMDILPeepholeOptimizer.cpp | 166 optLevel = TM.getOptLevel();
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDILPeepholeOptimizer.cpp | 166 optLevel = TM.getOptLevel();
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 5177 if (TM.getOptLevel() == CodeGenOpt::None)
|