| /external/valgrind/main/VEX/priv/ |
| H A D | host_generic_reg_alloc2.c | 79 HReg rreg; member in struct:__anon27584
95 /* Which rreg is this for? */
96 HReg rreg; member in struct:__anon27585
106 rreg has the same value as the spill slot for the associated
108 spill store or reload for this rreg. */
130 rreg" is the main beneficiary.
133 associated with any rreg, that entry can be set to INVALID_RREG_NO.
353 HReg rreg, vreg, vregS, vregD; local
391 /* The vreg -> rreg map constructed and then applied to each
429 (*ppReg)(rreg_state[z].rreg); \
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| H A D | host_mips_defs.c | 2202 void genSpill_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, argument
2207 vassert(!hregIsVirtual(rreg));
2211 switch (hregClass(rreg)) {
2214 *i1 = MIPSInstr_Store(8, am, rreg, mode64);
2218 *i1 = MIPSInstr_Store(4, am, rreg, mode64);
2222 *i1 = MIPSInstr_FpLdSt(False /*Store */ , 4, rreg, am);
2225 *i1 = MIPSInstr_FpLdSt(False /*Store */ , 8, rreg, am);
2228 ppHRegClass(hregClass(rreg));
2234 void genReload_MIPS( /*OUT*/ HInstr ** i1, /*OUT*/ HInstr ** i2, HReg rreg, argument
2238 vassert(!hregIsVirtual(rreg));
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| H A D | host_amd64_defs.h | 761 HReg rreg, Int offset, Bool );
763 HReg rreg, Int offset, Bool );
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| H A D | host_arm_defs.h | 1028 HReg rreg, Int offset, Bool );
1030 HReg rreg, Int offset, Bool );
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| H A D | host_mips_defs.h | 711 HReg rreg, Int offset, Bool);
713 HReg rreg, Int offset, Bool);
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| H A D | host_x86_defs.h | 722 HReg rreg, Int offset, Bool );
724 HReg rreg, Int offset, Bool );
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| H A D | host_x86_defs.c | 1702 HReg rreg, Int offsetB, Bool mode64 )
1706 vassert(!hregIsVirtual(rreg));
1710 switch (hregClass(rreg)) {
1712 *i1 = X86Instr_Alu32M ( Xalu_MOV, X86RI_Reg(rreg), am );
1715 *i1 = X86Instr_FpLdSt ( False/*store*/, 10, rreg, am );
1718 *i1 = X86Instr_SseLdSt ( False/*store*/, rreg, am );
1721 ppHRegClass(hregClass(rreg));
1727 HReg rreg, Int offsetB, Bool mode64 )
1731 vassert(!hregIsVirtual(rreg));
1735 switch (hregClass(rreg)) {
1701 genSpill_X86( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument
1726 genReload_X86( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument
[all...] |
| H A D | host_amd64_defs.c | 1855 HReg rreg, Int offsetB, Bool mode64 )
1859 vassert(!hregIsVirtual(rreg));
1863 switch (hregClass(rreg)) {
1865 *i1 = AMD64Instr_Alu64M ( Aalu_MOV, AMD64RI_Reg(rreg), am );
1868 *i1 = AMD64Instr_SseLdSt ( False/*store*/, 16, rreg, am );
1871 ppHRegClass(hregClass(rreg));
1877 HReg rreg, Int offsetB, Bool mode64 )
1881 vassert(!hregIsVirtual(rreg));
1885 switch (hregClass(rreg)) {
1887 *i1 = AMD64Instr_Alu64R ( Aalu_MOV, AMD64RMI_Mem(am), rreg );
1854 genSpill_AMD64( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument
1876 genReload_AMD64( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument
[all...] |
| H A D | host_ppc_defs.c | 2848 HReg rreg, Int offsetB, Bool mode64 )
2851 vassert(!hregIsVirtual(rreg));
2854 switch (hregClass(rreg)) {
2857 *i1 = PPCInstr_Store( 8, am, rreg, mode64 );
2861 *i1 = PPCInstr_Store( 4, am, rreg, mode64 );
2864 *i1 = PPCInstr_FpLdSt ( False/*store*/, 8, rreg, am );
2869 *i1 = PPCInstr_AvLdSt ( False/*store*/, 16, rreg, am );
2872 ppHRegClass(hregClass(rreg));
2878 HReg rreg, Int offsetB, Bool mode64 )
2881 vassert(!hregIsVirtual(rreg));
2847 genSpill_PPC( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument
2877 genReload_PPC( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument
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| H A D | host_ppc_defs.h | 1074 HReg rreg, Int offsetB, Bool mode64 );
1076 HReg rreg, Int offsetB, Bool mode64 );
|
| H A D | host_arm_defs.c | 2531 HReg rreg, Int offsetB, Bool mode64 )
2535 vassert(!hregIsVirtual(rreg));
2538 rclass = hregClass(rreg);
2543 rreg,
2563 rreg,
2567 rreg,
2576 *i2 = ARMInstr_NLdStQ(False, rreg, mkARMAModeN_R(r12));
2586 HReg rreg, Int offsetB, Bool mode64 )
2590 vassert(!hregIsVirtual(rreg));
2593 rclass = hregClass(rreg);
2530 genSpill_ARM( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument
2585 genReload_ARM( HInstr** i1, HInstr** i2, HReg rreg, Int offsetB, Bool mode64 ) argument
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| H A D | host_s390_defs.c | 455 genSpill_S390(HInstr **i1, HInstr **i2, HReg rreg, Int offsetB, Bool mode64) argument
461 vassert(!hregIsVirtual(rreg));
467 switch (hregClass(rreg)) {
470 *i1 = s390_insn_store(8, am, rreg);
474 ppHRegClass(hregClass(rreg));
482 genReload_S390(HInstr **i1, HInstr **i2, HReg rreg, Int offsetB, Bool mode64) argument
488 vassert(!hregIsVirtual(rreg));
494 switch (hregClass(rreg)) {
497 *i1 = s390_insn_load(8, rreg, am);
501 ppHRegClass(hregClass(rreg));
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