Searched refs:base_reg (Results 1 - 22 of 22) sorted by relevance

/external/chromium_org/v8/src/x64/
H A Dcodegen-x64.h116 Register base_reg,
121 : base_reg_(base_reg),
129 Register base_reg,
134 : base_reg_(base_reg),
142 Register base_reg,
147 : base_reg_(base_reg),
115 StackArgumentsAccessor( Register base_reg, int argument_count_immediate, StackArgumentsAccessorReceiverMode receiver_mode = ARGUMENTS_CONTAIN_RECEIVER, int extra_displacement_to_last_argument = 0) argument
128 StackArgumentsAccessor( Register base_reg, Register argument_count_reg, StackArgumentsAccessorReceiverMode receiver_mode = ARGUMENTS_CONTAIN_RECEIVER, int extra_displacement_to_last_argument = 0) argument
141 StackArgumentsAccessor( Register base_reg, const ParameterCount& parameter_count, StackArgumentsAccessorReceiverMode receiver_mode = ARGUMENTS_CONTAIN_RECEIVER, int extra_displacement_to_last_argument = 0) argument
H A Ddisasm-x64.cc363 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } function in class:disasm::DisassemblerX64
1434 NameOfCPURegister(base_reg(current & 0x07)));
1440 NameOfCPURegister(base_reg(current & 0x07)));
1463 NameOfCPURegister(base_reg(current & 0x07)),
H A Dmacro-assembler-x64.cc702 Register base_reg = r15; local
703 Move(base_reg, next_address);
704 movq(prev_next_address_reg, Operand(base_reg, kNextOffset));
705 movq(prev_limit_reg, Operand(base_reg, kLimitOffset));
706 addl(Operand(base_reg, kLevelOffset), Immediate(1));
757 subl(Operand(base_reg, kLevelOffset), Immediate(1));
758 movq(Operand(base_reg, kNextOffset), prev_next_address_reg);
759 cmpq(prev_limit_reg, Operand(base_reg, kLimitOffset));
820 movq(Operand(base_reg, kLimitOffset), prev_limit_reg);
H A Dassembler-x64.cc214 int base_reg = (has_sib ? operand.buf_[1] : modrm) & 0x07;
217 bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base.
237 } else if (disp_value != 0 || (base_reg == 0x05)) {
/external/chromium_org/third_party/mesa/src/src/mesa/program/
H A Dregister_allocate.h44 unsigned int base_reg, unsigned int reg);
H A Dregister_allocate.c210 * Adds a conflict between base_reg and reg, and also between reg and
211 * anything that base_reg conflicts with.
219 unsigned int base_reg, unsigned int reg)
223 ra_add_reg_conflict(regs, reg, base_reg);
225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) {
226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]);
218 ra_add_transitive_reg_conflict(struct ra_regs *regs, unsigned int base_reg, unsigned int reg) argument
/external/mesa3d/src/mesa/program/
H A Dregister_allocate.h44 unsigned int base_reg, unsigned int reg);
H A Dregister_allocate.c210 * Adds a conflict between base_reg and reg, and also between reg and
211 * anything that base_reg conflicts with.
219 unsigned int base_reg, unsigned int reg)
223 ra_add_reg_conflict(regs, reg, base_reg);
225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) {
226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]);
218 ra_add_transitive_reg_conflict(struct ra_regs *regs, unsigned int base_reg, unsigned int reg) argument
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dbrw_vec4_reg_allocate.cpp131 for (int base_reg = j;
132 base_reg < j + class_sizes[i];
133 base_reg++) {
134 ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
H A Dbrw_fs_reg_allocate.cpp119 for (int base_reg = j;
120 base_reg < j + class_sizes[i];
121 base_reg++) {
122 ra_add_transitive_reg_conflict(brw->wm.regs, base_reg, reg);
H A Dbrw_blorp_blit.cpp493 void alloc_push_const_regs(int base_reg);
743 brw_blorp_blit_program::alloc_push_const_regs(int base_reg) argument
748 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
H A Dbrw_wm_emit.c1323 GLuint base_reg,
1343 brw_message_reg(base_reg + 1),
1357 base_reg,
1322 fire_fb_write( struct brw_wm_compile *c, GLuint base_reg, GLuint nr, GLuint target, GLuint eot ) argument
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_vec4_reg_allocate.cpp131 for (int base_reg = j;
132 base_reg < j + class_sizes[i];
133 base_reg++) {
134 ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
H A Dbrw_fs_reg_allocate.cpp119 for (int base_reg = j;
120 base_reg < j + class_sizes[i];
121 base_reg++) {
122 ra_add_transitive_reg_conflict(brw->wm.regs, base_reg, reg);
H A Dbrw_blorp_blit.cpp493 void alloc_push_const_regs(int base_reg);
743 brw_blorp_blit_program::alloc_push_const_regs(int base_reg) argument
748 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
H A Dbrw_wm_emit.c1323 GLuint base_reg,
1343 brw_message_reg(base_reg + 1),
1357 base_reg,
1322 fire_fb_write( struct brw_wm_compile *c, GLuint base_reg, GLuint nr, GLuint target, GLuint eot ) argument
/external/qemu/
H A Dgdbstub.c258 int base_reg; member in struct:GDBRegisterState
1390 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1391 return r->get_reg(env, mem_buf, reg - r->base_reg);
1405 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1406 return r->set_reg(env, mem_buf, reg - r->base_reg);
1427 s->base_reg = last_reg;
1443 if (g_pos != s->base_reg) {
1445 "Expected %d got %d\n", xml, g_pos, s->base_reg);
[all...]
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
H A Dradeon_state_init.c423 uint32_t base_reg; local
435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_state_init.c423 uint32_t base_reg; local
435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
/external/v8/src/x64/
H A Ddisasm-x64.cc358 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } function in class:disasm::DisassemblerX64
1374 NameOfCPURegister(base_reg(current & 0x07)));
1380 NameOfCPURegister(base_reg(current & 0x07)));
1403 NameOfCPURegister(base_reg(current & 0x07)),
H A Dmacro-assembler-x64.cc698 Register base_reg = r15; local
699 movq(base_reg, next_address);
700 movq(prev_next_address_reg, Operand(base_reg, kNextOffset));
701 movq(prev_limit_reg, Operand(base_reg, kLimitOffset));
702 addl(Operand(base_reg, kLevelOffset), Immediate(1));
721 subl(Operand(base_reg, kLevelOffset), Immediate(1));
722 movq(Operand(base_reg, kNextOffset), prev_next_address_reg);
723 cmpq(prev_limit_reg, Operand(base_reg, kLimitOffset));
745 movq(Operand(base_reg, kLimitOffset), prev_limit_reg);
H A Dassembler-x64.cc274 int base_reg = (has_sib ? operand.buf_[1] : modrm) & 0x07;
277 bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base.
297 } else if (disp_value != 0 || (base_reg == 0x05)) {

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