| /art/compiler/dex/quick/x86/ |
| H A D | utility_x86.cc | 345 LIR* X86Mir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale, argument
350 bool is_array = r_index != INVALID_REG;
424 load = NewLIR5(opcode, r_dest, rBase, r_index, scale,
428 load2 = NewLIR5(opcode, r_dest_hi, rBase, r_index, scale,
430 load = NewLIR5(opcode, r_dest, rBase, r_index, scale,
433 load = NewLIR5(opcode, r_dest, rBase, r_index, scale,
435 load2 = NewLIR5(opcode, r_dest_hi, rBase, r_index, scale,
446 int r_index, int r_dest, int scale, OpSize size) {
447 return LoadBaseIndexedDisp(rBase, r_index, scale, 0,
463 LIR* X86Mir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, in argument
445 LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) argument
544 StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) argument
[all...] |
| H A D | int_x86.cc | 522 int r_index = TargetReg(kArg3); // Register holding index into array local
526 LoadValueDirectFixed(rl_index, r_index); // Grab index
539 LoadValueDirectFixed(rl_index, r_index); // Reload index
551 GenRegMemCheck(kCondUge, r_index, r_array, len_offset, kThrowArrayBounds);
553 StoreBaseIndexedDisp(r_array, r_index, scale,
555 FreeTemp(r_index);
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| H A D | codegen_x86.h | 36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
37 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
44 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
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| /art/compiler/dex/quick/mips/ |
| H A D | utility_mips.cc | 336 LIR* MipsMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest, argument
353 first = NewLIR3(kMipsAddu, t_reg , rBase, r_index);
355 first = OpRegRegImm(kOpLsl, t_reg, r_index, scale);
388 LIR* MipsMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src, argument
392 int r_new_index = r_index;
405 first = NewLIR3(kMipsAddu, t_reg , rBase, r_index);
407 first = OpRegRegImm(kOpLsl, t_reg, r_index, scale);
645 LIR* MipsMir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, argument
657 LIR* MipsMir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, argument
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| H A D | codegen_mips.h | 36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
37 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
44 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
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| H A D | int_mips.cc | 569 int r_index = TargetReg(kArg3); // Register holding index into array local
573 LoadValueDirectFixed(rl_index, r_index); // Grab index
586 LoadValueDirectFixed(rl_index, r_index); // Reload index
604 GenRegRegCheck(kCondCs, r_index, reg_len, kThrowArrayBounds);
606 StoreBaseIndexed(r_ptr, r_index, r_value, scale, kWord);
608 FreeTemp(r_index);
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| /art/compiler/dex/quick/arm/ |
| H A D | utility_arm.cc | 642 LIR* ArmMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest, argument
644 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_dest);
672 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index,
675 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_index);
699 load = NewLIR3(opcode, r_dest, rBase, r_index);
701 load = NewLIR4(opcode, r_dest, rBase, r_index, scale);
706 LIR* ArmMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src, argument
708 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_src);
736 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index,
739 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_index);
1045 StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_src, int r_src_hi, OpSize size, int s_reg) argument
1057 LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_dest, int r_dest_hi, OpSize size, int s_reg) argument
[all...] |
| H A D | codegen_arm.h | 35 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
36 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
42 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
43 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
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| H A D | int_arm.cc | 947 int r_index = TargetReg(kArg3); // Register holding index into array local
951 LoadValueDirectFixed(rl_index, r_index); // Grab index
964 LoadValueDirectFixed(rl_index, r_index); // Reload index
982 GenRegRegCheck(kCondCs, r_index, reg_len, kThrowArrayBounds);
984 StoreBaseIndexed(r_ptr, r_index, r_value, scale, kWord);
986 FreeTemp(r_index);
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| /art/compiler/dex/quick/ |
| H A D | mir_to_lir.h | 534 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0;
535 virtual LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
541 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0;
542 virtual LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
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