Searched refs:reg_index (Results 1 - 25 of 39) sorted by relevance

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/external/libnfc-nxp/src/
H A DphHciNfc_IDMgmt.c325 p_pipe_info->reg_index = FW_VERSION_INDEX;
339 p_pipe_info->reg_index = HW_VERSION_INDEX;
353 p_pipe_info->reg_index = HCI_VERSION_INDEX;
367 p_pipe_info->reg_index = VENDOR_NAME_INDEX;
381 p_pipe_info->reg_index = MODEL_ID_INDEX;
395 p_pipe_info->reg_index = GATES_LIST_INDEX;
409 p_pipe_info->reg_index = FULL_VERSION_INDEX;
487 p_pipe_info->reg_index = FW_VERSION_INDEX;
501 p_pipe_info->reg_index = HW_VERSION_INDEX;
515 p_pipe_info->reg_index
[all...]
H A DphHciNfc_RFReaderB.c304 p_pipe_info->reg_index = RDR_B_PUPI_INDEX;
319 p_pipe_info->reg_index = RDR_B_APP_DATA_INDEX;
335 p_pipe_info->reg_index = RDR_B_AFI_INDEX;
351 p_pipe_info->reg_index = RDR_B_HIGHER_LAYER_RESP_INDEX;
368 p_pipe_info->reg_index = RDR_B_HIGHER_LAYER_DATA_INDEX;
465 p_rdr_b_info->p_pipe_info->reg_index,
849 p_pipe_info->reg_index = RDR_B_AFI_INDEX;
903 p_pipe_info->reg_index = RDR_B_HIGHER_LAYER_DATA_INDEX;
H A DphHciNfc_LinkMgmt.c212 p_pipe_info->reg_index = REC_ERROR_INDEX;
236 p_pipe_info->reg_index = REC_ERROR_INDEX;
388 p_link_mgmt_info->p_pipe_info->reg_index,
H A DphHciNfc_PollingLoop.c384 p_pipe_info->reg_index
400 p_pipe_info->reg_index = PL_EMULATION_INDEX;
408 p_pipe_info->reg_index = PL_PAUSE_INDEX;
455 p_pipe_info->reg_index = PL_RD_PHASES_INDEX;
497 p_pipe_info->reg_index = PL_DISABLE_TARGET_INDEX;
632 p_poll_info->p_pipe_info->reg_index,
H A DphHciNfc_NfcIPMgmt.c700 ppipe_info->reg_index,
1050 p_pipe_info->reg_index = (uint8_t)NXP_NFCIP_NFCID3I;
1065 p_pipe_info->reg_index = (uint8_t)NXP_NFCIP_NFCID3T;
1080 p_pipe_info->reg_index = (uint8_t)NXP_NFCIP_PARAM;
1095 p_pipe_info->reg_index = (uint8_t)((NFCIP_INITIATOR ==
1112 p_pipe_info->reg_index = (uint8_t)NXP_NFCIP_STATUS;
1633 p_pipe_info->reg_index = (uint8_t)NXP_NFCIP_MODE;
1686 p_pipe_info->reg_index = (uint8_t)NXP_NFCIP_NAD;
1732 p_pipe_info->reg_index = (uint8_t)NXP_NFCIP_DID;
1777 p_pipe_info->reg_index
[all...]
H A DphHciNfc_CE_A.c190 ps_pipe_info->reg_index = HOST_CE_A_SAK_INDEX;
207 ps_pipe_info->reg_index = HOST_CE_A_ATQA_INDEX;
460 ps_ce_a_info->p_pipe_info->reg_index,
581 p_pipe_info->reg_index = HOST_CE_A_MODE_INDEX;
H A DphHciNfc_CE_B.c189 ps_pipe_info->reg_index = HOST_CE_B_ATQB_INDEX;
205 ps_pipe_info->reg_index = HOST_CE_B_ATQB_INDEX;
349 ps_pipe_info->reg_index = HOST_CE_B_MODE_INDEX;
502 ps_ce_b_info->p_pipe_info->reg_index,
H A DphHciNfc_RFReaderA.c282 p_pipe_info->reg_index = RDR_A_UID_INDEX;
297 p_pipe_info->reg_index = RDR_A_SAK_INDEX;
312 p_pipe_info->reg_index = RDR_A_ATQA_INDEX;
536 p_rdr_a_info->p_pipe_info->reg_index,
909 p_pipe_info->reg_index = NXP_AUTO_ACTIVATION_INDEX;
953 p_pipe_info->reg_index = RDR_A_DATA_RATE_MAX_INDEX;
1234 p_pipe_info->reg_index = RDR_A_APP_DATA_INDEX;
1283 p_pipe_info->reg_index = RDR_A_FWI_SFGT_INDEX;
H A DphHciNfc_Jewel.c300 ps_pipe_info->reg_index = NXP_JEWEL_READID;
320 ps_pipe_info->reg_index = JEWEL_END_SEQUENCE;
420 if (NXP_JEWEL_READID == ps_jewel_info->p_pipe_info->reg_index)
423 ps_jewel_info->p_pipe_info->reg_index,
484 ps_jewel_info->p_pipe_info->reg_index,
H A DphHciNfc_Felica.c315 p_pipe_info->reg_index = NXP_FEL_SYS_CODE;
330 p_pipe_info->reg_index = NXP_FEL_CURRENTIDM;
345 p_pipe_info->reg_index = NXP_FEL_CURRENTPMM;
603 p_fel_info->p_pipe_info->reg_index,
H A DphHciNfc_ISO15693.c296 ps_pipe_info->reg_index = ISO_15693_INVENTORY_INDEX;
311 ps_pipe_info->reg_index = ISO_15693_AFI_INDEX;
481 ps_pipe_info->reg_index,
756 ps_pipe_info->reg_index = ISO_15693_AFI_INDEX;
H A DphHciNfc_SWP.c255 ps_swp_info->p_pipe_info->reg_index,
329 ps_pipe_info->reg_index = NXP_SWP_DEFAULT_MODE_INDEX;
377 ps_pipe_info->reg_index = NXP_SWP_STATUS_INDEX;
453 ps_pipe_info->reg_index = NXP_SWP_PROTECTED_INDEX;
H A DphHciNfc_WI.c311 p_pipe_info->reg_index = NXP_SE_DEFAULTMODE_INDEX;
357 p_pipe_info->reg_index = NXP_SE_DEFAULTMODE_INDEX;
465 p_pipe_info->reg_index = NXP_SE_EVENTS_INDEX;
595 p_wiinfo->p_pipe_info->reg_index,
H A DphHciNfc_AdminMgmt.c278 p_pipe_info->reg_index = SESSION_INDEX;
336 p_pipe_info->reg_index = MAX_PIPE_INDEX;
413 p_pipe_info->reg_index = WHITELIST_INDEX;
444 p_pipe_info->reg_index = HOST_LIST_INDEX;
872 p_admin_info->admin_pipe_info->reg_index,
/external/chromium_org/v8/src/
H A Dsafepoint-table.cc52 bool SafepointEntry::HasRegisterAt(int reg_index) const {
54 ASSERT(reg_index >= 0 && reg_index < kNumSafepointRegisters);
55 int byte_index = reg_index >> kBitsPerByteLog2;
56 int bit_index = reg_index & (kBitsPerByte - 1);
H A Dlithium.cc69 int reg_index = unalloc->fixed_register_index(); local
71 Register::AllocationIndexToString(reg_index);
76 int reg_index = unalloc->fixed_register_index(); local
78 DoubleRegister::AllocationIndexToString(reg_index);
H A Dsafepoint-table.h96 bool HasRegisterAt(int reg_index) const;
/external/v8/src/
H A Dsafepoint-table.cc52 bool SafepointEntry::HasRegisterAt(int reg_index) const {
54 ASSERT(reg_index >= 0 && reg_index < kNumSafepointRegisters);
55 int byte_index = reg_index >> kBitsPerByteLog2;
56 int bit_index = reg_index & (kBitsPerByte - 1);
H A Dsafepoint-table.h96 bool HasRegisterAt(int reg_index) const;
/external/mdnsresponder/mDNSShared/
H A Ddnssd_ipc.c160 hdr->reg_index = htonl(hdr->reg_index);
H A Ddnssd_ipc.h180 uint32_t reg_index; // identifier for a record registered via DNSServiceRegisterRecord() on a variable
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
H A Dbrw_optimize.c117 int reg_index, int size,
130 const int reg_start = reg_index * REG_SIZE;
161 int reg_index, int size)
172 const int reg_start = reg_index * REG_SIZE;
231 int reg_index, int size)
234 const int reg_start = reg_index * REG_SIZE;
251 brw_is_mrf_written(const struct brw_instruction *inst, int reg_index, int size) argument
253 return (brw_is_mrf_written_alu(inst, reg_index, size) ||
254 brw_is_mrf_written_send(inst, reg_index, size));
259 int reg_index, in
116 brw_is_grf_written(const struct brw_instruction *inst, int reg_index, int size, int gen) argument
160 brw_is_mrf_written_alu(const struct brw_instruction *inst, int reg_index, int size) argument
230 brw_is_mrf_written_send(const struct brw_instruction *inst, int reg_index, int size) argument
258 brw_is_mrf_read(const struct brw_instruction *inst, int reg_index, int size, int gen) argument
294 brw_is_grf_read(const struct brw_instruction *inst, int reg_index, int size) argument
[all...]
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_optimize.c117 int reg_index, int size,
130 const int reg_start = reg_index * REG_SIZE;
161 int reg_index, int size)
172 const int reg_start = reg_index * REG_SIZE;
231 int reg_index, int size)
234 const int reg_start = reg_index * REG_SIZE;
251 brw_is_mrf_written(const struct brw_instruction *inst, int reg_index, int size) argument
253 return (brw_is_mrf_written_alu(inst, reg_index, size) ||
254 brw_is_mrf_written_send(inst, reg_index, size));
259 int reg_index, in
116 brw_is_grf_written(const struct brw_instruction *inst, int reg_index, int size, int gen) argument
160 brw_is_mrf_written_alu(const struct brw_instruction *inst, int reg_index, int size) argument
230 brw_is_mrf_written_send(const struct brw_instruction *inst, int reg_index, int size) argument
258 brw_is_mrf_read(const struct brw_instruction *inst, int reg_index, int size, int gen) argument
294 brw_is_grf_read(const struct brw_instruction *inst, int reg_index, int size) argument
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r600/
H A Dr600_llvm.c102 LLVMValueRef reg_index = lp_build_const_int32( local
108 reg_index);
126 LLVMValueRef reg_index = lp_build_const_int32( local
137 output, reg_index);
/external/mesa3d/src/gallium/drivers/r600/
H A Dr600_llvm.c102 LLVMValueRef reg_index = lp_build_const_int32( local
108 reg_index);
126 LLVMValueRef reg_index = lp_build_const_int32( local
137 output, reg_index);

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