1#ifndef __ASM_APICDEF_H 2#define __ASM_APICDEF_H 3 4/* 5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) 6 * 7 * Alan Cox <Alan.Cox@linux.org>, 1995. 8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 9 */ 10 11#define APIC_DEFAULT_PHYS_BASE 0xfee00000 12 13#define APIC_ID 0x20 14#define APIC_LVR 0x30 15#define APIC_LVR_MASK 0xFF00FF 16#define GET_APIC_VERSION(x) ((x)&0xFF) 17#define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF) 18#define APIC_INTEGRATED(x) ((x)&0xF0) 19#define APIC_XAPIC(x) ((x) >= 0x14) 20#define APIC_TASKPRI 0x80 21#define APIC_TPRI_MASK 0xFF 22#define APIC_ARBPRI 0x90 23#define APIC_ARBPRI_MASK 0xFF 24#define APIC_PROCPRI 0xA0 25#define APIC_EOI 0xB0 26#define APIC_EIO_ACK 0x0 /* Write this to the EOI register */ 27#define APIC_RRR 0xC0 28#define APIC_LDR 0xD0 29#define APIC_LDR_MASK (0xFF<<24) 30#define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF) 31#define SET_APIC_LOGICAL_ID(x) (((x)<<24)) 32#define APIC_ALL_CPUS 0xFF 33#define APIC_DFR 0xE0 34#define APIC_DFR_CLUSTER 0x0FFFFFFFul 35#define APIC_DFR_FLAT 0xFFFFFFFFul 36#define APIC_SPIV 0xF0 37#define APIC_SPIV_FOCUS_DISABLED (1<<9) 38#define APIC_SPIV_APIC_ENABLED (1<<8) 39#define APIC_ISR 0x100 40#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ 41#define APIC_TMR 0x180 42#define APIC_IRR 0x200 43#define APIC_ESR 0x280 44#define APIC_ESR_SEND_CS 0x00001 45#define APIC_ESR_RECV_CS 0x00002 46#define APIC_ESR_SEND_ACC 0x00004 47#define APIC_ESR_RECV_ACC 0x00008 48#define APIC_ESR_SENDILL 0x00020 49#define APIC_ESR_RECVILL 0x00040 50#define APIC_ESR_ILLREGA 0x00080 51#define APIC_ICR 0x300 52#define APIC_DEST_SELF 0x40000 53#define APIC_DEST_ALLINC 0x80000 54#define APIC_DEST_ALLBUT 0xC0000 55#define APIC_ICR_RR_MASK 0x30000 56#define APIC_ICR_RR_INVALID 0x00000 57#define APIC_ICR_RR_INPROG 0x10000 58#define APIC_ICR_RR_VALID 0x20000 59#define APIC_INT_LEVELTRIG 0x08000 60#define APIC_INT_ASSERT 0x04000 61#define APIC_ICR_BUSY 0x01000 62#define APIC_DEST_LOGICAL 0x00800 63#define APIC_DM_FIXED 0x00000 64#define APIC_DM_LOWEST 0x00100 65#define APIC_DM_SMI 0x00200 66#define APIC_DM_REMRD 0x00300 67#define APIC_DM_NMI 0x00400 68#define APIC_DM_INIT 0x00500 69#define APIC_DM_STARTUP 0x00600 70#define APIC_DM_EXTINT 0x00700 71#define APIC_VECTOR_MASK 0x000FF 72#define APIC_ICR2 0x310 73#define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF) 74#define SET_APIC_DEST_FIELD(x) ((x)<<24) 75#define APIC_LVTT 0x320 76#define APIC_LVTTHMR 0x330 77#define APIC_LVTPC 0x340 78#define APIC_LVT0 0x350 79#define APIC_LVT_TIMER_BASE_MASK (0x3<<18) 80#define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3) 81#define SET_APIC_TIMER_BASE(x) (((x)<<18)) 82#define APIC_TIMER_BASE_CLKIN 0x0 83#define APIC_TIMER_BASE_TMBASE 0x1 84#define APIC_TIMER_BASE_DIV 0x2 85#define APIC_LVT_TIMER_PERIODIC (1<<17) 86#define APIC_LVT_MASKED (1<<16) 87#define APIC_LVT_LEVEL_TRIGGER (1<<15) 88#define APIC_LVT_REMOTE_IRR (1<<14) 89#define APIC_INPUT_POLARITY (1<<13) 90#define APIC_SEND_PENDING (1<<12) 91#define APIC_MODE_MASK 0x700 92#define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7) 93#define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8)) 94#define APIC_MODE_FIXED 0x0 95#define APIC_MODE_NMI 0x4 96#define APIC_MODE_EXTINT 0x7 97#define APIC_LVT1 0x360 98#define APIC_LVTERR 0x370 99#define APIC_TMICT 0x380 100#define APIC_TMCCT 0x390 101#define APIC_TDCR 0x3E0 102#define APIC_TDR_DIV_TMBASE (1<<2) 103#define APIC_TDR_DIV_1 0xB 104#define APIC_TDR_DIV_2 0x0 105#define APIC_TDR_DIV_4 0x1 106#define APIC_TDR_DIV_8 0x2 107#define APIC_TDR_DIV_16 0x3 108#define APIC_TDR_DIV_32 0x8 109#define APIC_TDR_DIV_64 0x9 110#define APIC_TDR_DIV_128 0xA 111 112#define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) 113 114#define MAX_IO_APICS 64 115 116/* 117 * the local APIC register structure, memory mapped. Not terribly well 118 * tested, but we might eventually use this one in the future - the 119 * problem why we cannot use it right now is the P5 APIC, it has an 120 * errata which cannot take 8-bit reads and writes, only 32-bit ones ... 121 */ 122#define u32 unsigned int 123 124 125struct local_apic { 126 127/*000*/ struct { u32 __reserved[4]; } __reserved_01; 128 129/*010*/ struct { u32 __reserved[4]; } __reserved_02; 130 131/*020*/ struct { /* APIC ID Register */ 132 u32 __reserved_1 : 24, 133 phys_apic_id : 4, 134 __reserved_2 : 4; 135 u32 __reserved[3]; 136 } id; 137 138/*030*/ const 139 struct { /* APIC Version Register */ 140 u32 version : 8, 141 __reserved_1 : 8, 142 max_lvt : 8, 143 __reserved_2 : 8; 144 u32 __reserved[3]; 145 } version; 146 147/*040*/ struct { u32 __reserved[4]; } __reserved_03; 148 149/*050*/ struct { u32 __reserved[4]; } __reserved_04; 150 151/*060*/ struct { u32 __reserved[4]; } __reserved_05; 152 153/*070*/ struct { u32 __reserved[4]; } __reserved_06; 154 155/*080*/ struct { /* Task Priority Register */ 156 u32 priority : 8, 157 __reserved_1 : 24; 158 u32 __reserved_2[3]; 159 } tpr; 160 161/*090*/ const 162 struct { /* Arbitration Priority Register */ 163 u32 priority : 8, 164 __reserved_1 : 24; 165 u32 __reserved_2[3]; 166 } apr; 167 168/*0A0*/ const 169 struct { /* Processor Priority Register */ 170 u32 priority : 8, 171 __reserved_1 : 24; 172 u32 __reserved_2[3]; 173 } ppr; 174 175/*0B0*/ struct { /* End Of Interrupt Register */ 176 u32 eoi; 177 u32 __reserved[3]; 178 } eoi; 179 180/*0C0*/ struct { u32 __reserved[4]; } __reserved_07; 181 182/*0D0*/ struct { /* Logical Destination Register */ 183 u32 __reserved_1 : 24, 184 logical_dest : 8; 185 u32 __reserved_2[3]; 186 } ldr; 187 188/*0E0*/ struct { /* Destination Format Register */ 189 u32 __reserved_1 : 28, 190 model : 4; 191 u32 __reserved_2[3]; 192 } dfr; 193 194/*0F0*/ struct { /* Spurious Interrupt Vector Register */ 195 u32 spurious_vector : 8, 196 apic_enabled : 1, 197 focus_cpu : 1, 198 __reserved_2 : 22; 199 u32 __reserved_3[3]; 200 } svr; 201 202/*100*/ struct { /* In Service Register */ 203/*170*/ u32 bitfield; 204 u32 __reserved[3]; 205 } isr [8]; 206 207/*180*/ struct { /* Trigger Mode Register */ 208/*1F0*/ u32 bitfield; 209 u32 __reserved[3]; 210 } tmr [8]; 211 212/*200*/ struct { /* Interrupt Request Register */ 213/*270*/ u32 bitfield; 214 u32 __reserved[3]; 215 } irr [8]; 216 217/*280*/ union { /* Error Status Register */ 218 struct { 219 u32 send_cs_error : 1, 220 receive_cs_error : 1, 221 send_accept_error : 1, 222 receive_accept_error : 1, 223 __reserved_1 : 1, 224 send_illegal_vector : 1, 225 receive_illegal_vector : 1, 226 illegal_register_address : 1, 227 __reserved_2 : 24; 228 u32 __reserved_3[3]; 229 } error_bits; 230 struct { 231 u32 errors; 232 u32 __reserved_3[3]; 233 } all_errors; 234 } esr; 235 236/*290*/ struct { u32 __reserved[4]; } __reserved_08; 237 238/*2A0*/ struct { u32 __reserved[4]; } __reserved_09; 239 240/*2B0*/ struct { u32 __reserved[4]; } __reserved_10; 241 242/*2C0*/ struct { u32 __reserved[4]; } __reserved_11; 243 244/*2D0*/ struct { u32 __reserved[4]; } __reserved_12; 245 246/*2E0*/ struct { u32 __reserved[4]; } __reserved_13; 247 248/*2F0*/ struct { u32 __reserved[4]; } __reserved_14; 249 250/*300*/ struct { /* Interrupt Command Register 1 */ 251 u32 vector : 8, 252 delivery_mode : 3, 253 destination_mode : 1, 254 delivery_status : 1, 255 __reserved_1 : 1, 256 level : 1, 257 trigger : 1, 258 __reserved_2 : 2, 259 shorthand : 2, 260 __reserved_3 : 12; 261 u32 __reserved_4[3]; 262 } icr1; 263 264/*310*/ struct { /* Interrupt Command Register 2 */ 265 union { 266 u32 __reserved_1 : 24, 267 phys_dest : 4, 268 __reserved_2 : 4; 269 u32 __reserved_3 : 24, 270 logical_dest : 8; 271 } dest; 272 u32 __reserved_4[3]; 273 } icr2; 274 275/*320*/ struct { /* LVT - Timer */ 276 u32 vector : 8, 277 __reserved_1 : 4, 278 delivery_status : 1, 279 __reserved_2 : 3, 280 mask : 1, 281 timer_mode : 1, 282 __reserved_3 : 14; 283 u32 __reserved_4[3]; 284 } lvt_timer; 285 286/*330*/ struct { /* LVT - Thermal Sensor */ 287 u32 vector : 8, 288 delivery_mode : 3, 289 __reserved_1 : 1, 290 delivery_status : 1, 291 __reserved_2 : 3, 292 mask : 1, 293 __reserved_3 : 15; 294 u32 __reserved_4[3]; 295 } lvt_thermal; 296 297/*340*/ struct { /* LVT - Performance Counter */ 298 u32 vector : 8, 299 delivery_mode : 3, 300 __reserved_1 : 1, 301 delivery_status : 1, 302 __reserved_2 : 3, 303 mask : 1, 304 __reserved_3 : 15; 305 u32 __reserved_4[3]; 306 } lvt_pc; 307 308/*350*/ struct { /* LVT - LINT0 */ 309 u32 vector : 8, 310 delivery_mode : 3, 311 __reserved_1 : 1, 312 delivery_status : 1, 313 polarity : 1, 314 remote_irr : 1, 315 trigger : 1, 316 mask : 1, 317 __reserved_2 : 15; 318 u32 __reserved_3[3]; 319 } lvt_lint0; 320 321/*360*/ struct { /* LVT - LINT1 */ 322 u32 vector : 8, 323 delivery_mode : 3, 324 __reserved_1 : 1, 325 delivery_status : 1, 326 polarity : 1, 327 remote_irr : 1, 328 trigger : 1, 329 mask : 1, 330 __reserved_2 : 15; 331 u32 __reserved_3[3]; 332 } lvt_lint1; 333 334/*370*/ struct { /* LVT - Error */ 335 u32 vector : 8, 336 __reserved_1 : 4, 337 delivery_status : 1, 338 __reserved_2 : 3, 339 mask : 1, 340 __reserved_3 : 15; 341 u32 __reserved_4[3]; 342 } lvt_error; 343 344/*380*/ struct { /* Timer Initial Count Register */ 345 u32 initial_count; 346 u32 __reserved_2[3]; 347 } timer_icr; 348 349/*390*/ const 350 struct { /* Timer Current Count Register */ 351 u32 curr_count; 352 u32 __reserved_2[3]; 353 } timer_ccr; 354 355/*3A0*/ struct { u32 __reserved[4]; } __reserved_16; 356 357/*3B0*/ struct { u32 __reserved[4]; } __reserved_17; 358 359/*3C0*/ struct { u32 __reserved[4]; } __reserved_18; 360 361/*3D0*/ struct { u32 __reserved[4]; } __reserved_19; 362 363/*3E0*/ struct { /* Timer Divide Configuration Register */ 364 u32 divisor : 4, 365 __reserved_1 : 28; 366 u32 __reserved_2[3]; 367 } timer_dcr; 368 369/*3F0*/ struct { u32 __reserved[4]; } __reserved_20; 370 371} __attribute__ ((packed)); 372 373#undef u32 374 375#endif 376