SplitKit.cpp revision 4670353a21fbc6e8159a129cda965f256e73a451 
1//===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SplitAnalysis class as well as mutator functions for
11// live range splitting.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "regalloc"
16#include "SplitKit.h"
17#include "LiveRangeEdit.h"
18#include "VirtRegMap.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/CodeGen/CalcSpillWeights.h"
21#include "llvm/CodeGen/LiveIntervalAnalysis.h"
22#include "llvm/CodeGen/MachineDominators.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/Support/CommandLine.h"
26#include "llvm/Support/Debug.h"
27#include "llvm/Support/raw_ostream.h"
28#include "llvm/Target/TargetInstrInfo.h"
29#include "llvm/Target/TargetMachine.h"
30
31using namespace llvm;
32
33static cl::opt<bool>
34AllowSplit("spiller-splits-edges",
35           cl::desc("Allow critical edge splitting during spilling"));
36
37STATISTIC(NumFinished, "Number of splits finished");
38STATISTIC(NumSimple,   "Number of splits that were simple");
39
40//===----------------------------------------------------------------------===//
41//                                 Split Analysis
42//===----------------------------------------------------------------------===//
43
44SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
45                             const LiveIntervals &lis,
46                             const MachineLoopInfo &mli)
47  : MF(vrm.getMachineFunction()),
48    VRM(vrm),
49    LIS(lis),
50    Loops(mli),
51    TII(*MF.getTarget().getInstrInfo()),
52    CurLI(0) {}
53
54void SplitAnalysis::clear() {
55  UseSlots.clear();
56  UsingInstrs.clear();
57  UsingBlocks.clear();
58  LiveBlocks.clear();
59  CurLI = 0;
60}
61
62bool SplitAnalysis::canAnalyzeBranch(const MachineBasicBlock *MBB) {
63  MachineBasicBlock *T, *F;
64  SmallVector<MachineOperand, 4> Cond;
65  return !TII.AnalyzeBranch(const_cast<MachineBasicBlock&>(*MBB), T, F, Cond);
66}
67
68/// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
69void SplitAnalysis::analyzeUses() {
70  const MachineRegisterInfo &MRI = MF.getRegInfo();
71  for (MachineRegisterInfo::reg_iterator I = MRI.reg_begin(CurLI->reg),
72       E = MRI.reg_end(); I != E; ++I) {
73    MachineOperand &MO = I.getOperand();
74    if (MO.isUse() && MO.isUndef())
75      continue;
76    MachineInstr *MI = MO.getParent();
77    if (MI->isDebugValue() || !UsingInstrs.insert(MI))
78      continue;
79    UseSlots.push_back(LIS.getInstructionIndex(MI).getDefIndex());
80    MachineBasicBlock *MBB = MI->getParent();
81    UsingBlocks[MBB]++;
82  }
83  array_pod_sort(UseSlots.begin(), UseSlots.end());
84  calcLiveBlockInfo();
85  DEBUG(dbgs() << "  counted "
86               << UsingInstrs.size() << " instrs, "
87               << UsingBlocks.size() << " blocks.\n");
88}
89
90/// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
91/// where CurLI is live.
92void SplitAnalysis::calcLiveBlockInfo() {
93  if (CurLI->empty())
94    return;
95
96  LiveInterval::const_iterator LVI = CurLI->begin();
97  LiveInterval::const_iterator LVE = CurLI->end();
98
99  SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
100  UseI = UseSlots.begin();
101  UseE = UseSlots.end();
102
103  // Loop over basic blocks where CurLI is live.
104  MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
105  for (;;) {
106    BlockInfo BI;
107    BI.MBB = MFI;
108    SlotIndex Start, Stop;
109    tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
110
111    // The last split point is the latest possible insertion point that dominates
112    // all successor blocks. If interference reaches LastSplitPoint, it is not
113    // possible to insert a split or reload that makes CurLI live in the
114    // outgoing bundle.
115    MachineBasicBlock::iterator LSP = LIS.getLastSplitPoint(*CurLI, BI.MBB);
116    if (LSP == BI.MBB->end())
117      BI.LastSplitPoint = Stop;
118    else
119      BI.LastSplitPoint = LIS.getInstructionIndex(LSP);
120
121    // LVI is the first live segment overlapping MBB.
122    BI.LiveIn = LVI->start <= Start;
123    if (!BI.LiveIn)
124      BI.Def = LVI->start;
125
126    // Find the first and last uses in the block.
127    BI.Uses = hasUses(MFI);
128    if (BI.Uses && UseI != UseE) {
129      BI.FirstUse = *UseI;
130      assert(BI.FirstUse >= Start);
131      do ++UseI;
132      while (UseI != UseE && *UseI < Stop);
133      BI.LastUse = UseI[-1];
134      assert(BI.LastUse < Stop);
135    }
136
137    // Look for gaps in the live range.
138    bool hasGap = false;
139    BI.LiveOut = true;
140    while (LVI->end < Stop) {
141      SlotIndex LastStop = LVI->end;
142      if (++LVI == LVE || LVI->start >= Stop) {
143        BI.Kill = LastStop;
144        BI.LiveOut = false;
145        break;
146      }
147      if (LastStop < LVI->start) {
148        hasGap = true;
149        BI.Kill = LastStop;
150        BI.Def = LVI->start;
151      }
152    }
153
154    // Don't set LiveThrough when the block has a gap.
155    BI.LiveThrough = !hasGap && BI.LiveIn && BI.LiveOut;
156    LiveBlocks.push_back(BI);
157
158    // LVI is now at LVE or LVI->end >= Stop.
159    if (LVI == LVE)
160      break;
161
162    // Live segment ends exactly at Stop. Move to the next segment.
163    if (LVI->end == Stop && ++LVI == LVE)
164      break;
165
166    // Pick the next basic block.
167    if (LVI->start < Stop)
168      ++MFI;
169    else
170      MFI = LIS.getMBBFromIndex(LVI->start);
171  }
172}
173
174bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
175  unsigned OrigReg = VRM.getOriginal(CurLI->reg);
176  const LiveInterval &Orig = LIS.getInterval(OrigReg);
177  assert(!Orig.empty() && "Splitting empty interval?");
178  LiveInterval::const_iterator I = Orig.find(Idx);
179
180  // Range containing Idx should begin at Idx.
181  if (I != Orig.end() && I->start <= Idx)
182    return I->start == Idx;
183
184  // Range does not contain Idx, previous must end at Idx.
185  return I != Orig.begin() && (--I)->end == Idx;
186}
187
188void SplitAnalysis::print(const BlockPtrSet &B, raw_ostream &OS) const {
189  for (BlockPtrSet::const_iterator I = B.begin(), E = B.end(); I != E; ++I) {
190    unsigned count = UsingBlocks.lookup(*I);
191    OS << " BB#" << (*I)->getNumber();
192    if (count)
193      OS << '(' << count << ')';
194  }
195}
196
197void SplitAnalysis::analyze(const LiveInterval *li) {
198  clear();
199  CurLI = li;
200  analyzeUses();
201}
202
203
204//===----------------------------------------------------------------------===//
205//                               Split Editor
206//===----------------------------------------------------------------------===//
207
208/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
209SplitEditor::SplitEditor(SplitAnalysis &sa,
210                         LiveIntervals &lis,
211                         VirtRegMap &vrm,
212                         MachineDominatorTree &mdt,
213                         LiveRangeEdit &edit)
214  : SA(sa), LIS(lis), VRM(vrm),
215    MRI(vrm.getMachineFunction().getRegInfo()),
216    MDT(mdt),
217    TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
218    TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
219    Edit(edit),
220    OpenIdx(0),
221    RegAssign(Allocator)
222{
223  // We don't need an AliasAnalysis since we will only be performing
224  // cheap-as-a-copy remats anyway.
225  Edit.anyRematerializable(LIS, TII, 0);
226}
227
228void SplitEditor::dump() const {
229  if (RegAssign.empty()) {
230    dbgs() << " empty\n";
231    return;
232  }
233
234  for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
235    dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
236  dbgs() << '\n';
237}
238
239VNInfo *SplitEditor::defValue(unsigned RegIdx,
240                              const VNInfo *ParentVNI,
241                              SlotIndex Idx) {
242  assert(ParentVNI && "Mapping  NULL value");
243  assert(Idx.isValid() && "Invalid SlotIndex");
244  assert(Edit.getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
245  LiveInterval *LI = Edit.get(RegIdx);
246
247  // Create a new value.
248  VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
249
250  // Preserve the PHIDef bit.
251  if (ParentVNI->isPHIDef() && Idx == ParentVNI->def)
252    VNI->setIsPHIDef(true);
253
254  // Use insert for lookup, so we can add missing values with a second lookup.
255  std::pair<ValueMap::iterator, bool> InsP =
256    Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
257
258  // This was the first time (RegIdx, ParentVNI) was mapped.
259  // Keep it as a simple def without any liveness.
260  if (InsP.second)
261    return VNI;
262
263  // If the previous value was a simple mapping, add liveness for it now.
264  if (VNInfo *OldVNI = InsP.first->second) {
265    SlotIndex Def = OldVNI->def;
266    LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
267    // No longer a simple mapping.
268    InsP.first->second = 0;
269  }
270
271  // This is a complex mapping, add liveness for VNI
272  SlotIndex Def = VNI->def;
273  LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
274
275  return VNI;
276}
277
278void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
279  assert(ParentVNI && "Mapping  NULL value");
280  VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
281
282  // ParentVNI was either unmapped or already complex mapped. Either way.
283  if (!VNI)
284    return;
285
286  // This was previously a single mapping. Make sure the old def is represented
287  // by a trivial live range.
288  SlotIndex Def = VNI->def;
289  Edit.get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
290  VNI = 0;
291}
292
293// extendRange - Extend the live range to reach Idx.
294// Potentially create phi-def values.
295void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
296  assert(Idx.isValid() && "Invalid SlotIndex");
297  MachineBasicBlock *IdxMBB = LIS.getMBBFromIndex(Idx);
298  assert(IdxMBB && "No MBB at Idx");
299  LiveInterval *LI = Edit.get(RegIdx);
300
301  // Is there a def in the same MBB we can extend?
302  if (LI->extendInBlock(LIS.getMBBStartIdx(IdxMBB), Idx))
303    return;
304
305  // Now for the fun part. We know that ParentVNI potentially has multiple defs,
306  // and we may need to create even more phi-defs to preserve VNInfo SSA form.
307  // Perform a search for all predecessor blocks where we know the dominating
308  // VNInfo. Insert phi-def VNInfos along the path back to IdxMBB.
309  DEBUG(dbgs() << "\n  Reaching defs for BB#" << IdxMBB->getNumber()
310               << " at " << Idx << " in " << *LI << '\n');
311
312  // Blocks where LI should be live-in.
313  SmallVector<MachineDomTreeNode*, 16> LiveIn;
314  LiveIn.push_back(MDT[IdxMBB]);
315
316  // Using LiveOutCache as a visited set, perform a BFS for all reaching defs.
317  for (unsigned i = 0; i != LiveIn.size(); ++i) {
318    MachineBasicBlock *MBB = LiveIn[i]->getBlock();
319    for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
320           PE = MBB->pred_end(); PI != PE; ++PI) {
321       MachineBasicBlock *Pred = *PI;
322       // Is this a known live-out block?
323       std::pair<LiveOutMap::iterator,bool> LOIP =
324         LiveOutCache.insert(std::make_pair(Pred, LiveOutPair()));
325       // Yes, we have been here before.
326       if (!LOIP.second)
327         continue;
328
329       // Does Pred provide a live-out value?
330       SlotIndex Start, Last;
331       tie(Start, Last) = LIS.getSlotIndexes()->getMBBRange(Pred);
332       Last = Last.getPrevSlot();
333       if (VNInfo *VNI = LI->extendInBlock(Start, Last)) {
334         MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(VNI->def);
335         LiveOutPair &LOP = LOIP.first->second;
336         LOP.first = VNI;
337         LOP.second = MDT[DefMBB];
338         continue;
339       }
340       // No, we need a live-in value for Pred as well
341       if (Pred != IdxMBB)
342         LiveIn.push_back(MDT[Pred]);
343    }
344  }
345
346  // We may need to add phi-def values to preserve the SSA form.
347  VNInfo *IdxVNI = updateSSA(RegIdx, LiveIn, Idx, IdxMBB);
348
349#ifndef NDEBUG
350  // Check the LiveOutCache invariants.
351  for (LiveOutMap::iterator I = LiveOutCache.begin(), E = LiveOutCache.end();
352         I != E; ++I) {
353    assert(I->first && "Null MBB entry in cache");
354    assert(I->second.first && "Null VNInfo in cache");
355    assert(I->second.second && "Null DomTreeNode in cache");
356    if (I->second.second->getBlock() == I->first)
357      continue;
358    for (MachineBasicBlock::pred_iterator PI = I->first->pred_begin(),
359           PE = I->first->pred_end(); PI != PE; ++PI)
360      assert(LiveOutCache.lookup(*PI) == I->second && "Bad invariant");
361  }
362#endif
363
364  // Since we went through the trouble of a full BFS visiting all reaching defs,
365  // the values in LiveIn are now accurate. No more phi-defs are needed
366  // for these blocks, so we can color the live ranges.
367  for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) {
368    MachineBasicBlock *MBB = LiveIn[i]->getBlock();
369    SlotIndex Start = LIS.getMBBStartIdx(MBB);
370    VNInfo *VNI = LiveOutCache.lookup(MBB).first;
371
372    // Anything in LiveIn other than IdxMBB is live-through.
373    // In IdxMBB, we should stop at Idx unless the same value is live-out.
374    if (MBB == IdxMBB && IdxVNI != VNI)
375      LI->addRange(LiveRange(Start, Idx.getNextSlot(), IdxVNI));
376    else
377      LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
378  }
379}
380
381VNInfo *SplitEditor::updateSSA(unsigned RegIdx,
382                               SmallVectorImpl<MachineDomTreeNode*> &LiveIn,
383                               SlotIndex Idx,
384                               const MachineBasicBlock *IdxMBB) {
385  // This is essentially the same iterative algorithm that SSAUpdater uses,
386  // except we already have a dominator tree, so we don't have to recompute it.
387  LiveInterval *LI = Edit.get(RegIdx);
388  VNInfo *IdxVNI = 0;
389  unsigned Changes;
390  do {
391    Changes = 0;
392    DEBUG(dbgs() << "  Iterating over " << LiveIn.size() << " blocks.\n");
393    // Propagate live-out values down the dominator tree, inserting phi-defs
394    // when necessary. Since LiveIn was created by a BFS, going backwards makes
395    // it more likely for us to visit immediate dominators before their
396    // children.
397    for (unsigned i = LiveIn.size(); i; --i) {
398      MachineDomTreeNode *Node = LiveIn[i-1];
399      MachineBasicBlock *MBB = Node->getBlock();
400      MachineDomTreeNode *IDom = Node->getIDom();
401      LiveOutPair IDomValue;
402      // We need a live-in value to a block with no immediate dominator?
403      // This is probably an unreachable block that has survived somehow.
404      bool needPHI = !IDom;
405
406      // Get the IDom live-out value.
407      if (!needPHI) {
408        LiveOutMap::iterator I = LiveOutCache.find(IDom->getBlock());
409        if (I != LiveOutCache.end())
410          IDomValue = I->second;
411        else
412          // If IDom is outside our set of live-out blocks, there must be new
413          // defs, and we need a phi-def here.
414          needPHI = true;
415      }
416
417      // IDom dominates all of our predecessors, but it may not be the immediate
418      // dominator. Check if any of them have live-out values that are properly
419      // dominated by IDom. If so, we need a phi-def here.
420      if (!needPHI) {
421        for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
422               PE = MBB->pred_end(); PI != PE; ++PI) {
423          LiveOutPair Value = LiveOutCache[*PI];
424          if (!Value.first || Value.first == IDomValue.first)
425            continue;
426          // This predecessor is carrying something other than IDomValue.
427          // It could be because IDomValue hasn't propagated yet, or it could be
428          // because MBB is in the dominance frontier of that value.
429          if (MDT.dominates(IDom, Value.second)) {
430            needPHI = true;
431            break;
432          }
433        }
434      }
435
436      // Create a phi-def if required.
437      if (needPHI) {
438        ++Changes;
439        SlotIndex Start = LIS.getMBBStartIdx(MBB);
440        VNInfo *VNI = LI->getNextValue(Start, 0, LIS.getVNInfoAllocator());
441        VNI->setIsPHIDef(true);
442        DEBUG(dbgs() << "    - BB#" << MBB->getNumber()
443                     << " phi-def #" << VNI->id << " at " << Start << '\n');
444        // We no longer need LI to be live-in.
445        LiveIn.erase(LiveIn.begin()+(i-1));
446        // Blocks in LiveIn are either IdxMBB, or have a value live-through.
447        if (MBB == IdxMBB)
448          IdxVNI = VNI;
449        // Check if we need to update live-out info.
450        LiveOutMap::iterator I = LiveOutCache.find(MBB);
451        if (I == LiveOutCache.end() || I->second.second == Node) {
452          // We already have a live-out defined in MBB, so this must be IdxMBB.
453          assert(MBB == IdxMBB && "Adding phi-def to known live-out");
454          LI->addRange(LiveRange(Start, Idx.getNextSlot(), VNI));
455        } else {
456          // This phi-def is also live-out, so color the whole block.
457          LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
458          I->second = LiveOutPair(VNI, Node);
459        }
460      } else if (IDomValue.first) {
461        // No phi-def here. Remember incoming value for IdxMBB.
462        if (MBB == IdxMBB)
463          IdxVNI = IDomValue.first;
464        // Propagate IDomValue if needed:
465        // MBB is live-out and doesn't define its own value.
466        LiveOutMap::iterator I = LiveOutCache.find(MBB);
467        if (I != LiveOutCache.end() && I->second.second != Node &&
468            I->second.first != IDomValue.first) {
469          ++Changes;
470          I->second = IDomValue;
471          DEBUG(dbgs() << "    - BB#" << MBB->getNumber()
472                       << " idom valno #" << IDomValue.first->id
473                       << " from BB#" << IDom->getBlock()->getNumber() << '\n');
474        }
475      }
476    }
477    DEBUG(dbgs() << "  - made " << Changes << " changes.\n");
478  } while (Changes);
479
480  assert(IdxVNI && "Didn't find value for Idx");
481  return IdxVNI;
482}
483
484VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
485                                   VNInfo *ParentVNI,
486                                   SlotIndex UseIdx,
487                                   MachineBasicBlock &MBB,
488                                   MachineBasicBlock::iterator I) {
489  MachineInstr *CopyMI = 0;
490  SlotIndex Def;
491  LiveInterval *LI = Edit.get(RegIdx);
492
493  // Attempt cheap-as-a-copy rematerialization.
494  LiveRangeEdit::Remat RM(ParentVNI);
495  if (Edit.canRematerializeAt(RM, UseIdx, true, LIS)) {
496    Def = Edit.rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI);
497  } else {
498    // Can't remat, just insert a copy from parent.
499    CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
500               .addReg(Edit.getReg());
501    Def = LIS.InsertMachineInstrInMaps(CopyMI).getDefIndex();
502  }
503
504  // Define the value in Reg.
505  VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
506  VNI->setCopy(CopyMI);
507  return VNI;
508}
509
510/// Create a new virtual register and live interval.
511void SplitEditor::openIntv() {
512  assert(!OpenIdx && "Previous LI not closed before openIntv");
513
514  // Create the complement as index 0.
515  if (Edit.empty())
516    Edit.create(MRI, LIS, VRM);
517
518  // Create the open interval.
519  OpenIdx = Edit.size();
520  Edit.create(MRI, LIS, VRM);
521}
522
523SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
524  assert(OpenIdx && "openIntv not called before enterIntvBefore");
525  DEBUG(dbgs() << "    enterIntvBefore " << Idx);
526  Idx = Idx.getBaseIndex();
527  VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Idx);
528  if (!ParentVNI) {
529    DEBUG(dbgs() << ": not live\n");
530    return Idx;
531  }
532  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
533  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
534  assert(MI && "enterIntvBefore called with invalid index");
535
536  VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
537  return VNI->def;
538}
539
540SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
541  assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
542  SlotIndex End = LIS.getMBBEndIdx(&MBB);
543  SlotIndex Last = End.getPrevSlot();
544  DEBUG(dbgs() << "    enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
545  VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Last);
546  if (!ParentVNI) {
547    DEBUG(dbgs() << ": not live\n");
548    return End;
549  }
550  DEBUG(dbgs() << ": valno " << ParentVNI->id);
551  VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
552                              LIS.getLastSplitPoint(Edit.getParent(), &MBB));
553  RegAssign.insert(VNI->def, End, OpenIdx);
554  DEBUG(dump());
555  return VNI->def;
556}
557
558/// useIntv - indicate that all instructions in MBB should use OpenLI.
559void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
560  useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
561}
562
563void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
564  assert(OpenIdx && "openIntv not called before useIntv");
565  DEBUG(dbgs() << "    useIntv [" << Start << ';' << End << "):");
566  RegAssign.insert(Start, End, OpenIdx);
567  DEBUG(dump());
568}
569
570SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
571  assert(OpenIdx && "openIntv not called before leaveIntvAfter");
572  DEBUG(dbgs() << "    leaveIntvAfter " << Idx);
573
574  // The interval must be live beyond the instruction at Idx.
575  Idx = Idx.getBoundaryIndex();
576  VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Idx);
577  if (!ParentVNI) {
578    DEBUG(dbgs() << ": not live\n");
579    return Idx.getNextSlot();
580  }
581  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
582
583  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
584  assert(MI && "No instruction at index");
585  VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
586                              llvm::next(MachineBasicBlock::iterator(MI)));
587  return VNI->def;
588}
589
590SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
591  assert(OpenIdx && "openIntv not called before leaveIntvBefore");
592  DEBUG(dbgs() << "    leaveIntvBefore " << Idx);
593
594  // The interval must be live into the instruction at Idx.
595  Idx = Idx.getBoundaryIndex();
596  VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Idx);
597  if (!ParentVNI) {
598    DEBUG(dbgs() << ": not live\n");
599    return Idx.getNextSlot();
600  }
601  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
602
603  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
604  assert(MI && "No instruction at index");
605  VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
606  return VNI->def;
607}
608
609SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
610  assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
611  SlotIndex Start = LIS.getMBBStartIdx(&MBB);
612  DEBUG(dbgs() << "    leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
613
614  VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Start);
615  if (!ParentVNI) {
616    DEBUG(dbgs() << ": not live\n");
617    return Start;
618  }
619
620  VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
621                              MBB.SkipPHIsAndLabels(MBB.begin()));
622  RegAssign.insert(Start, VNI->def, OpenIdx);
623  DEBUG(dump());
624  return VNI->def;
625}
626
627void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
628  assert(OpenIdx && "openIntv not called before overlapIntv");
629  const VNInfo *ParentVNI = Edit.getParent().getVNInfoAt(Start);
630  assert(ParentVNI == Edit.getParent().getVNInfoAt(End.getPrevSlot()) &&
631         "Parent changes value in extended range");
632  assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
633         "Range cannot span basic blocks");
634
635  // The complement interval will be extended as needed by extendRange().
636  markComplexMapped(0, ParentVNI);
637  DEBUG(dbgs() << "    overlapIntv [" << Start << ';' << End << "):");
638  RegAssign.insert(Start, End, OpenIdx);
639  DEBUG(dump());
640}
641
642/// closeIntv - Indicate that we are done editing the currently open
643/// LiveInterval, and ranges can be trimmed.
644void SplitEditor::closeIntv() {
645  assert(OpenIdx && "openIntv not called before closeIntv");
646  OpenIdx = 0;
647}
648
649/// transferSimpleValues - Transfer all simply defined values to the new live
650/// ranges.
651/// Values that were rematerialized or that have multiple defs are left alone.
652bool SplitEditor::transferSimpleValues() {
653  bool Skipped = false;
654  RegAssignMap::const_iterator AssignI = RegAssign.begin();
655  for (LiveInterval::const_iterator ParentI = Edit.getParent().begin(),
656         ParentE = Edit.getParent().end(); ParentI != ParentE; ++ParentI) {
657    DEBUG(dbgs() << "  blit " << *ParentI << ':');
658    VNInfo *ParentVNI = ParentI->valno;
659    // RegAssign has holes where RegIdx 0 should be used.
660    SlotIndex Start = ParentI->start;
661    AssignI.advanceTo(Start);
662    do {
663      unsigned RegIdx;
664      SlotIndex End = ParentI->end;
665      if (!AssignI.valid()) {
666        RegIdx = 0;
667      } else if (AssignI.start() <= Start) {
668        RegIdx = AssignI.value();
669        if (AssignI.stop() < End) {
670          End = AssignI.stop();
671          ++AssignI;
672        }
673      } else {
674        RegIdx = 0;
675        End = std::min(End, AssignI.start());
676      }
677      DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
678      if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
679        DEBUG(dbgs() << ':' << VNI->id);
680        Edit.get(RegIdx)->addRange(LiveRange(Start, End, VNI));
681      } else
682        Skipped = true;
683      Start = End;
684    } while (Start != ParentI->end);
685    DEBUG(dbgs() << '\n');
686  }
687  return Skipped;
688}
689
690void SplitEditor::extendPHIKillRanges() {
691    // Extend live ranges to be live-out for successor PHI values.
692  for (LiveInterval::const_vni_iterator I = Edit.getParent().vni_begin(),
693       E = Edit.getParent().vni_end(); I != E; ++I) {
694    const VNInfo *PHIVNI = *I;
695    if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
696      continue;
697    unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
698    MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
699    for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
700         PE = MBB->pred_end(); PI != PE; ++PI) {
701      SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
702      // The predecessor may not have a live-out value. That is OK, like an
703      // undef PHI operand.
704      if (Edit.getParent().liveAt(End)) {
705        assert(RegAssign.lookup(End) == RegIdx &&
706               "Different register assignment in phi predecessor");
707        extendRange(RegIdx, End);
708      }
709    }
710  }
711}
712
713/// rewriteAssigned - Rewrite all uses of Edit.getReg().
714void SplitEditor::rewriteAssigned(bool ExtendRanges) {
715  for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit.getReg()),
716       RE = MRI.reg_end(); RI != RE;) {
717    MachineOperand &MO = RI.getOperand();
718    MachineInstr *MI = MO.getParent();
719    ++RI;
720    // LiveDebugVariables should have handled all DBG_VALUE instructions.
721    if (MI->isDebugValue()) {
722      DEBUG(dbgs() << "Zapping " << *MI);
723      MO.setReg(0);
724      continue;
725    }
726
727    // <undef> operands don't really read the register, so just assign them to
728    // the complement.
729    if (MO.isUse() && MO.isUndef()) {
730      MO.setReg(Edit.get(0)->reg);
731      continue;
732    }
733
734    SlotIndex Idx = LIS.getInstructionIndex(MI);
735    Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex();
736
737    // Rewrite to the mapped register at Idx.
738    unsigned RegIdx = RegAssign.lookup(Idx);
739    MO.setReg(Edit.get(RegIdx)->reg);
740    DEBUG(dbgs() << "  rewr BB#" << MI->getParent()->getNumber() << '\t'
741                 << Idx << ':' << RegIdx << '\t' << *MI);
742
743    // Extend liveness to Idx.
744    if (ExtendRanges)
745      extendRange(RegIdx, Idx);
746  }
747}
748
749/// rewriteSplit - Rewrite uses of Intvs[0] according to the ConEQ mapping.
750void SplitEditor::rewriteComponents(const SmallVectorImpl<LiveInterval*> &Intvs,
751                                    const ConnectedVNInfoEqClasses &ConEq) {
752  for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Intvs[0]->reg),
753       RE = MRI.reg_end(); RI != RE;) {
754    MachineOperand &MO = RI.getOperand();
755    MachineInstr *MI = MO.getParent();
756    ++RI;
757    if (MO.isUse() && MO.isUndef())
758      continue;
759    // DBG_VALUE instructions should have been eliminated earlier.
760    SlotIndex Idx = LIS.getInstructionIndex(MI);
761    Idx = MO.isUse() ? Idx.getUseIndex() : Idx.getDefIndex();
762    DEBUG(dbgs() << "  rewr BB#" << MI->getParent()->getNumber() << '\t'
763                 << Idx << ':');
764    const VNInfo *VNI = Intvs[0]->getVNInfoAt(Idx);
765    assert(VNI && "Interval not live at use.");
766    MO.setReg(Intvs[ConEq.getEqClass(VNI)]->reg);
767    DEBUG(dbgs() << VNI->id << '\t' << *MI);
768  }
769}
770
771void SplitEditor::finish() {
772  assert(OpenIdx == 0 && "Previous LI not closed before rewrite");
773  ++NumFinished;
774
775  // At this point, the live intervals in Edit contain VNInfos corresponding to
776  // the inserted copies.
777
778  // Add the original defs from the parent interval.
779  for (LiveInterval::const_vni_iterator I = Edit.getParent().vni_begin(),
780         E = Edit.getParent().vni_end(); I != E; ++I) {
781    const VNInfo *ParentVNI = *I;
782    if (ParentVNI->isUnused())
783      continue;
784    unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
785    defValue(RegIdx, ParentVNI, ParentVNI->def);
786    // Mark rematted values as complex everywhere to force liveness computation.
787    // The new live ranges may be truncated.
788    if (Edit.didRematerialize(ParentVNI))
789      for (unsigned i = 0, e = Edit.size(); i != e; ++i)
790        markComplexMapped(i, ParentVNI);
791  }
792
793#ifndef NDEBUG
794  // Every new interval must have a def by now, otherwise the split is bogus.
795  for (LiveRangeEdit::iterator I = Edit.begin(), E = Edit.end(); I != E; ++I)
796    assert((*I)->hasAtLeastOneValue() && "Split interval has no value");
797#endif
798
799  // Transfer the simply mapped values, check if any are complex.
800  bool Complex = transferSimpleValues();
801  if (Complex)
802    extendPHIKillRanges();
803  else
804    ++NumSimple;
805
806  // Rewrite virtual registers, possibly extending ranges.
807  rewriteAssigned(Complex);
808
809  // FIXME: Delete defs that were rematted everywhere.
810
811  // Get rid of unused values and set phi-kill flags.
812  for (LiveRangeEdit::iterator I = Edit.begin(), E = Edit.end(); I != E; ++I)
813    (*I)->RenumberValues(LIS);
814
815  // Now check if any registers were separated into multiple components.
816  ConnectedVNInfoEqClasses ConEQ(LIS);
817  for (unsigned i = 0, e = Edit.size(); i != e; ++i) {
818    // Don't use iterators, they are invalidated by create() below.
819    LiveInterval *li = Edit.get(i);
820    unsigned NumComp = ConEQ.Classify(li);
821    if (NumComp <= 1)
822      continue;
823    DEBUG(dbgs() << "  " << NumComp << " components: " << *li << '\n');
824    SmallVector<LiveInterval*, 8> dups;
825    dups.push_back(li);
826    for (unsigned i = 1; i != NumComp; ++i)
827      dups.push_back(&Edit.create(MRI, LIS, VRM));
828    rewriteComponents(dups, ConEQ);
829    ConEQ.Distribute(&dups[0]);
830  }
831
832  // Calculate spill weight and allocation hints for new intervals.
833  VirtRegAuxInfo vrai(VRM.getMachineFunction(), LIS, SA.Loops);
834  for (LiveRangeEdit::iterator I = Edit.begin(), E = Edit.end(); I != E; ++I){
835    LiveInterval &li = **I;
836    vrai.CalculateRegClass(li.reg);
837    vrai.CalculateWeightAndHint(li);
838    DEBUG(dbgs() << "  new interval " << MRI.getRegClass(li.reg)->getName()
839                 << ":" << li << '\n');
840  }
841}
842
843
844//===----------------------------------------------------------------------===//
845//                            Single Block Splitting
846//===----------------------------------------------------------------------===//
847
848/// getMultiUseBlocks - if CurLI has more than one use in a basic block, it
849/// may be an advantage to split CurLI for the duration of the block.
850bool SplitAnalysis::getMultiUseBlocks(BlockPtrSet &Blocks) {
851  // If CurLI is local to one block, there is no point to splitting it.
852  if (LiveBlocks.size() <= 1)
853    return false;
854  // Add blocks with multiple uses.
855  for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
856    const BlockInfo &BI = LiveBlocks[i];
857    if (!BI.Uses)
858      continue;
859    unsigned Instrs = UsingBlocks.lookup(BI.MBB);
860    if (Instrs <= 1)
861      continue;
862    if (Instrs == 2 && BI.LiveIn && BI.LiveOut && !BI.LiveThrough)
863      continue;
864    Blocks.insert(BI.MBB);
865  }
866  return !Blocks.empty();
867}
868
869/// splitSingleBlocks - Split CurLI into a separate live interval inside each
870/// basic block in Blocks.
871void SplitEditor::splitSingleBlocks(const SplitAnalysis::BlockPtrSet &Blocks) {
872  DEBUG(dbgs() << "  splitSingleBlocks for " << Blocks.size() << " blocks.\n");
873
874  for (unsigned i = 0, e = SA.LiveBlocks.size(); i != e; ++i) {
875    const SplitAnalysis::BlockInfo &BI = SA.LiveBlocks[i];
876    if (!BI.Uses || !Blocks.count(BI.MBB))
877      continue;
878
879    openIntv();
880    SlotIndex SegStart = enterIntvBefore(BI.FirstUse);
881    if (!BI.LiveOut || BI.LastUse < BI.LastSplitPoint) {
882      useIntv(SegStart, leaveIntvAfter(BI.LastUse));
883    } else {
884      // The last use is after the last valid split point.
885      SlotIndex SegStop = leaveIntvBefore(BI.LastSplitPoint);
886      useIntv(SegStart, SegStop);
887      overlapIntv(SegStop, BI.LastUse);
888    }
889    closeIntv();
890  }
891  finish();
892}
893