SplitKit.cpp revision b09701db9e74298912164d988ddf40bb1b5ec19b 
1//===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SplitAnalysis class as well as mutator functions for
11// live range splitting.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "regalloc"
16#include "SplitKit.h"
17#include "LiveRangeEdit.h"
18#include "VirtRegMap.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/CodeGen/LiveIntervalAnalysis.h"
21#include "llvm/CodeGen/MachineDominators.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/raw_ostream.h"
26#include "llvm/Target/TargetInstrInfo.h"
27#include "llvm/Target/TargetMachine.h"
28
29using namespace llvm;
30
31STATISTIC(NumFinished, "Number of splits finished");
32STATISTIC(NumSimple,   "Number of splits that were simple");
33STATISTIC(NumCopies,   "Number of copies inserted for splitting");
34STATISTIC(NumRemats,   "Number of rematerialized defs for splitting");
35STATISTIC(NumRepairs,  "Number of invalid live ranges repaired");
36
37//===----------------------------------------------------------------------===//
38//                                 Split Analysis
39//===----------------------------------------------------------------------===//
40
41SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
42                             const LiveIntervals &lis,
43                             const MachineLoopInfo &mli)
44  : MF(vrm.getMachineFunction()),
45    VRM(vrm),
46    LIS(lis),
47    Loops(mli),
48    TII(*MF.getTarget().getInstrInfo()),
49    CurLI(0),
50    LastSplitPoint(MF.getNumBlockIDs()) {}
51
52void SplitAnalysis::clear() {
53  UseSlots.clear();
54  UseBlocks.clear();
55  ThroughBlocks.clear();
56  CurLI = 0;
57  DidRepairRange = false;
58}
59
60SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
61  const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
62  const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
63  std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
64
65  // Compute split points on the first call. The pair is independent of the
66  // current live interval.
67  if (!LSP.first.isValid()) {
68    MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
69    if (FirstTerm == MBB->end())
70      LSP.first = LIS.getMBBEndIdx(MBB);
71    else
72      LSP.first = LIS.getInstructionIndex(FirstTerm);
73
74    // If there is a landing pad successor, also find the call instruction.
75    if (!LPad)
76      return LSP.first;
77    // There may not be a call instruction (?) in which case we ignore LPad.
78    LSP.second = LSP.first;
79    for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
80         I != E;) {
81      --I;
82      if (I->getDesc().isCall()) {
83        LSP.second = LIS.getInstructionIndex(I);
84        break;
85      }
86    }
87  }
88
89  // If CurLI is live into a landing pad successor, move the last split point
90  // back to the call that may throw.
91  if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
92    return LSP.second;
93  else
94    return LSP.first;
95}
96
97/// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
98void SplitAnalysis::analyzeUses() {
99  assert(UseSlots.empty() && "Call clear first");
100
101  // First get all the defs from the interval values. This provides the correct
102  // slots for early clobbers.
103  for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
104       E = CurLI->vni_end(); I != E; ++I)
105    if (!(*I)->isPHIDef() && !(*I)->isUnused())
106      UseSlots.push_back((*I)->def);
107
108  // Get use slots form the use-def chain.
109  const MachineRegisterInfo &MRI = MF.getRegInfo();
110  for (MachineRegisterInfo::use_nodbg_iterator
111       I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
112       ++I)
113    if (!I.getOperand().isUndef())
114      UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
115
116  array_pod_sort(UseSlots.begin(), UseSlots.end());
117
118  // Remove duplicates, keeping the smaller slot for each instruction.
119  // That is what we want for early clobbers.
120  UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
121                             SlotIndex::isSameInstr),
122                 UseSlots.end());
123
124  // Compute per-live block info.
125  if (!calcLiveBlockInfo()) {
126    // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
127    // I am looking at you, RegisterCoalescer!
128    DidRepairRange = true;
129    ++NumRepairs;
130    DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
131    const_cast<LiveIntervals&>(LIS)
132      .shrinkToUses(const_cast<LiveInterval*>(CurLI));
133    UseBlocks.clear();
134    ThroughBlocks.clear();
135    bool fixed = calcLiveBlockInfo();
136    (void)fixed;
137    assert(fixed && "Couldn't fix broken live interval");
138  }
139
140  DEBUG(dbgs() << "Analyze counted "
141               << UseSlots.size() << " instrs in "
142               << UseBlocks.size() << " blocks, through "
143               << NumThroughBlocks << " blocks.\n");
144}
145
146/// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
147/// where CurLI is live.
148bool SplitAnalysis::calcLiveBlockInfo() {
149  ThroughBlocks.resize(MF.getNumBlockIDs());
150  NumThroughBlocks = NumGapBlocks = 0;
151  if (CurLI->empty())
152    return true;
153
154  LiveInterval::const_iterator LVI = CurLI->begin();
155  LiveInterval::const_iterator LVE = CurLI->end();
156
157  SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
158  UseI = UseSlots.begin();
159  UseE = UseSlots.end();
160
161  // Loop over basic blocks where CurLI is live.
162  MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
163  for (;;) {
164    BlockInfo BI;
165    BI.MBB = MFI;
166    SlotIndex Start, Stop;
167    tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
168
169    // If the block contains no uses, the range must be live through. At one
170    // point, RegisterCoalescer could create dangling ranges that ended
171    // mid-block.
172    if (UseI == UseE || *UseI >= Stop) {
173      ++NumThroughBlocks;
174      ThroughBlocks.set(BI.MBB->getNumber());
175      // The range shouldn't end mid-block if there are no uses. This shouldn't
176      // happen.
177      if (LVI->end < Stop)
178        return false;
179    } else {
180      // This block has uses. Find the first and last uses in the block.
181      BI.FirstUse = *UseI;
182      assert(BI.FirstUse >= Start);
183      do ++UseI;
184      while (UseI != UseE && *UseI < Stop);
185      BI.LastUse = UseI[-1];
186      assert(BI.LastUse < Stop);
187
188      // LVI is the first live segment overlapping MBB.
189      BI.LiveIn = LVI->start <= Start;
190
191      // Look for gaps in the live range.
192      BI.LiveOut = true;
193      while (LVI->end < Stop) {
194        SlotIndex LastStop = LVI->end;
195        if (++LVI == LVE || LVI->start >= Stop) {
196          BI.LiveOut = false;
197          BI.LastUse = LastStop;
198          break;
199        }
200        if (LastStop < LVI->start) {
201          // There is a gap in the live range. Create duplicate entries for the
202          // live-in snippet and the live-out snippet.
203          ++NumGapBlocks;
204
205          // Push the Live-in part.
206          BI.LiveThrough = false;
207          BI.LiveOut = false;
208          UseBlocks.push_back(BI);
209          UseBlocks.back().LastUse = LastStop;
210
211          // Set up BI for the live-out part.
212          BI.LiveIn = false;
213          BI.LiveOut = true;
214          BI.FirstUse = LVI->start;
215        }
216      }
217
218      // Don't set LiveThrough when the block has a gap.
219      BI.LiveThrough = BI.LiveIn && BI.LiveOut;
220      UseBlocks.push_back(BI);
221
222      // LVI is now at LVE or LVI->end >= Stop.
223      if (LVI == LVE)
224        break;
225    }
226
227    // Live segment ends exactly at Stop. Move to the next segment.
228    if (LVI->end == Stop && ++LVI == LVE)
229      break;
230
231    // Pick the next basic block.
232    if (LVI->start < Stop)
233      ++MFI;
234    else
235      MFI = LIS.getMBBFromIndex(LVI->start);
236  }
237
238  assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
239  return true;
240}
241
242unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
243  if (cli->empty())
244    return 0;
245  LiveInterval *li = const_cast<LiveInterval*>(cli);
246  LiveInterval::iterator LVI = li->begin();
247  LiveInterval::iterator LVE = li->end();
248  unsigned Count = 0;
249
250  // Loop over basic blocks where li is live.
251  MachineFunction::const_iterator MFI = LIS.getMBBFromIndex(LVI->start);
252  SlotIndex Stop = LIS.getMBBEndIdx(MFI);
253  for (;;) {
254    ++Count;
255    LVI = li->advanceTo(LVI, Stop);
256    if (LVI == LVE)
257      return Count;
258    do {
259      ++MFI;
260      Stop = LIS.getMBBEndIdx(MFI);
261    } while (Stop <= LVI->start);
262  }
263}
264
265bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
266  unsigned OrigReg = VRM.getOriginal(CurLI->reg);
267  const LiveInterval &Orig = LIS.getInterval(OrigReg);
268  assert(!Orig.empty() && "Splitting empty interval?");
269  LiveInterval::const_iterator I = Orig.find(Idx);
270
271  // Range containing Idx should begin at Idx.
272  if (I != Orig.end() && I->start <= Idx)
273    return I->start == Idx;
274
275  // Range does not contain Idx, previous must end at Idx.
276  return I != Orig.begin() && (--I)->end == Idx;
277}
278
279void SplitAnalysis::analyze(const LiveInterval *li) {
280  clear();
281  CurLI = li;
282  analyzeUses();
283}
284
285
286//===----------------------------------------------------------------------===//
287//                               Split Editor
288//===----------------------------------------------------------------------===//
289
290/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
291SplitEditor::SplitEditor(SplitAnalysis &sa,
292                         LiveIntervals &lis,
293                         VirtRegMap &vrm,
294                         MachineDominatorTree &mdt)
295  : SA(sa), LIS(lis), VRM(vrm),
296    MRI(vrm.getMachineFunction().getRegInfo()),
297    MDT(mdt),
298    TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
299    TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
300    Edit(0),
301    OpenIdx(0),
302    RegAssign(Allocator)
303{}
304
305void SplitEditor::reset(LiveRangeEdit &lre) {
306  Edit = &lre;
307  OpenIdx = 0;
308  RegAssign.clear();
309  Values.clear();
310
311  // We don't need to clear LiveOutCache, only LiveOutSeen entries are read.
312  LiveOutSeen.clear();
313
314  // We don't need an AliasAnalysis since we will only be performing
315  // cheap-as-a-copy remats anyway.
316  Edit->anyRematerializable(LIS, TII, 0);
317}
318
319void SplitEditor::dump() const {
320  if (RegAssign.empty()) {
321    dbgs() << " empty\n";
322    return;
323  }
324
325  for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
326    dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
327  dbgs() << '\n';
328}
329
330VNInfo *SplitEditor::defValue(unsigned RegIdx,
331                              const VNInfo *ParentVNI,
332                              SlotIndex Idx) {
333  assert(ParentVNI && "Mapping  NULL value");
334  assert(Idx.isValid() && "Invalid SlotIndex");
335  assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
336  LiveInterval *LI = Edit->get(RegIdx);
337
338  // Create a new value.
339  VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
340
341  // Use insert for lookup, so we can add missing values with a second lookup.
342  std::pair<ValueMap::iterator, bool> InsP =
343    Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
344
345  // This was the first time (RegIdx, ParentVNI) was mapped.
346  // Keep it as a simple def without any liveness.
347  if (InsP.second)
348    return VNI;
349
350  // If the previous value was a simple mapping, add liveness for it now.
351  if (VNInfo *OldVNI = InsP.first->second) {
352    SlotIndex Def = OldVNI->def;
353    LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
354    // No longer a simple mapping.
355    InsP.first->second = 0;
356  }
357
358  // This is a complex mapping, add liveness for VNI
359  SlotIndex Def = VNI->def;
360  LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
361
362  return VNI;
363}
364
365void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
366  assert(ParentVNI && "Mapping  NULL value");
367  VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
368
369  // ParentVNI was either unmapped or already complex mapped. Either way.
370  if (!VNI)
371    return;
372
373  // This was previously a single mapping. Make sure the old def is represented
374  // by a trivial live range.
375  SlotIndex Def = VNI->def;
376  Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
377  VNI = 0;
378}
379
380// extendRange - Extend the live range to reach Idx.
381// Potentially create phi-def values.
382void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
383  assert(Idx.isValid() && "Invalid SlotIndex");
384  MachineBasicBlock *IdxMBB = LIS.getMBBFromIndex(Idx);
385  assert(IdxMBB && "No MBB at Idx");
386  LiveInterval *LI = Edit->get(RegIdx);
387
388  // Is there a def in the same MBB we can extend?
389  if (LI->extendInBlock(LIS.getMBBStartIdx(IdxMBB), Idx))
390    return;
391
392  // Now for the fun part. We know that ParentVNI potentially has multiple defs,
393  // and we may need to create even more phi-defs to preserve VNInfo SSA form.
394  // Perform a search for all predecessor blocks where we know the dominating
395  // VNInfo.
396  VNInfo *VNI = findReachingDefs(LI, IdxMBB, Idx.getNextSlot());
397
398  // When there were multiple different values, we may need new PHIs.
399  if (!VNI)
400    return updateSSA();
401
402  // Poor man's SSA update for the single-value case.
403  LiveOutPair LOP(VNI, MDT[LIS.getMBBFromIndex(VNI->def)]);
404  for (SmallVectorImpl<LiveInBlock>::iterator I = LiveInBlocks.begin(),
405         E = LiveInBlocks.end(); I != E; ++I) {
406    MachineBasicBlock *MBB = I->DomNode->getBlock();
407    SlotIndex Start = LIS.getMBBStartIdx(MBB);
408    if (I->Kill.isValid())
409      LI->addRange(LiveRange(Start, I->Kill, VNI));
410    else {
411      LiveOutCache[MBB] = LOP;
412      LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
413    }
414  }
415}
416
417/// findReachingDefs - Search the CFG for known live-out values.
418/// Add required live-in blocks to LiveInBlocks.
419VNInfo *SplitEditor::findReachingDefs(LiveInterval *LI,
420                                      MachineBasicBlock *KillMBB,
421                                      SlotIndex Kill) {
422  // Initialize the live-out cache the first time it is needed.
423  if (LiveOutSeen.empty()) {
424    unsigned N = VRM.getMachineFunction().getNumBlockIDs();
425    LiveOutSeen.resize(N);
426    LiveOutCache.resize(N);
427  }
428
429  // Blocks where LI should be live-in.
430  SmallVector<MachineBasicBlock*, 16> WorkList(1, KillMBB);
431
432  // Remember if we have seen more than one value.
433  bool UniqueVNI = true;
434  VNInfo *TheVNI = 0;
435
436  // Using LiveOutCache as a visited set, perform a BFS for all reaching defs.
437  for (unsigned i = 0; i != WorkList.size(); ++i) {
438    MachineBasicBlock *MBB = WorkList[i];
439    assert(!MBB->pred_empty() && "Value live-in to entry block?");
440    for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
441           PE = MBB->pred_end(); PI != PE; ++PI) {
442       MachineBasicBlock *Pred = *PI;
443       LiveOutPair &LOP = LiveOutCache[Pred];
444
445       // Is this a known live-out block?
446       if (LiveOutSeen.test(Pred->getNumber())) {
447         if (VNInfo *VNI = LOP.first) {
448           if (TheVNI && TheVNI != VNI)
449             UniqueVNI = false;
450           TheVNI = VNI;
451         }
452         continue;
453       }
454
455       // First time. LOP is garbage and must be cleared below.
456       LiveOutSeen.set(Pred->getNumber());
457
458       // Does Pred provide a live-out value?
459       SlotIndex Start, Last;
460       tie(Start, Last) = LIS.getSlotIndexes()->getMBBRange(Pred);
461       Last = Last.getPrevSlot();
462       VNInfo *VNI = LI->extendInBlock(Start, Last);
463       LOP.first = VNI;
464       if (VNI) {
465         LOP.second = MDT[LIS.getMBBFromIndex(VNI->def)];
466         if (TheVNI && TheVNI != VNI)
467           UniqueVNI = false;
468         TheVNI = VNI;
469         continue;
470       }
471       LOP.second = 0;
472
473       // No, we need a live-in value for Pred as well
474       if (Pred != KillMBB)
475          WorkList.push_back(Pred);
476       else
477          // Loopback to KillMBB, so value is really live through.
478         Kill = SlotIndex();
479    }
480  }
481
482  // Transfer WorkList to LiveInBlocks in reverse order.
483  // This ordering works best with updateSSA().
484  LiveInBlocks.clear();
485  LiveInBlocks.reserve(WorkList.size());
486  while(!WorkList.empty())
487    LiveInBlocks.push_back(MDT[WorkList.pop_back_val()]);
488
489  // The kill block may not be live-through.
490  assert(LiveInBlocks.back().DomNode->getBlock() == KillMBB);
491  LiveInBlocks.back().Kill = Kill;
492
493  return UniqueVNI ? TheVNI : 0;
494}
495
496void SplitEditor::updateSSA() {
497  // This is essentially the same iterative algorithm that SSAUpdater uses,
498  // except we already have a dominator tree, so we don't have to recompute it.
499  unsigned Changes;
500  do {
501    Changes = 0;
502    // Propagate live-out values down the dominator tree, inserting phi-defs
503    // when necessary.
504    for (SmallVectorImpl<LiveInBlock>::iterator I = LiveInBlocks.begin(),
505           E = LiveInBlocks.end(); I != E; ++I) {
506      MachineDomTreeNode *Node = I->DomNode;
507      // Skip block if the live-in value has already been determined.
508      if (!Node)
509        continue;
510      MachineBasicBlock *MBB = Node->getBlock();
511      MachineDomTreeNode *IDom = Node->getIDom();
512      LiveOutPair IDomValue;
513
514      // We need a live-in value to a block with no immediate dominator?
515      // This is probably an unreachable block that has survived somehow.
516      bool needPHI = !IDom || !LiveOutSeen.test(IDom->getBlock()->getNumber());
517
518      // IDom dominates all of our predecessors, but it may not be their
519      // immediate dominator. Check if any of them have live-out values that are
520      // properly dominated by IDom. If so, we need a phi-def here.
521      if (!needPHI) {
522        IDomValue = LiveOutCache[IDom->getBlock()];
523        for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
524               PE = MBB->pred_end(); PI != PE; ++PI) {
525          LiveOutPair Value = LiveOutCache[*PI];
526          if (!Value.first || Value.first == IDomValue.first)
527            continue;
528          // This predecessor is carrying something other than IDomValue.
529          // It could be because IDomValue hasn't propagated yet, or it could be
530          // because MBB is in the dominance frontier of that value.
531          if (MDT.dominates(IDom, Value.second)) {
532            needPHI = true;
533            break;
534          }
535        }
536      }
537
538      // The value may be live-through even if Kill is set, as can happen when
539      // we are called from extendRange. In that case LiveOutSeen is true, and
540      // LiveOutCache indicates a foreign or missing value.
541      LiveOutPair &LOP = LiveOutCache[MBB];
542
543      // Create a phi-def if required.
544      if (needPHI) {
545        ++Changes;
546        SlotIndex Start = LIS.getMBBStartIdx(MBB);
547        unsigned RegIdx = RegAssign.lookup(Start);
548        LiveInterval *LI = Edit->get(RegIdx);
549        VNInfo *VNI = LI->getNextValue(Start, 0, LIS.getVNInfoAllocator());
550        VNI->setIsPHIDef(true);
551        I->Value = VNI;
552        // This block is done, we know the final value.
553        I->DomNode = 0;
554        if (I->Kill.isValid())
555          LI->addRange(LiveRange(Start, I->Kill, VNI));
556        else {
557          LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
558          LOP = LiveOutPair(VNI, Node);
559        }
560      } else if (IDomValue.first) {
561        // No phi-def here. Remember incoming value.
562        I->Value = IDomValue.first;
563        if (I->Kill.isValid())
564          continue;
565        // Propagate IDomValue if needed:
566        // MBB is live-out and doesn't define its own value.
567        if (LOP.second != Node && LOP.first != IDomValue.first) {
568          ++Changes;
569          LOP = IDomValue;
570        }
571      }
572    }
573  } while (Changes);
574
575  // The values in LiveInBlocks are now accurate. No more phi-defs are needed
576  // for these blocks, so we can color the live ranges.
577  for (SmallVectorImpl<LiveInBlock>::iterator I = LiveInBlocks.begin(),
578         E = LiveInBlocks.end(); I != E; ++I) {
579    if (!I->DomNode)
580      continue;
581    assert(I->Value && "No live-in value found");
582    MachineBasicBlock *MBB = I->DomNode->getBlock();
583    SlotIndex Start = LIS.getMBBStartIdx(MBB);
584    unsigned RegIdx = RegAssign.lookup(Start);
585    LiveInterval *LI = Edit->get(RegIdx);
586    LI->addRange(LiveRange(Start, I->Kill.isValid() ?
587                                  I->Kill : LIS.getMBBEndIdx(MBB), I->Value));
588  }
589}
590
591VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
592                                   VNInfo *ParentVNI,
593                                   SlotIndex UseIdx,
594                                   MachineBasicBlock &MBB,
595                                   MachineBasicBlock::iterator I) {
596  MachineInstr *CopyMI = 0;
597  SlotIndex Def;
598  LiveInterval *LI = Edit->get(RegIdx);
599
600  // We may be trying to avoid interference that ends at a deleted instruction,
601  // so always begin RegIdx 0 early and all others late.
602  bool Late = RegIdx != 0;
603
604  // Attempt cheap-as-a-copy rematerialization.
605  LiveRangeEdit::Remat RM(ParentVNI);
606  if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
607    Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI, Late);
608    ++NumRemats;
609  } else {
610    // Can't remat, just insert a copy from parent.
611    CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
612               .addReg(Edit->getReg());
613    Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
614            .getDefIndex();
615    ++NumCopies;
616  }
617
618  // Define the value in Reg.
619  VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
620  VNI->setCopy(CopyMI);
621  return VNI;
622}
623
624/// Create a new virtual register and live interval.
625unsigned SplitEditor::openIntv() {
626  // Create the complement as index 0.
627  if (Edit->empty())
628    Edit->create(LIS, VRM);
629
630  // Create the open interval.
631  OpenIdx = Edit->size();
632  Edit->create(LIS, VRM);
633  return OpenIdx;
634}
635
636void SplitEditor::selectIntv(unsigned Idx) {
637  assert(Idx != 0 && "Cannot select the complement interval");
638  assert(Idx < Edit->size() && "Can only select previously opened interval");
639  DEBUG(dbgs() << "    selectIntv " << OpenIdx << " -> " << Idx << '\n');
640  OpenIdx = Idx;
641}
642
643SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
644  assert(OpenIdx && "openIntv not called before enterIntvBefore");
645  DEBUG(dbgs() << "    enterIntvBefore " << Idx);
646  Idx = Idx.getBaseIndex();
647  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
648  if (!ParentVNI) {
649    DEBUG(dbgs() << ": not live\n");
650    return Idx;
651  }
652  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
653  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
654  assert(MI && "enterIntvBefore called with invalid index");
655
656  VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
657  return VNI->def;
658}
659
660SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
661  assert(OpenIdx && "openIntv not called before enterIntvAfter");
662  DEBUG(dbgs() << "    enterIntvAfter " << Idx);
663  Idx = Idx.getBoundaryIndex();
664  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
665  if (!ParentVNI) {
666    DEBUG(dbgs() << ": not live\n");
667    return Idx;
668  }
669  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
670  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
671  assert(MI && "enterIntvAfter called with invalid index");
672
673  VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
674                              llvm::next(MachineBasicBlock::iterator(MI)));
675  return VNI->def;
676}
677
678SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
679  assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
680  SlotIndex End = LIS.getMBBEndIdx(&MBB);
681  SlotIndex Last = End.getPrevSlot();
682  DEBUG(dbgs() << "    enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
683  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
684  if (!ParentVNI) {
685    DEBUG(dbgs() << ": not live\n");
686    return End;
687  }
688  DEBUG(dbgs() << ": valno " << ParentVNI->id);
689  VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
690                              LIS.getLastSplitPoint(Edit->getParent(), &MBB));
691  RegAssign.insert(VNI->def, End, OpenIdx);
692  DEBUG(dump());
693  return VNI->def;
694}
695
696/// useIntv - indicate that all instructions in MBB should use OpenLI.
697void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
698  useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
699}
700
701void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
702  assert(OpenIdx && "openIntv not called before useIntv");
703  DEBUG(dbgs() << "    useIntv [" << Start << ';' << End << "):");
704  RegAssign.insert(Start, End, OpenIdx);
705  DEBUG(dump());
706}
707
708SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
709  assert(OpenIdx && "openIntv not called before leaveIntvAfter");
710  DEBUG(dbgs() << "    leaveIntvAfter " << Idx);
711
712  // The interval must be live beyond the instruction at Idx.
713  Idx = Idx.getBoundaryIndex();
714  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
715  if (!ParentVNI) {
716    DEBUG(dbgs() << ": not live\n");
717    return Idx.getNextSlot();
718  }
719  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
720
721  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
722  assert(MI && "No instruction at index");
723  VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
724                              llvm::next(MachineBasicBlock::iterator(MI)));
725  return VNI->def;
726}
727
728SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
729  assert(OpenIdx && "openIntv not called before leaveIntvBefore");
730  DEBUG(dbgs() << "    leaveIntvBefore " << Idx);
731
732  // The interval must be live into the instruction at Idx.
733  Idx = Idx.getBaseIndex();
734  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
735  if (!ParentVNI) {
736    DEBUG(dbgs() << ": not live\n");
737    return Idx.getNextSlot();
738  }
739  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
740
741  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
742  assert(MI && "No instruction at index");
743  VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
744  return VNI->def;
745}
746
747SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
748  assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
749  SlotIndex Start = LIS.getMBBStartIdx(&MBB);
750  DEBUG(dbgs() << "    leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
751
752  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
753  if (!ParentVNI) {
754    DEBUG(dbgs() << ": not live\n");
755    return Start;
756  }
757
758  VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
759                              MBB.SkipPHIsAndLabels(MBB.begin()));
760  RegAssign.insert(Start, VNI->def, OpenIdx);
761  DEBUG(dump());
762  return VNI->def;
763}
764
765void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
766  assert(OpenIdx && "openIntv not called before overlapIntv");
767  const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
768  assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
769         "Parent changes value in extended range");
770  assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
771         "Range cannot span basic blocks");
772
773  // The complement interval will be extended as needed by extendRange().
774  if (ParentVNI)
775    markComplexMapped(0, ParentVNI);
776  DEBUG(dbgs() << "    overlapIntv [" << Start << ';' << End << "):");
777  RegAssign.insert(Start, End, OpenIdx);
778  DEBUG(dump());
779}
780
781/// transferValues - Transfer all possible values to the new live ranges.
782/// Values that were rematerialized are left alone, they need extendRange().
783bool SplitEditor::transferValues() {
784  bool Skipped = false;
785  LiveInBlocks.clear();
786  RegAssignMap::const_iterator AssignI = RegAssign.begin();
787  for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
788         ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
789    DEBUG(dbgs() << "  blit " << *ParentI << ':');
790    VNInfo *ParentVNI = ParentI->valno;
791    // RegAssign has holes where RegIdx 0 should be used.
792    SlotIndex Start = ParentI->start;
793    AssignI.advanceTo(Start);
794    do {
795      unsigned RegIdx;
796      SlotIndex End = ParentI->end;
797      if (!AssignI.valid()) {
798        RegIdx = 0;
799      } else if (AssignI.start() <= Start) {
800        RegIdx = AssignI.value();
801        if (AssignI.stop() < End) {
802          End = AssignI.stop();
803          ++AssignI;
804        }
805      } else {
806        RegIdx = 0;
807        End = std::min(End, AssignI.start());
808      }
809
810      // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
811      DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
812      LiveInterval *LI = Edit->get(RegIdx);
813
814      // Check for a simply defined value that can be blitted directly.
815      if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
816        DEBUG(dbgs() << ':' << VNI->id);
817        LI->addRange(LiveRange(Start, End, VNI));
818        Start = End;
819        continue;
820      }
821
822      // Skip rematerialized values, we need to use extendRange() and
823      // extendPHIKillRanges() to completely recompute the live ranges.
824      if (Edit->didRematerialize(ParentVNI)) {
825        DEBUG(dbgs() << "(remat)");
826        Skipped = true;
827        Start = End;
828        continue;
829      }
830
831      // Initialize the live-out cache the first time it is needed.
832      if (LiveOutSeen.empty()) {
833        unsigned N = VRM.getMachineFunction().getNumBlockIDs();
834        LiveOutSeen.resize(N);
835        LiveOutCache.resize(N);
836      }
837
838      // This value has multiple defs in RegIdx, but it wasn't rematerialized,
839      // so the live range is accurate. Add live-in blocks in [Start;End) to the
840      // LiveInBlocks.
841      MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
842      SlotIndex BlockStart, BlockEnd;
843      tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB);
844
845      // The first block may be live-in, or it may have its own def.
846      if (Start != BlockStart) {
847        VNInfo *VNI = LI->extendInBlock(BlockStart,
848                                        std::min(BlockEnd, End).getPrevSlot());
849        assert(VNI && "Missing def for complex mapped value");
850        DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
851        // MBB has its own def. Is it also live-out?
852        if (BlockEnd <= End) {
853          LiveOutSeen.set(MBB->getNumber());
854          LiveOutCache[MBB] = LiveOutPair(VNI, MDT[MBB]);
855        }
856        // Skip to the next block for live-in.
857        ++MBB;
858        BlockStart = BlockEnd;
859      }
860
861      // Handle the live-in blocks covered by [Start;End).
862      assert(Start <= BlockStart && "Expected live-in block");
863      while (BlockStart < End) {
864        DEBUG(dbgs() << ">BB#" << MBB->getNumber());
865        BlockEnd = LIS.getMBBEndIdx(MBB);
866        if (BlockStart == ParentVNI->def) {
867          // This block has the def of a parent PHI, so it isn't live-in.
868          assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
869          VNInfo *VNI = LI->extendInBlock(BlockStart,
870                                         std::min(BlockEnd, End).getPrevSlot());
871          assert(VNI && "Missing def for complex mapped parent PHI");
872          if (End >= BlockEnd) {
873            // Live-out as well.
874            LiveOutSeen.set(MBB->getNumber());
875            LiveOutCache[MBB] = LiveOutPair(VNI, MDT[MBB]);
876          }
877        } else {
878          // This block needs a live-in value.
879          LiveInBlocks.push_back(MDT[MBB]);
880          // The last block covered may not be live-out.
881          if (End < BlockEnd)
882            LiveInBlocks.back().Kill = End;
883          else {
884            // Live-out, but we need updateSSA to tell us the value.
885            LiveOutSeen.set(MBB->getNumber());
886            LiveOutCache[MBB] = LiveOutPair((VNInfo*)0,
887                                            (MachineDomTreeNode*)0);
888          }
889        }
890        BlockStart = BlockEnd;
891        ++MBB;
892      }
893      Start = End;
894    } while (Start != ParentI->end);
895    DEBUG(dbgs() << '\n');
896  }
897
898  if (!LiveInBlocks.empty())
899    updateSSA();
900
901  return Skipped;
902}
903
904void SplitEditor::extendPHIKillRanges() {
905    // Extend live ranges to be live-out for successor PHI values.
906  for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
907       E = Edit->getParent().vni_end(); I != E; ++I) {
908    const VNInfo *PHIVNI = *I;
909    if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
910      continue;
911    unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
912    MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
913    for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
914         PE = MBB->pred_end(); PI != PE; ++PI) {
915      SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
916      // The predecessor may not have a live-out value. That is OK, like an
917      // undef PHI operand.
918      if (Edit->getParent().liveAt(End)) {
919        assert(RegAssign.lookup(End) == RegIdx &&
920               "Different register assignment in phi predecessor");
921        extendRange(RegIdx, End);
922      }
923    }
924  }
925}
926
927/// rewriteAssigned - Rewrite all uses of Edit->getReg().
928void SplitEditor::rewriteAssigned(bool ExtendRanges) {
929  for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
930       RE = MRI.reg_end(); RI != RE;) {
931    MachineOperand &MO = RI.getOperand();
932    MachineInstr *MI = MO.getParent();
933    ++RI;
934    // LiveDebugVariables should have handled all DBG_VALUE instructions.
935    if (MI->isDebugValue()) {
936      DEBUG(dbgs() << "Zapping " << *MI);
937      MO.setReg(0);
938      continue;
939    }
940
941    // <undef> operands don't really read the register, so it doesn't matter
942    // which register we choose.  When the use operand is tied to a def, we must
943    // use the same register as the def, so just do that always.
944    SlotIndex Idx = LIS.getInstructionIndex(MI);
945    if (MO.isDef() || MO.isUndef())
946      Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex();
947
948    // Rewrite to the mapped register at Idx.
949    unsigned RegIdx = RegAssign.lookup(Idx);
950    MO.setReg(Edit->get(RegIdx)->reg);
951    DEBUG(dbgs() << "  rewr BB#" << MI->getParent()->getNumber() << '\t'
952                 << Idx << ':' << RegIdx << '\t' << *MI);
953
954    // Extend liveness to Idx if the instruction reads reg.
955    if (!ExtendRanges)
956      continue;
957
958    // Skip instructions that don't read Reg.
959    if (MO.isDef()) {
960      if (!MO.getSubReg() && !MO.isEarlyClobber())
961        continue;
962      // We may wan't to extend a live range for a partial redef, or for a use
963      // tied to an early clobber.
964      Idx = Idx.getPrevSlot();
965      if (!Edit->getParent().liveAt(Idx))
966        continue;
967    } else
968      Idx = Idx.getUseIndex();
969
970    extendRange(RegIdx, Idx);
971  }
972}
973
974void SplitEditor::deleteRematVictims() {
975  SmallVector<MachineInstr*, 8> Dead;
976  for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
977    LiveInterval *LI = *I;
978    for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
979           LII != LIE; ++LII) {
980      // Dead defs end at the store slot.
981      if (LII->end != LII->valno->def.getNextSlot())
982        continue;
983      MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
984      assert(MI && "Missing instruction for dead def");
985      MI->addRegisterDead(LI->reg, &TRI);
986
987      if (!MI->allDefsAreDead())
988        continue;
989
990      DEBUG(dbgs() << "All defs dead: " << *MI);
991      Dead.push_back(MI);
992    }
993  }
994
995  if (Dead.empty())
996    return;
997
998  Edit->eliminateDeadDefs(Dead, LIS, VRM, TII);
999}
1000
1001void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
1002  ++NumFinished;
1003
1004  // At this point, the live intervals in Edit contain VNInfos corresponding to
1005  // the inserted copies.
1006
1007  // Add the original defs from the parent interval.
1008  for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
1009         E = Edit->getParent().vni_end(); I != E; ++I) {
1010    const VNInfo *ParentVNI = *I;
1011    if (ParentVNI->isUnused())
1012      continue;
1013    unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
1014    VNInfo *VNI = defValue(RegIdx, ParentVNI, ParentVNI->def);
1015    VNI->setIsPHIDef(ParentVNI->isPHIDef());
1016    VNI->setCopy(ParentVNI->getCopy());
1017
1018    // Mark rematted values as complex everywhere to force liveness computation.
1019    // The new live ranges may be truncated.
1020    if (Edit->didRematerialize(ParentVNI))
1021      for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1022        markComplexMapped(i, ParentVNI);
1023  }
1024
1025  // Transfer the simply mapped values, check if any are skipped.
1026  bool Skipped = transferValues();
1027  if (Skipped)
1028    extendPHIKillRanges();
1029  else
1030    ++NumSimple;
1031
1032  // Rewrite virtual registers, possibly extending ranges.
1033  rewriteAssigned(Skipped);
1034
1035  // Delete defs that were rematted everywhere.
1036  if (Skipped)
1037    deleteRematVictims();
1038
1039  // Get rid of unused values and set phi-kill flags.
1040  for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
1041    (*I)->RenumberValues(LIS);
1042
1043  // Provide a reverse mapping from original indices to Edit ranges.
1044  if (LRMap) {
1045    LRMap->clear();
1046    for (unsigned i = 0, e = Edit->size(); i != e; ++i)
1047      LRMap->push_back(i);
1048  }
1049
1050  // Now check if any registers were separated into multiple components.
1051  ConnectedVNInfoEqClasses ConEQ(LIS);
1052  for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
1053    // Don't use iterators, they are invalidated by create() below.
1054    LiveInterval *li = Edit->get(i);
1055    unsigned NumComp = ConEQ.Classify(li);
1056    if (NumComp <= 1)
1057      continue;
1058    DEBUG(dbgs() << "  " << NumComp << " components: " << *li << '\n');
1059    SmallVector<LiveInterval*, 8> dups;
1060    dups.push_back(li);
1061    for (unsigned j = 1; j != NumComp; ++j)
1062      dups.push_back(&Edit->create(LIS, VRM));
1063    ConEQ.Distribute(&dups[0], MRI);
1064    // The new intervals all map back to i.
1065    if (LRMap)
1066      LRMap->resize(Edit->size(), i);
1067  }
1068
1069  // Calculate spill weight and allocation hints for new intervals.
1070  Edit->calculateRegClassAndHint(VRM.getMachineFunction(), LIS, SA.Loops);
1071
1072  assert(!LRMap || LRMap->size() == Edit->size());
1073}
1074
1075
1076//===----------------------------------------------------------------------===//
1077//                            Single Block Splitting
1078//===----------------------------------------------------------------------===//
1079
1080/// getMultiUseBlocks - if CurLI has more than one use in a basic block, it
1081/// may be an advantage to split CurLI for the duration of the block.
1082bool SplitAnalysis::getMultiUseBlocks(BlockPtrSet &Blocks) {
1083  // If CurLI is local to one block, there is no point to splitting it.
1084  if (UseBlocks.size() <= 1)
1085    return false;
1086  // Add blocks with multiple uses.
1087  for (unsigned i = 0, e = UseBlocks.size(); i != e; ++i) {
1088    const BlockInfo &BI = UseBlocks[i];
1089    if (BI.FirstUse == BI.LastUse)
1090      continue;
1091    Blocks.insert(BI.MBB);
1092  }
1093  return !Blocks.empty();
1094}
1095
1096void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
1097  openIntv();
1098  SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
1099  SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstUse,
1100    LastSplitPoint));
1101  if (!BI.LiveOut || BI.LastUse < LastSplitPoint) {
1102    useIntv(SegStart, leaveIntvAfter(BI.LastUse));
1103  } else {
1104      // The last use is after the last valid split point.
1105    SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
1106    useIntv(SegStart, SegStop);
1107    overlapIntv(SegStop, BI.LastUse);
1108  }
1109}
1110
1111/// splitSingleBlocks - Split CurLI into a separate live interval inside each
1112/// basic block in Blocks.
1113void SplitEditor::splitSingleBlocks(const SplitAnalysis::BlockPtrSet &Blocks) {
1114  DEBUG(dbgs() << "  splitSingleBlocks for " << Blocks.size() << " blocks.\n");
1115  ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA.getUseBlocks();
1116  for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1117    const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1118    if (Blocks.count(BI.MBB))
1119      splitSingleBlock(BI);
1120  }
1121  finish();
1122}
1123
1124
1125//===----------------------------------------------------------------------===//
1126//                    Global Live Range Splitting Support
1127//===----------------------------------------------------------------------===//
1128
1129// These methods support a method of global live range splitting that uses a
1130// global algorithm to decide intervals for CFG edges. They will insert split
1131// points and color intervals in basic blocks while avoiding interference.
1132//
1133// Note that splitSingleBlock is also useful for blocks where both CFG edges
1134// are on the stack.
1135
1136void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
1137                                        unsigned IntvIn, SlotIndex LeaveBefore,
1138                                        unsigned IntvOut, SlotIndex EnterAfter){
1139  SlotIndex Start, Stop;
1140  tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
1141
1142  DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
1143               << ") intf " << LeaveBefore << '-' << EnterAfter
1144               << ", live-through " << IntvIn << " -> " << IntvOut);
1145
1146  assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
1147
1148  assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
1149  assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
1150  assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
1151
1152  MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
1153
1154  if (!IntvOut) {
1155    DEBUG(dbgs() << ", spill on entry.\n");
1156    //
1157    //        <<<<<<<<<    Possible LeaveBefore interference.
1158    //    |-----------|    Live through.
1159    //    -____________    Spill on entry.
1160    //
1161    selectIntv(IntvIn);
1162    SlotIndex Idx = leaveIntvAtTop(*MBB);
1163    assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1164    (void)Idx;
1165    return;
1166  }
1167
1168  if (!IntvIn) {
1169    DEBUG(dbgs() << ", reload on exit.\n");
1170    //
1171    //    >>>>>>>          Possible EnterAfter interference.
1172    //    |-----------|    Live through.
1173    //    ___________--    Reload on exit.
1174    //
1175    selectIntv(IntvOut);
1176    SlotIndex Idx = enterIntvAtEnd(*MBB);
1177    assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1178    (void)Idx;
1179    return;
1180  }
1181
1182  if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1183    DEBUG(dbgs() << ", straight through.\n");
1184    //
1185    //    |-----------|    Live through.
1186    //    -------------    Straight through, same intv, no interference.
1187    //
1188    selectIntv(IntvOut);
1189    useIntv(Start, Stop);
1190    return;
1191  }
1192
1193  // We cannot legally insert splits after LSP.
1194  SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
1195  assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
1196
1197  if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1198                  LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
1199    DEBUG(dbgs() << ", switch avoiding interference.\n");
1200    //
1201    //    >>>>     <<<<    Non-overlapping EnterAfter/LeaveBefore interference.
1202    //    |-----------|    Live through.
1203    //    ------=======    Switch intervals between interference.
1204    //
1205    selectIntv(IntvOut);
1206    SlotIndex Idx;
1207    if (LeaveBefore && LeaveBefore < LSP) {
1208      Idx = enterIntvBefore(LeaveBefore);
1209      useIntv(Idx, Stop);
1210    } else {
1211      Idx = enterIntvAtEnd(*MBB);
1212    }
1213    selectIntv(IntvIn);
1214    useIntv(Start, Idx);
1215    assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1216    assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1217    return;
1218  }
1219
1220  DEBUG(dbgs() << ", create local intv for interference.\n");
1221  //
1222  //    >>><><><><<<<    Overlapping EnterAfter/LeaveBefore interference.
1223  //    |-----------|    Live through.
1224  //    ==---------==    Switch intervals before/after interference.
1225  //
1226  assert(LeaveBefore <= EnterAfter && "Missed case");
1227
1228  selectIntv(IntvOut);
1229  SlotIndex Idx = enterIntvAfter(EnterAfter);
1230  useIntv(Idx, Stop);
1231  assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1232
1233  selectIntv(IntvIn);
1234  Idx = leaveIntvBefore(LeaveBefore);
1235  useIntv(Start, Idx);
1236  assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1237}
1238
1239
1240void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1241                                  unsigned IntvIn, SlotIndex LeaveBefore) {
1242  SlotIndex Start, Stop;
1243  tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1244
1245  DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1246               << "), uses " << BI.FirstUse << '-' << BI.LastUse
1247               << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1248               << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1249
1250  assert(IntvIn && "Must have register in");
1251  assert(BI.LiveIn && "Must be live-in");
1252  assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1253
1254  if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastUse)) {
1255    DEBUG(dbgs() << " before interference.\n");
1256    //
1257    //               <<<    Interference after kill.
1258    //     |---o---x   |    Killed in block.
1259    //     =========        Use IntvIn everywhere.
1260    //
1261    selectIntv(IntvIn);
1262    useIntv(Start, BI.LastUse);
1263    return;
1264  }
1265
1266  SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1267
1268  if (!LeaveBefore || LeaveBefore > BI.LastUse.getBoundaryIndex()) {
1269    //
1270    //               <<<    Possible interference after last use.
1271    //     |---o---o---|    Live-out on stack.
1272    //     =========____    Leave IntvIn after last use.
1273    //
1274    //                 <    Interference after last use.
1275    //     |---o---o--o|    Live-out on stack, late last use.
1276    //     ============     Copy to stack after LSP, overlap IntvIn.
1277    //            \_____    Stack interval is live-out.
1278    //
1279    if (BI.LastUse < LSP) {
1280      DEBUG(dbgs() << ", spill after last use before interference.\n");
1281      selectIntv(IntvIn);
1282      SlotIndex Idx = leaveIntvAfter(BI.LastUse);
1283      useIntv(Start, Idx);
1284      assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1285    } else {
1286      DEBUG(dbgs() << ", spill before last split point.\n");
1287      selectIntv(IntvIn);
1288      SlotIndex Idx = leaveIntvBefore(LSP);
1289      overlapIntv(Idx, BI.LastUse);
1290      useIntv(Start, Idx);
1291      assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1292    }
1293    return;
1294  }
1295
1296  // The interference is overlapping somewhere we wanted to use IntvIn. That
1297  // means we need to create a local interval that can be allocated a
1298  // different register.
1299  unsigned LocalIntv = openIntv();
1300  (void)LocalIntv;
1301  DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1302
1303  if (!BI.LiveOut || BI.LastUse < LSP) {
1304    //
1305    //           <<<<<<<    Interference overlapping uses.
1306    //     |---o---o---|    Live-out on stack.
1307    //     =====----____    Leave IntvIn before interference, then spill.
1308    //
1309    SlotIndex To = leaveIntvAfter(BI.LastUse);
1310    SlotIndex From = enterIntvBefore(LeaveBefore);
1311    useIntv(From, To);
1312    selectIntv(IntvIn);
1313    useIntv(Start, From);
1314    assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1315    return;
1316  }
1317
1318  //           <<<<<<<    Interference overlapping uses.
1319  //     |---o---o--o|    Live-out on stack, late last use.
1320  //     =====-------     Copy to stack before LSP, overlap LocalIntv.
1321  //            \_____    Stack interval is live-out.
1322  //
1323  SlotIndex To = leaveIntvBefore(LSP);
1324  overlapIntv(To, BI.LastUse);
1325  SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1326  useIntv(From, To);
1327  selectIntv(IntvIn);
1328  useIntv(Start, From);
1329  assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1330}
1331
1332void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1333                                   unsigned IntvOut, SlotIndex EnterAfter) {
1334  SlotIndex Start, Stop;
1335  tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1336
1337  DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1338               << "), uses " << BI.FirstUse << '-' << BI.LastUse
1339               << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1340               << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1341
1342  SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1343
1344  assert(IntvOut && "Must have register out");
1345  assert(BI.LiveOut && "Must be live-out");
1346  assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1347
1348  if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstUse)) {
1349    DEBUG(dbgs() << " after interference.\n");
1350    //
1351    //    >>>>             Interference before def.
1352    //    |   o---o---|    Defined in block.
1353    //        =========    Use IntvOut everywhere.
1354    //
1355    selectIntv(IntvOut);
1356    useIntv(BI.FirstUse, Stop);
1357    return;
1358  }
1359
1360  if (!EnterAfter || EnterAfter < BI.FirstUse.getBaseIndex()) {
1361    DEBUG(dbgs() << ", reload after interference.\n");
1362    //
1363    //    >>>>             Interference before def.
1364    //    |---o---o---|    Live-through, stack-in.
1365    //    ____=========    Enter IntvOut before first use.
1366    //
1367    selectIntv(IntvOut);
1368    SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstUse));
1369    useIntv(Idx, Stop);
1370    assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1371    return;
1372  }
1373
1374  // The interference is overlapping somewhere we wanted to use IntvOut. That
1375  // means we need to create a local interval that can be allocated a
1376  // different register.
1377  DEBUG(dbgs() << ", interference overlaps uses.\n");
1378  //
1379  //    >>>>>>>          Interference overlapping uses.
1380  //    |---o---o---|    Live-through, stack-in.
1381  //    ____---======    Create local interval for interference range.
1382  //
1383  selectIntv(IntvOut);
1384  SlotIndex Idx = enterIntvAfter(EnterAfter);
1385  useIntv(Idx, Stop);
1386  assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1387
1388  openIntv();
1389  SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstUse));
1390  useIntv(From, Idx);
1391}
1392