SplitKit.cpp revision e5a2e366322ef5f0d597b1fb8dbf55f2cf36cf15 
1//===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SplitAnalysis class as well as mutator functions for
11// live range splitting.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "regalloc"
16#include "SplitKit.h"
17#include "LiveRangeEdit.h"
18#include "VirtRegMap.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/CodeGen/LiveIntervalAnalysis.h"
21#include "llvm/CodeGen/MachineDominators.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/raw_ostream.h"
26#include "llvm/Target/TargetInstrInfo.h"
27#include "llvm/Target/TargetMachine.h"
28
29using namespace llvm;
30
31STATISTIC(NumFinished, "Number of splits finished");
32STATISTIC(NumSimple,   "Number of splits that were simple");
33STATISTIC(NumCopies,   "Number of copies inserted for splitting");
34STATISTIC(NumRemats,   "Number of rematerialized defs for splitting");
35STATISTIC(NumRepairs,  "Number of invalid live ranges repaired");
36
37//===----------------------------------------------------------------------===//
38//                                 Split Analysis
39//===----------------------------------------------------------------------===//
40
41SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
42                             const LiveIntervals &lis,
43                             const MachineLoopInfo &mli)
44  : MF(vrm.getMachineFunction()),
45    VRM(vrm),
46    LIS(lis),
47    Loops(mli),
48    TII(*MF.getTarget().getInstrInfo()),
49    CurLI(0),
50    LastSplitPoint(MF.getNumBlockIDs()) {}
51
52void SplitAnalysis::clear() {
53  UseSlots.clear();
54  UseBlocks.clear();
55  ThroughBlocks.clear();
56  CurLI = 0;
57  DidRepairRange = false;
58}
59
60SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
61  const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
62  const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
63  std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
64
65  // Compute split points on the first call. The pair is independent of the
66  // current live interval.
67  if (!LSP.first.isValid()) {
68    MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
69    if (FirstTerm == MBB->end())
70      LSP.first = LIS.getMBBEndIdx(MBB);
71    else
72      LSP.first = LIS.getInstructionIndex(FirstTerm);
73
74    // If there is a landing pad successor, also find the call instruction.
75    if (!LPad)
76      return LSP.first;
77    // There may not be a call instruction (?) in which case we ignore LPad.
78    LSP.second = LSP.first;
79    for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
80         I != E;) {
81      --I;
82      if (I->getDesc().isCall()) {
83        LSP.second = LIS.getInstructionIndex(I);
84        break;
85      }
86    }
87  }
88
89  // If CurLI is live into a landing pad successor, move the last split point
90  // back to the call that may throw.
91  if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
92    return LSP.second;
93  else
94    return LSP.first;
95}
96
97/// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
98void SplitAnalysis::analyzeUses() {
99  assert(UseSlots.empty() && "Call clear first");
100
101  // First get all the defs from the interval values. This provides the correct
102  // slots for early clobbers.
103  for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
104       E = CurLI->vni_end(); I != E; ++I)
105    if (!(*I)->isPHIDef() && !(*I)->isUnused())
106      UseSlots.push_back((*I)->def);
107
108  // Get use slots form the use-def chain.
109  const MachineRegisterInfo &MRI = MF.getRegInfo();
110  for (MachineRegisterInfo::use_nodbg_iterator
111       I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
112       ++I)
113    if (!I.getOperand().isUndef())
114      UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
115
116  array_pod_sort(UseSlots.begin(), UseSlots.end());
117
118  // Remove duplicates, keeping the smaller slot for each instruction.
119  // That is what we want for early clobbers.
120  UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
121                             SlotIndex::isSameInstr),
122                 UseSlots.end());
123
124  // Compute per-live block info.
125  if (!calcLiveBlockInfo()) {
126    // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
127    // I am looking at you, RegisterCoalescer!
128    DidRepairRange = true;
129    ++NumRepairs;
130    DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
131    const_cast<LiveIntervals&>(LIS)
132      .shrinkToUses(const_cast<LiveInterval*>(CurLI));
133    UseBlocks.clear();
134    ThroughBlocks.clear();
135    bool fixed = calcLiveBlockInfo();
136    (void)fixed;
137    assert(fixed && "Couldn't fix broken live interval");
138  }
139
140  DEBUG(dbgs() << "Analyze counted "
141               << UseSlots.size() << " instrs in "
142               << UseBlocks.size() << " blocks, through "
143               << NumThroughBlocks << " blocks.\n");
144}
145
146/// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
147/// where CurLI is live.
148bool SplitAnalysis::calcLiveBlockInfo() {
149  ThroughBlocks.resize(MF.getNumBlockIDs());
150  NumThroughBlocks = NumGapBlocks = 0;
151  if (CurLI->empty())
152    return true;
153
154  LiveInterval::const_iterator LVI = CurLI->begin();
155  LiveInterval::const_iterator LVE = CurLI->end();
156
157  SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
158  UseI = UseSlots.begin();
159  UseE = UseSlots.end();
160
161  // Loop over basic blocks where CurLI is live.
162  MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
163  for (;;) {
164    BlockInfo BI;
165    BI.MBB = MFI;
166    SlotIndex Start, Stop;
167    tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
168
169    // If the block contains no uses, the range must be live through. At one
170    // point, RegisterCoalescer could create dangling ranges that ended
171    // mid-block.
172    if (UseI == UseE || *UseI >= Stop) {
173      ++NumThroughBlocks;
174      ThroughBlocks.set(BI.MBB->getNumber());
175      // The range shouldn't end mid-block if there are no uses. This shouldn't
176      // happen.
177      if (LVI->end < Stop)
178        return false;
179    } else {
180      // This block has uses. Find the first and last uses in the block.
181      BI.FirstInstr = *UseI;
182      assert(BI.FirstInstr >= Start);
183      do ++UseI;
184      while (UseI != UseE && *UseI < Stop);
185      BI.LastInstr = UseI[-1];
186      assert(BI.LastInstr < Stop);
187
188      // LVI is the first live segment overlapping MBB.
189      BI.LiveIn = LVI->start <= Start;
190
191      // When not live in, the first use should be a def.
192      if (!BI.LiveIn) {
193        assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
194        assert(LVI->start == BI.FirstInstr && "First instr should be a def");
195        BI.FirstDef = BI.FirstInstr;
196      }
197
198      // Look for gaps in the live range.
199      BI.LiveOut = true;
200      while (LVI->end < Stop) {
201        SlotIndex LastStop = LVI->end;
202        if (++LVI == LVE || LVI->start >= Stop) {
203          BI.LiveOut = false;
204          BI.LastInstr = LastStop;
205          break;
206        }
207
208        if (LastStop < LVI->start) {
209          // There is a gap in the live range. Create duplicate entries for the
210          // live-in snippet and the live-out snippet.
211          ++NumGapBlocks;
212
213          // Push the Live-in part.
214          BI.LiveOut = false;
215          UseBlocks.push_back(BI);
216          UseBlocks.back().LastInstr = LastStop;
217
218          // Set up BI for the live-out part.
219          BI.LiveIn = false;
220          BI.LiveOut = true;
221          BI.FirstInstr = BI.FirstDef = LVI->start;
222        }
223
224        // A LiveRange that starts in the middle of the block must be a def.
225        assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
226        if (!BI.FirstDef)
227          BI.FirstDef = LVI->start;
228      }
229
230      UseBlocks.push_back(BI);
231
232      // LVI is now at LVE or LVI->end >= Stop.
233      if (LVI == LVE)
234        break;
235    }
236
237    // Live segment ends exactly at Stop. Move to the next segment.
238    if (LVI->end == Stop && ++LVI == LVE)
239      break;
240
241    // Pick the next basic block.
242    if (LVI->start < Stop)
243      ++MFI;
244    else
245      MFI = LIS.getMBBFromIndex(LVI->start);
246  }
247
248  assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
249  return true;
250}
251
252unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
253  if (cli->empty())
254    return 0;
255  LiveInterval *li = const_cast<LiveInterval*>(cli);
256  LiveInterval::iterator LVI = li->begin();
257  LiveInterval::iterator LVE = li->end();
258  unsigned Count = 0;
259
260  // Loop over basic blocks where li is live.
261  MachineFunction::const_iterator MFI = LIS.getMBBFromIndex(LVI->start);
262  SlotIndex Stop = LIS.getMBBEndIdx(MFI);
263  for (;;) {
264    ++Count;
265    LVI = li->advanceTo(LVI, Stop);
266    if (LVI == LVE)
267      return Count;
268    do {
269      ++MFI;
270      Stop = LIS.getMBBEndIdx(MFI);
271    } while (Stop <= LVI->start);
272  }
273}
274
275bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
276  unsigned OrigReg = VRM.getOriginal(CurLI->reg);
277  const LiveInterval &Orig = LIS.getInterval(OrigReg);
278  assert(!Orig.empty() && "Splitting empty interval?");
279  LiveInterval::const_iterator I = Orig.find(Idx);
280
281  // Range containing Idx should begin at Idx.
282  if (I != Orig.end() && I->start <= Idx)
283    return I->start == Idx;
284
285  // Range does not contain Idx, previous must end at Idx.
286  return I != Orig.begin() && (--I)->end == Idx;
287}
288
289void SplitAnalysis::analyze(const LiveInterval *li) {
290  clear();
291  CurLI = li;
292  analyzeUses();
293}
294
295
296//===----------------------------------------------------------------------===//
297//                               Split Editor
298//===----------------------------------------------------------------------===//
299
300/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
301SplitEditor::SplitEditor(SplitAnalysis &sa,
302                         LiveIntervals &lis,
303                         VirtRegMap &vrm,
304                         MachineDominatorTree &mdt)
305  : SA(sa), LIS(lis), VRM(vrm),
306    MRI(vrm.getMachineFunction().getRegInfo()),
307    MDT(mdt),
308    TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
309    TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
310    Edit(0),
311    OpenIdx(0),
312    SpillMode(SM_Partition),
313    RegAssign(Allocator)
314{}
315
316void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
317  Edit = &LRE;
318  SpillMode = SM;
319  OpenIdx = 0;
320  OverlappedComplement.clear();
321  RegAssign.clear();
322  Values.clear();
323
324  // Reset the LiveRangeCalc instances needed for this spill mode.
325  LRCalc[0].reset(&VRM.getMachineFunction());
326  if (SpillMode)
327    LRCalc[1].reset(&VRM.getMachineFunction());
328
329  // We don't need an AliasAnalysis since we will only be performing
330  // cheap-as-a-copy remats anyway.
331  Edit->anyRematerializable(LIS, TII, 0);
332}
333
334void SplitEditor::dump() const {
335  if (RegAssign.empty()) {
336    dbgs() << " empty\n";
337    return;
338  }
339
340  for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
341    dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
342  dbgs() << '\n';
343}
344
345VNInfo *SplitEditor::defValue(unsigned RegIdx,
346                              const VNInfo *ParentVNI,
347                              SlotIndex Idx) {
348  assert(ParentVNI && "Mapping  NULL value");
349  assert(Idx.isValid() && "Invalid SlotIndex");
350  assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
351  LiveInterval *LI = Edit->get(RegIdx);
352
353  // Create a new value.
354  VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
355
356  // Use insert for lookup, so we can add missing values with a second lookup.
357  std::pair<ValueMap::iterator, bool> InsP =
358    Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
359
360  // This was the first time (RegIdx, ParentVNI) was mapped.
361  // Keep it as a simple def without any liveness.
362  if (InsP.second)
363    return VNI;
364
365  // If the previous value was a simple mapping, add liveness for it now.
366  if (VNInfo *OldVNI = InsP.first->second) {
367    SlotIndex Def = OldVNI->def;
368    LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
369    // No longer a simple mapping.
370    InsP.first->second = 0;
371  }
372
373  // This is a complex mapping, add liveness for VNI
374  SlotIndex Def = VNI->def;
375  LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
376
377  return VNI;
378}
379
380void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
381  assert(ParentVNI && "Mapping  NULL value");
382  VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
383
384  // ParentVNI was either unmapped or already complex mapped. Either way.
385  if (!VNI)
386    return;
387
388  // This was previously a single mapping. Make sure the old def is represented
389  // by a trivial live range.
390  SlotIndex Def = VNI->def;
391  Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
392  VNI = 0;
393}
394
395void SplitEditor::markOverlappedComplement(const VNInfo *ParentVNI) {
396  if (OverlappedComplement.insert(ParentVNI))
397    markComplexMapped(0, ParentVNI);
398}
399
400bool SplitEditor::needsRecompute(unsigned RegIdx, const VNInfo *ParentVNI) {
401  return (RegIdx == 0 && OverlappedComplement.count(ParentVNI)) ||
402    Edit->didRematerialize(ParentVNI);
403}
404
405VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
406                                   VNInfo *ParentVNI,
407                                   SlotIndex UseIdx,
408                                   MachineBasicBlock &MBB,
409                                   MachineBasicBlock::iterator I) {
410  MachineInstr *CopyMI = 0;
411  SlotIndex Def;
412  LiveInterval *LI = Edit->get(RegIdx);
413
414  // We may be trying to avoid interference that ends at a deleted instruction,
415  // so always begin RegIdx 0 early and all others late.
416  bool Late = RegIdx != 0;
417
418  // Attempt cheap-as-a-copy rematerialization.
419  LiveRangeEdit::Remat RM(ParentVNI);
420  if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
421    Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI, Late);
422    ++NumRemats;
423  } else {
424    // Can't remat, just insert a copy from parent.
425    CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
426               .addReg(Edit->getReg());
427    Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
428            .getDefIndex();
429    ++NumCopies;
430  }
431
432  // Define the value in Reg.
433  VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
434  VNI->setCopy(CopyMI);
435  return VNI;
436}
437
438/// Create a new virtual register and live interval.
439unsigned SplitEditor::openIntv() {
440  // Create the complement as index 0.
441  if (Edit->empty())
442    Edit->create(LIS, VRM);
443
444  // Create the open interval.
445  OpenIdx = Edit->size();
446  Edit->create(LIS, VRM);
447  return OpenIdx;
448}
449
450void SplitEditor::selectIntv(unsigned Idx) {
451  assert(Idx != 0 && "Cannot select the complement interval");
452  assert(Idx < Edit->size() && "Can only select previously opened interval");
453  DEBUG(dbgs() << "    selectIntv " << OpenIdx << " -> " << Idx << '\n');
454  OpenIdx = Idx;
455}
456
457SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
458  assert(OpenIdx && "openIntv not called before enterIntvBefore");
459  DEBUG(dbgs() << "    enterIntvBefore " << Idx);
460  Idx = Idx.getBaseIndex();
461  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
462  if (!ParentVNI) {
463    DEBUG(dbgs() << ": not live\n");
464    return Idx;
465  }
466  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
467  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
468  assert(MI && "enterIntvBefore called with invalid index");
469
470  VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
471  return VNI->def;
472}
473
474SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
475  assert(OpenIdx && "openIntv not called before enterIntvAfter");
476  DEBUG(dbgs() << "    enterIntvAfter " << Idx);
477  Idx = Idx.getBoundaryIndex();
478  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
479  if (!ParentVNI) {
480    DEBUG(dbgs() << ": not live\n");
481    return Idx;
482  }
483  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
484  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
485  assert(MI && "enterIntvAfter called with invalid index");
486
487  VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
488                              llvm::next(MachineBasicBlock::iterator(MI)));
489  return VNI->def;
490}
491
492SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
493  assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
494  SlotIndex End = LIS.getMBBEndIdx(&MBB);
495  SlotIndex Last = End.getPrevSlot();
496  DEBUG(dbgs() << "    enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
497  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
498  if (!ParentVNI) {
499    DEBUG(dbgs() << ": not live\n");
500    return End;
501  }
502  DEBUG(dbgs() << ": valno " << ParentVNI->id);
503  VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
504                              LIS.getLastSplitPoint(Edit->getParent(), &MBB));
505  RegAssign.insert(VNI->def, End, OpenIdx);
506  DEBUG(dump());
507  return VNI->def;
508}
509
510/// useIntv - indicate that all instructions in MBB should use OpenLI.
511void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
512  useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
513}
514
515void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
516  assert(OpenIdx && "openIntv not called before useIntv");
517  DEBUG(dbgs() << "    useIntv [" << Start << ';' << End << "):");
518  RegAssign.insert(Start, End, OpenIdx);
519  DEBUG(dump());
520}
521
522SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
523  assert(OpenIdx && "openIntv not called before leaveIntvAfter");
524  DEBUG(dbgs() << "    leaveIntvAfter " << Idx);
525
526  // The interval must be live beyond the instruction at Idx.
527  Idx = Idx.getBoundaryIndex();
528  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
529  if (!ParentVNI) {
530    DEBUG(dbgs() << ": not live\n");
531    return Idx.getNextSlot();
532  }
533  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
534
535  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
536  assert(MI && "No instruction at index");
537  VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
538                              llvm::next(MachineBasicBlock::iterator(MI)));
539  return VNI->def;
540}
541
542SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
543  assert(OpenIdx && "openIntv not called before leaveIntvBefore");
544  DEBUG(dbgs() << "    leaveIntvBefore " << Idx);
545
546  // The interval must be live into the instruction at Idx.
547  Idx = Idx.getBaseIndex();
548  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
549  if (!ParentVNI) {
550    DEBUG(dbgs() << ": not live\n");
551    return Idx.getNextSlot();
552  }
553  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
554
555  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
556  assert(MI && "No instruction at index");
557  VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
558  return VNI->def;
559}
560
561SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
562  assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
563  SlotIndex Start = LIS.getMBBStartIdx(&MBB);
564  DEBUG(dbgs() << "    leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
565
566  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
567  if (!ParentVNI) {
568    DEBUG(dbgs() << ": not live\n");
569    return Start;
570  }
571
572  VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
573                              MBB.SkipPHIsAndLabels(MBB.begin()));
574  RegAssign.insert(Start, VNI->def, OpenIdx);
575  DEBUG(dump());
576  return VNI->def;
577}
578
579void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
580  assert(OpenIdx && "openIntv not called before overlapIntv");
581  const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
582  assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
583         "Parent changes value in extended range");
584  assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
585         "Range cannot span basic blocks");
586
587  // The complement interval will be extended as needed by LRCalc.extend().
588  if (ParentVNI)
589    markOverlappedComplement(ParentVNI);
590  DEBUG(dbgs() << "    overlapIntv [" << Start << ';' << End << "):");
591  RegAssign.insert(Start, End, OpenIdx);
592  DEBUG(dump());
593}
594
595/// transferValues - Transfer all possible values to the new live ranges.
596/// Values that were rematerialized are left alone, they need LRCalc.extend().
597bool SplitEditor::transferValues() {
598  bool Skipped = false;
599  RegAssignMap::const_iterator AssignI = RegAssign.begin();
600  for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
601         ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
602    DEBUG(dbgs() << "  blit " << *ParentI << ':');
603    VNInfo *ParentVNI = ParentI->valno;
604    // RegAssign has holes where RegIdx 0 should be used.
605    SlotIndex Start = ParentI->start;
606    AssignI.advanceTo(Start);
607    do {
608      unsigned RegIdx;
609      SlotIndex End = ParentI->end;
610      if (!AssignI.valid()) {
611        RegIdx = 0;
612      } else if (AssignI.start() <= Start) {
613        RegIdx = AssignI.value();
614        if (AssignI.stop() < End) {
615          End = AssignI.stop();
616          ++AssignI;
617        }
618      } else {
619        RegIdx = 0;
620        End = std::min(End, AssignI.start());
621      }
622
623      // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
624      DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
625      LiveInterval *LI = Edit->get(RegIdx);
626
627      // Check for a simply defined value that can be blitted directly.
628      if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
629        DEBUG(dbgs() << ':' << VNI->id);
630        LI->addRange(LiveRange(Start, End, VNI));
631        Start = End;
632        continue;
633      }
634
635      // Skip rematerialized values, we need to use LRCalc.extend() and
636      // extendPHIKillRanges() to completely recompute the live ranges.
637      if (needsRecompute(RegIdx, ParentVNI)) {
638        DEBUG(dbgs() << "(remat)");
639        Skipped = true;
640        Start = End;
641        continue;
642      }
643
644      LiveRangeCalc &LRC = getLRCalc(RegIdx);
645
646      // This value has multiple defs in RegIdx, but it wasn't rematerialized,
647      // so the live range is accurate. Add live-in blocks in [Start;End) to the
648      // LiveInBlocks.
649      MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
650      SlotIndex BlockStart, BlockEnd;
651      tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB);
652
653      // The first block may be live-in, or it may have its own def.
654      if (Start != BlockStart) {
655        VNInfo *VNI = LI->extendInBlock(BlockStart, std::min(BlockEnd, End));
656        assert(VNI && "Missing def for complex mapped value");
657        DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
658        // MBB has its own def. Is it also live-out?
659        if (BlockEnd <= End)
660          LRC.setLiveOutValue(MBB, VNI);
661
662        // Skip to the next block for live-in.
663        ++MBB;
664        BlockStart = BlockEnd;
665      }
666
667      // Handle the live-in blocks covered by [Start;End).
668      assert(Start <= BlockStart && "Expected live-in block");
669      while (BlockStart < End) {
670        DEBUG(dbgs() << ">BB#" << MBB->getNumber());
671        BlockEnd = LIS.getMBBEndIdx(MBB);
672        if (BlockStart == ParentVNI->def) {
673          // This block has the def of a parent PHI, so it isn't live-in.
674          assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
675          VNInfo *VNI = LI->extendInBlock(BlockStart, std::min(BlockEnd, End));
676          assert(VNI && "Missing def for complex mapped parent PHI");
677          if (End >= BlockEnd)
678            LRC.setLiveOutValue(MBB, VNI); // Live-out as well.
679        } else {
680          // This block needs a live-in value.  The last block covered may not
681          // be live-out.
682          if (End < BlockEnd)
683            LRC.addLiveInBlock(LI, MDT[MBB], End);
684          else {
685            // Live-through, and we don't know the value.
686            LRC.addLiveInBlock(LI, MDT[MBB]);
687            LRC.setLiveOutValue(MBB, 0);
688          }
689        }
690        BlockStart = BlockEnd;
691        ++MBB;
692      }
693      Start = End;
694    } while (Start != ParentI->end);
695    DEBUG(dbgs() << '\n');
696  }
697
698  LRCalc[0].calculateValues(LIS.getSlotIndexes(), &MDT,
699                            &LIS.getVNInfoAllocator());
700  if (SpillMode)
701    LRCalc[1].calculateValues(LIS.getSlotIndexes(), &MDT,
702                              &LIS.getVNInfoAllocator());
703
704  return Skipped;
705}
706
707void SplitEditor::extendPHIKillRanges() {
708    // Extend live ranges to be live-out for successor PHI values.
709  for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
710       E = Edit->getParent().vni_end(); I != E; ++I) {
711    const VNInfo *PHIVNI = *I;
712    if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
713      continue;
714    unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
715    LiveInterval *LI = Edit->get(RegIdx);
716    LiveRangeCalc &LRC = getLRCalc(RegIdx);
717    MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
718    for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
719         PE = MBB->pred_end(); PI != PE; ++PI) {
720      SlotIndex End = LIS.getMBBEndIdx(*PI);
721      SlotIndex LastUse = End.getPrevSlot();
722      // The predecessor may not have a live-out value. That is OK, like an
723      // undef PHI operand.
724      if (Edit->getParent().liveAt(LastUse)) {
725        assert(RegAssign.lookup(LastUse) == RegIdx &&
726               "Different register assignment in phi predecessor");
727        LRC.extend(LI, End,
728                   LIS.getSlotIndexes(), &MDT, &LIS.getVNInfoAllocator());
729      }
730    }
731  }
732}
733
734/// rewriteAssigned - Rewrite all uses of Edit->getReg().
735void SplitEditor::rewriteAssigned(bool ExtendRanges) {
736  for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
737       RE = MRI.reg_end(); RI != RE;) {
738    MachineOperand &MO = RI.getOperand();
739    MachineInstr *MI = MO.getParent();
740    ++RI;
741    // LiveDebugVariables should have handled all DBG_VALUE instructions.
742    if (MI->isDebugValue()) {
743      DEBUG(dbgs() << "Zapping " << *MI);
744      MO.setReg(0);
745      continue;
746    }
747
748    // <undef> operands don't really read the register, so it doesn't matter
749    // which register we choose.  When the use operand is tied to a def, we must
750    // use the same register as the def, so just do that always.
751    SlotIndex Idx = LIS.getInstructionIndex(MI);
752    if (MO.isDef() || MO.isUndef())
753      Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex();
754
755    // Rewrite to the mapped register at Idx.
756    unsigned RegIdx = RegAssign.lookup(Idx);
757    LiveInterval *LI = Edit->get(RegIdx);
758    MO.setReg(LI->reg);
759    DEBUG(dbgs() << "  rewr BB#" << MI->getParent()->getNumber() << '\t'
760                 << Idx << ':' << RegIdx << '\t' << *MI);
761
762    // Extend liveness to Idx if the instruction reads reg.
763    if (!ExtendRanges || MO.isUndef())
764      continue;
765
766    // Skip instructions that don't read Reg.
767    if (MO.isDef()) {
768      if (!MO.getSubReg() && !MO.isEarlyClobber())
769        continue;
770      // We may wan't to extend a live range for a partial redef, or for a use
771      // tied to an early clobber.
772      Idx = Idx.getPrevSlot();
773      if (!Edit->getParent().liveAt(Idx))
774        continue;
775    } else
776      Idx = Idx.getUseIndex();
777
778    getLRCalc(RegIdx).extend(LI, Idx.getNextSlot(), LIS.getSlotIndexes(),
779                             &MDT, &LIS.getVNInfoAllocator());
780  }
781}
782
783void SplitEditor::deleteRematVictims() {
784  SmallVector<MachineInstr*, 8> Dead;
785  for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
786    LiveInterval *LI = *I;
787    for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
788           LII != LIE; ++LII) {
789      // Dead defs end at the store slot.
790      if (LII->end != LII->valno->def.getNextSlot())
791        continue;
792      MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
793      assert(MI && "Missing instruction for dead def");
794      MI->addRegisterDead(LI->reg, &TRI);
795
796      if (!MI->allDefsAreDead())
797        continue;
798
799      DEBUG(dbgs() << "All defs dead: " << *MI);
800      Dead.push_back(MI);
801    }
802  }
803
804  if (Dead.empty())
805    return;
806
807  Edit->eliminateDeadDefs(Dead, LIS, VRM, TII);
808}
809
810void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
811  ++NumFinished;
812
813  // At this point, the live intervals in Edit contain VNInfos corresponding to
814  // the inserted copies.
815
816  // Add the original defs from the parent interval.
817  for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
818         E = Edit->getParent().vni_end(); I != E; ++I) {
819    const VNInfo *ParentVNI = *I;
820    if (ParentVNI->isUnused())
821      continue;
822    unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
823    VNInfo *VNI = defValue(RegIdx, ParentVNI, ParentVNI->def);
824    VNI->setIsPHIDef(ParentVNI->isPHIDef());
825    VNI->setCopy(ParentVNI->getCopy());
826
827    // Mark rematted values as complex everywhere to force liveness computation.
828    // The new live ranges may be truncated.
829    if (Edit->didRematerialize(ParentVNI))
830      for (unsigned i = 0, e = Edit->size(); i != e; ++i)
831        markComplexMapped(i, ParentVNI);
832  }
833
834  // Transfer the simply mapped values, check if any are skipped.
835  bool Skipped = transferValues();
836  if (Skipped)
837    extendPHIKillRanges();
838  else
839    ++NumSimple;
840
841  // Rewrite virtual registers, possibly extending ranges.
842  rewriteAssigned(Skipped);
843
844  // Delete defs that were rematted everywhere.
845  if (Skipped)
846    deleteRematVictims();
847
848  // Get rid of unused values and set phi-kill flags.
849  for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
850    (*I)->RenumberValues(LIS);
851
852  // Provide a reverse mapping from original indices to Edit ranges.
853  if (LRMap) {
854    LRMap->clear();
855    for (unsigned i = 0, e = Edit->size(); i != e; ++i)
856      LRMap->push_back(i);
857  }
858
859  // Now check if any registers were separated into multiple components.
860  ConnectedVNInfoEqClasses ConEQ(LIS);
861  for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
862    // Don't use iterators, they are invalidated by create() below.
863    LiveInterval *li = Edit->get(i);
864    unsigned NumComp = ConEQ.Classify(li);
865    if (NumComp <= 1)
866      continue;
867    DEBUG(dbgs() << "  " << NumComp << " components: " << *li << '\n');
868    SmallVector<LiveInterval*, 8> dups;
869    dups.push_back(li);
870    for (unsigned j = 1; j != NumComp; ++j)
871      dups.push_back(&Edit->create(LIS, VRM));
872    ConEQ.Distribute(&dups[0], MRI);
873    // The new intervals all map back to i.
874    if (LRMap)
875      LRMap->resize(Edit->size(), i);
876  }
877
878  // Calculate spill weight and allocation hints for new intervals.
879  Edit->calculateRegClassAndHint(VRM.getMachineFunction(), LIS, SA.Loops);
880
881  assert(!LRMap || LRMap->size() == Edit->size());
882}
883
884
885//===----------------------------------------------------------------------===//
886//                            Single Block Splitting
887//===----------------------------------------------------------------------===//
888
889bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
890                                           bool SingleInstrs) const {
891  // Always split for multiple instructions.
892  if (!BI.isOneInstr())
893    return true;
894  // Don't split for single instructions unless explicitly requested.
895  if (!SingleInstrs)
896    return false;
897  // Splitting a live-through range always makes progress.
898  if (BI.LiveIn && BI.LiveOut)
899    return true;
900  // No point in isolating a copy. It has no register class constraints.
901  if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike())
902    return false;
903  // Finally, don't isolate an end point that was created by earlier splits.
904  return isOriginalEndpoint(BI.FirstInstr);
905}
906
907void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
908  openIntv();
909  SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
910  SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstInstr,
911    LastSplitPoint));
912  if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
913    useIntv(SegStart, leaveIntvAfter(BI.LastInstr));
914  } else {
915      // The last use is after the last valid split point.
916    SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
917    useIntv(SegStart, SegStop);
918    overlapIntv(SegStop, BI.LastInstr);
919  }
920}
921
922
923//===----------------------------------------------------------------------===//
924//                    Global Live Range Splitting Support
925//===----------------------------------------------------------------------===//
926
927// These methods support a method of global live range splitting that uses a
928// global algorithm to decide intervals for CFG edges. They will insert split
929// points and color intervals in basic blocks while avoiding interference.
930//
931// Note that splitSingleBlock is also useful for blocks where both CFG edges
932// are on the stack.
933
934void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
935                                        unsigned IntvIn, SlotIndex LeaveBefore,
936                                        unsigned IntvOut, SlotIndex EnterAfter){
937  SlotIndex Start, Stop;
938  tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
939
940  DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
941               << ") intf " << LeaveBefore << '-' << EnterAfter
942               << ", live-through " << IntvIn << " -> " << IntvOut);
943
944  assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
945
946  assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
947  assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
948  assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
949
950  MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
951
952  if (!IntvOut) {
953    DEBUG(dbgs() << ", spill on entry.\n");
954    //
955    //        <<<<<<<<<    Possible LeaveBefore interference.
956    //    |-----------|    Live through.
957    //    -____________    Spill on entry.
958    //
959    selectIntv(IntvIn);
960    SlotIndex Idx = leaveIntvAtTop(*MBB);
961    assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
962    (void)Idx;
963    return;
964  }
965
966  if (!IntvIn) {
967    DEBUG(dbgs() << ", reload on exit.\n");
968    //
969    //    >>>>>>>          Possible EnterAfter interference.
970    //    |-----------|    Live through.
971    //    ___________--    Reload on exit.
972    //
973    selectIntv(IntvOut);
974    SlotIndex Idx = enterIntvAtEnd(*MBB);
975    assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
976    (void)Idx;
977    return;
978  }
979
980  if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
981    DEBUG(dbgs() << ", straight through.\n");
982    //
983    //    |-----------|    Live through.
984    //    -------------    Straight through, same intv, no interference.
985    //
986    selectIntv(IntvOut);
987    useIntv(Start, Stop);
988    return;
989  }
990
991  // We cannot legally insert splits after LSP.
992  SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
993  assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
994
995  if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
996                  LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
997    DEBUG(dbgs() << ", switch avoiding interference.\n");
998    //
999    //    >>>>     <<<<    Non-overlapping EnterAfter/LeaveBefore interference.
1000    //    |-----------|    Live through.
1001    //    ------=======    Switch intervals between interference.
1002    //
1003    selectIntv(IntvOut);
1004    SlotIndex Idx;
1005    if (LeaveBefore && LeaveBefore < LSP) {
1006      Idx = enterIntvBefore(LeaveBefore);
1007      useIntv(Idx, Stop);
1008    } else {
1009      Idx = enterIntvAtEnd(*MBB);
1010    }
1011    selectIntv(IntvIn);
1012    useIntv(Start, Idx);
1013    assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1014    assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1015    return;
1016  }
1017
1018  DEBUG(dbgs() << ", create local intv for interference.\n");
1019  //
1020  //    >>><><><><<<<    Overlapping EnterAfter/LeaveBefore interference.
1021  //    |-----------|    Live through.
1022  //    ==---------==    Switch intervals before/after interference.
1023  //
1024  assert(LeaveBefore <= EnterAfter && "Missed case");
1025
1026  selectIntv(IntvOut);
1027  SlotIndex Idx = enterIntvAfter(EnterAfter);
1028  useIntv(Idx, Stop);
1029  assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1030
1031  selectIntv(IntvIn);
1032  Idx = leaveIntvBefore(LeaveBefore);
1033  useIntv(Start, Idx);
1034  assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1035}
1036
1037
1038void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1039                                  unsigned IntvIn, SlotIndex LeaveBefore) {
1040  SlotIndex Start, Stop;
1041  tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1042
1043  DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1044               << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1045               << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1046               << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1047
1048  assert(IntvIn && "Must have register in");
1049  assert(BI.LiveIn && "Must be live-in");
1050  assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1051
1052  if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1053    DEBUG(dbgs() << " before interference.\n");
1054    //
1055    //               <<<    Interference after kill.
1056    //     |---o---x   |    Killed in block.
1057    //     =========        Use IntvIn everywhere.
1058    //
1059    selectIntv(IntvIn);
1060    useIntv(Start, BI.LastInstr);
1061    return;
1062  }
1063
1064  SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1065
1066  if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1067    //
1068    //               <<<    Possible interference after last use.
1069    //     |---o---o---|    Live-out on stack.
1070    //     =========____    Leave IntvIn after last use.
1071    //
1072    //                 <    Interference after last use.
1073    //     |---o---o--o|    Live-out on stack, late last use.
1074    //     ============     Copy to stack after LSP, overlap IntvIn.
1075    //            \_____    Stack interval is live-out.
1076    //
1077    if (BI.LastInstr < LSP) {
1078      DEBUG(dbgs() << ", spill after last use before interference.\n");
1079      selectIntv(IntvIn);
1080      SlotIndex Idx = leaveIntvAfter(BI.LastInstr);
1081      useIntv(Start, Idx);
1082      assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1083    } else {
1084      DEBUG(dbgs() << ", spill before last split point.\n");
1085      selectIntv(IntvIn);
1086      SlotIndex Idx = leaveIntvBefore(LSP);
1087      overlapIntv(Idx, BI.LastInstr);
1088      useIntv(Start, Idx);
1089      assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1090    }
1091    return;
1092  }
1093
1094  // The interference is overlapping somewhere we wanted to use IntvIn. That
1095  // means we need to create a local interval that can be allocated a
1096  // different register.
1097  unsigned LocalIntv = openIntv();
1098  (void)LocalIntv;
1099  DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1100
1101  if (!BI.LiveOut || BI.LastInstr < LSP) {
1102    //
1103    //           <<<<<<<    Interference overlapping uses.
1104    //     |---o---o---|    Live-out on stack.
1105    //     =====----____    Leave IntvIn before interference, then spill.
1106    //
1107    SlotIndex To = leaveIntvAfter(BI.LastInstr);
1108    SlotIndex From = enterIntvBefore(LeaveBefore);
1109    useIntv(From, To);
1110    selectIntv(IntvIn);
1111    useIntv(Start, From);
1112    assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1113    return;
1114  }
1115
1116  //           <<<<<<<    Interference overlapping uses.
1117  //     |---o---o--o|    Live-out on stack, late last use.
1118  //     =====-------     Copy to stack before LSP, overlap LocalIntv.
1119  //            \_____    Stack interval is live-out.
1120  //
1121  SlotIndex To = leaveIntvBefore(LSP);
1122  overlapIntv(To, BI.LastInstr);
1123  SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1124  useIntv(From, To);
1125  selectIntv(IntvIn);
1126  useIntv(Start, From);
1127  assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1128}
1129
1130void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1131                                   unsigned IntvOut, SlotIndex EnterAfter) {
1132  SlotIndex Start, Stop;
1133  tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1134
1135  DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1136               << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1137               << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1138               << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1139
1140  SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1141
1142  assert(IntvOut && "Must have register out");
1143  assert(BI.LiveOut && "Must be live-out");
1144  assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1145
1146  if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1147    DEBUG(dbgs() << " after interference.\n");
1148    //
1149    //    >>>>             Interference before def.
1150    //    |   o---o---|    Defined in block.
1151    //        =========    Use IntvOut everywhere.
1152    //
1153    selectIntv(IntvOut);
1154    useIntv(BI.FirstInstr, Stop);
1155    return;
1156  }
1157
1158  if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1159    DEBUG(dbgs() << ", reload after interference.\n");
1160    //
1161    //    >>>>             Interference before def.
1162    //    |---o---o---|    Live-through, stack-in.
1163    //    ____=========    Enter IntvOut before first use.
1164    //
1165    selectIntv(IntvOut);
1166    SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstInstr));
1167    useIntv(Idx, Stop);
1168    assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1169    return;
1170  }
1171
1172  // The interference is overlapping somewhere we wanted to use IntvOut. That
1173  // means we need to create a local interval that can be allocated a
1174  // different register.
1175  DEBUG(dbgs() << ", interference overlaps uses.\n");
1176  //
1177  //    >>>>>>>          Interference overlapping uses.
1178  //    |---o---o---|    Live-through, stack-in.
1179  //    ____---======    Create local interval for interference range.
1180  //
1181  selectIntv(IntvOut);
1182  SlotIndex Idx = enterIntvAfter(EnterAfter);
1183  useIntv(Idx, Stop);
1184  assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1185
1186  openIntv();
1187  SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstInstr));
1188  useIntv(From, Idx);
1189}
1190