SplitKit.cpp revision fd5c51342a429ecab86a645282d0b36b216c0256 
1//===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the SplitAnalysis class as well as mutator functions for
11// live range splitting.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "regalloc"
16#include "SplitKit.h"
17#include "LiveRangeEdit.h"
18#include "VirtRegMap.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/CodeGen/LiveIntervalAnalysis.h"
21#include "llvm/CodeGen/MachineDominators.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/raw_ostream.h"
26#include "llvm/Target/TargetInstrInfo.h"
27#include "llvm/Target/TargetMachine.h"
28
29using namespace llvm;
30
31STATISTIC(NumFinished, "Number of splits finished");
32STATISTIC(NumSimple,   "Number of splits that were simple");
33
34//===----------------------------------------------------------------------===//
35//                                 Split Analysis
36//===----------------------------------------------------------------------===//
37
38SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
39                             const LiveIntervals &lis,
40                             const MachineLoopInfo &mli)
41  : MF(vrm.getMachineFunction()),
42    VRM(vrm),
43    LIS(lis),
44    Loops(mli),
45    TII(*MF.getTarget().getInstrInfo()),
46    CurLI(0),
47    LastSplitPoint(MF.getNumBlockIDs()) {}
48
49void SplitAnalysis::clear() {
50  UseSlots.clear();
51  UseBlocks.clear();
52  ThroughBlocks.clear();
53  CurLI = 0;
54}
55
56SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
57  const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
58  const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
59  std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
60
61  // Compute split points on the first call. The pair is independent of the
62  // current live interval.
63  if (!LSP.first.isValid()) {
64    MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
65    if (FirstTerm == MBB->end())
66      LSP.first = LIS.getMBBEndIdx(MBB);
67    else
68      LSP.first = LIS.getInstructionIndex(FirstTerm);
69
70    // If there is a landing pad successor, also find the call instruction.
71    if (!LPad)
72      return LSP.first;
73    // There may not be a call instruction (?) in which case we ignore LPad.
74    LSP.second = LSP.first;
75    for (MachineBasicBlock::const_iterator I = FirstTerm, E = MBB->begin();
76         I != E; --I)
77      if (I->getDesc().isCall()) {
78        LSP.second = LIS.getInstructionIndex(I);
79        break;
80      }
81  }
82
83  // If CurLI is live into a landing pad successor, move the last split point
84  // back to the call that may throw.
85  if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
86    return LSP.second;
87  else
88    return LSP.first;
89}
90
91/// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
92void SplitAnalysis::analyzeUses() {
93  assert(UseSlots.empty() && "Call clear first");
94
95  // First get all the defs from the interval values. This provides the correct
96  // slots for early clobbers.
97  for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
98       E = CurLI->vni_end(); I != E; ++I)
99    if (!(*I)->isPHIDef() && !(*I)->isUnused())
100      UseSlots.push_back((*I)->def);
101
102  // Get use slots form the use-def chain.
103  const MachineRegisterInfo &MRI = MF.getRegInfo();
104  for (MachineRegisterInfo::use_nodbg_iterator
105       I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
106       ++I)
107    if (!I.getOperand().isUndef())
108      UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
109
110  array_pod_sort(UseSlots.begin(), UseSlots.end());
111
112  // Remove duplicates, keeping the smaller slot for each instruction.
113  // That is what we want for early clobbers.
114  UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
115                             SlotIndex::isSameInstr),
116                 UseSlots.end());
117
118  // Compute per-live block info.
119  if (!calcLiveBlockInfo()) {
120    // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
121    // I am looking at you, SimpleRegisterCoalescing!
122    DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
123    const_cast<LiveIntervals&>(LIS)
124      .shrinkToUses(const_cast<LiveInterval*>(CurLI));
125    UseBlocks.clear();
126    ThroughBlocks.clear();
127    bool fixed = calcLiveBlockInfo();
128    (void)fixed;
129    assert(fixed && "Couldn't fix broken live interval");
130  }
131
132  DEBUG(dbgs() << "Analyze counted "
133               << UseSlots.size() << " instrs in "
134               << UseBlocks.size() << " blocks, through "
135               << NumThroughBlocks << " blocks.\n");
136}
137
138/// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
139/// where CurLI is live.
140bool SplitAnalysis::calcLiveBlockInfo() {
141  ThroughBlocks.resize(MF.getNumBlockIDs());
142  NumThroughBlocks = 0;
143  if (CurLI->empty())
144    return true;
145
146  LiveInterval::const_iterator LVI = CurLI->begin();
147  LiveInterval::const_iterator LVE = CurLI->end();
148
149  SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
150  UseI = UseSlots.begin();
151  UseE = UseSlots.end();
152
153  // Loop over basic blocks where CurLI is live.
154  MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
155  for (;;) {
156    BlockInfo BI;
157    BI.MBB = MFI;
158    SlotIndex Start, Stop;
159    tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
160
161    // LVI is the first live segment overlapping MBB.
162    BI.LiveIn = LVI->start <= Start;
163    if (!BI.LiveIn)
164      BI.Def = LVI->start;
165
166    // Find the first and last uses in the block.
167    bool Uses = UseI != UseE && *UseI < Stop;
168    if (Uses) {
169      BI.FirstUse = *UseI;
170      assert(BI.FirstUse >= Start);
171      do ++UseI;
172      while (UseI != UseE && *UseI < Stop);
173      BI.LastUse = UseI[-1];
174      assert(BI.LastUse < Stop);
175    }
176
177    // Look for gaps in the live range.
178    bool hasGap = false;
179    BI.LiveOut = true;
180    while (LVI->end < Stop) {
181      SlotIndex LastStop = LVI->end;
182      if (++LVI == LVE || LVI->start >= Stop) {
183        BI.Kill = LastStop;
184        BI.LiveOut = false;
185        break;
186      }
187      if (LastStop < LVI->start) {
188        hasGap = true;
189        BI.Kill = LastStop;
190        BI.Def = LVI->start;
191      }
192    }
193
194    // Don't set LiveThrough when the block has a gap.
195    BI.LiveThrough = !hasGap && BI.LiveIn && BI.LiveOut;
196    if (Uses)
197      UseBlocks.push_back(BI);
198    else {
199      ++NumThroughBlocks;
200      ThroughBlocks.set(BI.MBB->getNumber());
201    }
202    // FIXME: This should never happen. The live range stops or starts without a
203    // corresponding use. An earlier pass did something wrong.
204    if (!BI.LiveThrough && !Uses)
205      return false;
206
207    // LVI is now at LVE or LVI->end >= Stop.
208    if (LVI == LVE)
209      break;
210
211    // Live segment ends exactly at Stop. Move to the next segment.
212    if (LVI->end == Stop && ++LVI == LVE)
213      break;
214
215    // Pick the next basic block.
216    if (LVI->start < Stop)
217      ++MFI;
218    else
219      MFI = LIS.getMBBFromIndex(LVI->start);
220  }
221  return true;
222}
223
224bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
225  unsigned OrigReg = VRM.getOriginal(CurLI->reg);
226  const LiveInterval &Orig = LIS.getInterval(OrigReg);
227  assert(!Orig.empty() && "Splitting empty interval?");
228  LiveInterval::const_iterator I = Orig.find(Idx);
229
230  // Range containing Idx should begin at Idx.
231  if (I != Orig.end() && I->start <= Idx)
232    return I->start == Idx;
233
234  // Range does not contain Idx, previous must end at Idx.
235  return I != Orig.begin() && (--I)->end == Idx;
236}
237
238void SplitAnalysis::analyze(const LiveInterval *li) {
239  clear();
240  CurLI = li;
241  analyzeUses();
242}
243
244
245//===----------------------------------------------------------------------===//
246//                               Split Editor
247//===----------------------------------------------------------------------===//
248
249/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
250SplitEditor::SplitEditor(SplitAnalysis &sa,
251                         LiveIntervals &lis,
252                         VirtRegMap &vrm,
253                         MachineDominatorTree &mdt)
254  : SA(sa), LIS(lis), VRM(vrm),
255    MRI(vrm.getMachineFunction().getRegInfo()),
256    MDT(mdt),
257    TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
258    TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
259    Edit(0),
260    OpenIdx(0),
261    RegAssign(Allocator)
262{}
263
264void SplitEditor::reset(LiveRangeEdit &lre) {
265  Edit = &lre;
266  OpenIdx = 0;
267  RegAssign.clear();
268  Values.clear();
269
270  // We don't need to clear LiveOutCache, only LiveOutSeen entries are read.
271  LiveOutSeen.clear();
272
273  // We don't need an AliasAnalysis since we will only be performing
274  // cheap-as-a-copy remats anyway.
275  Edit->anyRematerializable(LIS, TII, 0);
276}
277
278void SplitEditor::dump() const {
279  if (RegAssign.empty()) {
280    dbgs() << " empty\n";
281    return;
282  }
283
284  for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
285    dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
286  dbgs() << '\n';
287}
288
289VNInfo *SplitEditor::defValue(unsigned RegIdx,
290                              const VNInfo *ParentVNI,
291                              SlotIndex Idx) {
292  assert(ParentVNI && "Mapping  NULL value");
293  assert(Idx.isValid() && "Invalid SlotIndex");
294  assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
295  LiveInterval *LI = Edit->get(RegIdx);
296
297  // Create a new value.
298  VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
299
300  // Use insert for lookup, so we can add missing values with a second lookup.
301  std::pair<ValueMap::iterator, bool> InsP =
302    Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
303
304  // This was the first time (RegIdx, ParentVNI) was mapped.
305  // Keep it as a simple def without any liveness.
306  if (InsP.second)
307    return VNI;
308
309  // If the previous value was a simple mapping, add liveness for it now.
310  if (VNInfo *OldVNI = InsP.first->second) {
311    SlotIndex Def = OldVNI->def;
312    LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
313    // No longer a simple mapping.
314    InsP.first->second = 0;
315  }
316
317  // This is a complex mapping, add liveness for VNI
318  SlotIndex Def = VNI->def;
319  LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
320
321  return VNI;
322}
323
324void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
325  assert(ParentVNI && "Mapping  NULL value");
326  VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
327
328  // ParentVNI was either unmapped or already complex mapped. Either way.
329  if (!VNI)
330    return;
331
332  // This was previously a single mapping. Make sure the old def is represented
333  // by a trivial live range.
334  SlotIndex Def = VNI->def;
335  Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
336  VNI = 0;
337}
338
339// extendRange - Extend the live range to reach Idx.
340// Potentially create phi-def values.
341void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
342  assert(Idx.isValid() && "Invalid SlotIndex");
343  MachineBasicBlock *IdxMBB = LIS.getMBBFromIndex(Idx);
344  assert(IdxMBB && "No MBB at Idx");
345  LiveInterval *LI = Edit->get(RegIdx);
346
347  // Is there a def in the same MBB we can extend?
348  if (LI->extendInBlock(LIS.getMBBStartIdx(IdxMBB), Idx))
349    return;
350
351  // Now for the fun part. We know that ParentVNI potentially has multiple defs,
352  // and we may need to create even more phi-defs to preserve VNInfo SSA form.
353  // Perform a search for all predecessor blocks where we know the dominating
354  // VNInfo. Insert phi-def VNInfos along the path back to IdxMBB.
355
356  // Initialize the live-out cache the first time it is needed.
357  if (LiveOutSeen.empty()) {
358    unsigned N = VRM.getMachineFunction().getNumBlockIDs();
359    LiveOutSeen.resize(N);
360    LiveOutCache.resize(N);
361  }
362
363  // Blocks where LI should be live-in.
364  SmallVector<MachineDomTreeNode*, 16> LiveIn;
365  LiveIn.push_back(MDT[IdxMBB]);
366
367  // Remember if we have seen more than one value.
368  bool UniqueVNI = true;
369  VNInfo *IdxVNI = 0;
370
371  // Using LiveOutCache as a visited set, perform a BFS for all reaching defs.
372  for (unsigned i = 0; i != LiveIn.size(); ++i) {
373    MachineBasicBlock *MBB = LiveIn[i]->getBlock();
374    assert(!MBB->pred_empty() && "Value live-in to entry block?");
375    for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
376           PE = MBB->pred_end(); PI != PE; ++PI) {
377       MachineBasicBlock *Pred = *PI;
378       LiveOutPair &LOP = LiveOutCache[Pred];
379
380       // Is this a known live-out block?
381       if (LiveOutSeen.test(Pred->getNumber())) {
382         if (VNInfo *VNI = LOP.first) {
383           if (IdxVNI && IdxVNI != VNI)
384             UniqueVNI = false;
385           IdxVNI = VNI;
386         }
387         continue;
388       }
389
390       // First time. LOP is garbage and must be cleared below.
391       LiveOutSeen.set(Pred->getNumber());
392
393       // Does Pred provide a live-out value?
394       SlotIndex Start, Last;
395       tie(Start, Last) = LIS.getSlotIndexes()->getMBBRange(Pred);
396       Last = Last.getPrevSlot();
397       VNInfo *VNI = LI->extendInBlock(Start, Last);
398       LOP.first = VNI;
399       if (VNI) {
400         LOP.second = MDT[LIS.getMBBFromIndex(VNI->def)];
401         if (IdxVNI && IdxVNI != VNI)
402           UniqueVNI = false;
403         IdxVNI = VNI;
404         continue;
405       }
406       LOP.second = 0;
407
408       // No, we need a live-in value for Pred as well
409       if (Pred != IdxMBB)
410         LiveIn.push_back(MDT[Pred]);
411       else
412         UniqueVNI = false; // Loopback to IdxMBB, ask updateSSA() for help.
413    }
414  }
415
416  // We may need to add phi-def values to preserve the SSA form.
417  if (UniqueVNI) {
418    LiveOutPair LOP(IdxVNI, MDT[LIS.getMBBFromIndex(IdxVNI->def)]);
419    // Update LiveOutCache, but skip IdxMBB at LiveIn[0].
420    for (unsigned i = 1, e = LiveIn.size(); i != e; ++i)
421      LiveOutCache[LiveIn[i]->getBlock()] = LOP;
422  } else
423    IdxVNI = updateSSA(RegIdx, LiveIn, Idx, IdxMBB);
424
425  // Since we went through the trouble of a full BFS visiting all reaching defs,
426  // the values in LiveIn are now accurate. No more phi-defs are needed
427  // for these blocks, so we can color the live ranges.
428  for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) {
429    MachineBasicBlock *MBB = LiveIn[i]->getBlock();
430    SlotIndex Start = LIS.getMBBStartIdx(MBB);
431    VNInfo *VNI = LiveOutCache[MBB].first;
432
433    // Anything in LiveIn other than IdxMBB is live-through.
434    // In IdxMBB, we should stop at Idx unless the same value is live-out.
435    if (MBB == IdxMBB && IdxVNI != VNI)
436      LI->addRange(LiveRange(Start, Idx.getNextSlot(), IdxVNI));
437    else
438      LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
439  }
440}
441
442VNInfo *SplitEditor::updateSSA(unsigned RegIdx,
443                               SmallVectorImpl<MachineDomTreeNode*> &LiveIn,
444                               SlotIndex Idx,
445                               const MachineBasicBlock *IdxMBB) {
446  // This is essentially the same iterative algorithm that SSAUpdater uses,
447  // except we already have a dominator tree, so we don't have to recompute it.
448  LiveInterval *LI = Edit->get(RegIdx);
449  VNInfo *IdxVNI = 0;
450  unsigned Changes;
451  do {
452    Changes = 0;
453    // Propagate live-out values down the dominator tree, inserting phi-defs
454    // when necessary. Since LiveIn was created by a BFS, going backwards makes
455    // it more likely for us to visit immediate dominators before their
456    // children.
457    for (unsigned i = LiveIn.size(); i; --i) {
458      MachineDomTreeNode *Node = LiveIn[i-1];
459      MachineBasicBlock *MBB = Node->getBlock();
460      MachineDomTreeNode *IDom = Node->getIDom();
461      LiveOutPair IDomValue;
462
463      // We need a live-in value to a block with no immediate dominator?
464      // This is probably an unreachable block that has survived somehow.
465      bool needPHI = !IDom || !LiveOutSeen.test(IDom->getBlock()->getNumber());
466
467      // IDom dominates all of our predecessors, but it may not be the immediate
468      // dominator. Check if any of them have live-out values that are properly
469      // dominated by IDom. If so, we need a phi-def here.
470      if (!needPHI) {
471        IDomValue = LiveOutCache[IDom->getBlock()];
472        for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
473               PE = MBB->pred_end(); PI != PE; ++PI) {
474          LiveOutPair Value = LiveOutCache[*PI];
475          if (!Value.first || Value.first == IDomValue.first)
476            continue;
477          // This predecessor is carrying something other than IDomValue.
478          // It could be because IDomValue hasn't propagated yet, or it could be
479          // because MBB is in the dominance frontier of that value.
480          if (MDT.dominates(IDom, Value.second)) {
481            needPHI = true;
482            break;
483          }
484        }
485      }
486
487      // Create a phi-def if required.
488      if (needPHI) {
489        ++Changes;
490        SlotIndex Start = LIS.getMBBStartIdx(MBB);
491        VNInfo *VNI = LI->getNextValue(Start, 0, LIS.getVNInfoAllocator());
492        VNI->setIsPHIDef(true);
493        // We no longer need LI to be live-in.
494        LiveIn.erase(LiveIn.begin()+(i-1));
495        // Blocks in LiveIn are either IdxMBB, or have a value live-through.
496        if (MBB == IdxMBB)
497          IdxVNI = VNI;
498        // Check if we need to update live-out info.
499        LiveOutPair &LOP = LiveOutCache[MBB];
500        if (LOP.second == Node || !LiveOutSeen.test(MBB->getNumber())) {
501          // We already have a live-out defined in MBB, so this must be IdxMBB.
502          assert(MBB == IdxMBB && "Adding phi-def to known live-out");
503          LI->addRange(LiveRange(Start, Idx.getNextSlot(), VNI));
504        } else {
505          // This phi-def is also live-out, so color the whole block.
506          LI->addRange(LiveRange(Start, LIS.getMBBEndIdx(MBB), VNI));
507          LOP = LiveOutPair(VNI, Node);
508        }
509      } else if (IDomValue.first) {
510        // No phi-def here. Remember incoming value for IdxMBB.
511        if (MBB == IdxMBB) {
512          IdxVNI = IDomValue.first;
513          // IdxMBB need not be live-out.
514          if (!LiveOutSeen.test(MBB->getNumber()))
515            continue;
516        }
517        assert(LiveOutSeen.test(MBB->getNumber()) && "Expected live-out block");
518        // Propagate IDomValue if needed:
519        // MBB is live-out and doesn't define its own value.
520        LiveOutPair &LOP = LiveOutCache[MBB];
521        if (LOP.second != Node && LOP.first != IDomValue.first) {
522          ++Changes;
523          LOP = IDomValue;
524        }
525      }
526    }
527  } while (Changes);
528
529  assert(IdxVNI && "Didn't find value for Idx");
530  return IdxVNI;
531}
532
533VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
534                                   VNInfo *ParentVNI,
535                                   SlotIndex UseIdx,
536                                   MachineBasicBlock &MBB,
537                                   MachineBasicBlock::iterator I) {
538  MachineInstr *CopyMI = 0;
539  SlotIndex Def;
540  LiveInterval *LI = Edit->get(RegIdx);
541
542  // Attempt cheap-as-a-copy rematerialization.
543  LiveRangeEdit::Remat RM(ParentVNI);
544  if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
545    Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI);
546  } else {
547    // Can't remat, just insert a copy from parent.
548    CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
549               .addReg(Edit->getReg());
550    Def = LIS.InsertMachineInstrInMaps(CopyMI).getDefIndex();
551  }
552
553  // Define the value in Reg.
554  VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
555  VNI->setCopy(CopyMI);
556  return VNI;
557}
558
559/// Create a new virtual register and live interval.
560unsigned SplitEditor::openIntv() {
561  assert(!OpenIdx && "Previous LI not closed before openIntv");
562
563  // Create the complement as index 0.
564  if (Edit->empty())
565    Edit->create(LIS, VRM);
566
567  // Create the open interval.
568  OpenIdx = Edit->size();
569  Edit->create(LIS, VRM);
570  return OpenIdx;
571}
572
573void SplitEditor::selectIntv(unsigned Idx) {
574  assert(Idx != 0 && "Cannot select the complement interval");
575  assert(Idx < Edit->size() && "Can only select previously opened interval");
576  OpenIdx = Idx;
577}
578
579SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
580  assert(OpenIdx && "openIntv not called before enterIntvBefore");
581  DEBUG(dbgs() << "    enterIntvBefore " << Idx);
582  Idx = Idx.getBaseIndex();
583  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
584  if (!ParentVNI) {
585    DEBUG(dbgs() << ": not live\n");
586    return Idx;
587  }
588  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
589  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
590  assert(MI && "enterIntvBefore called with invalid index");
591
592  VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
593  return VNI->def;
594}
595
596SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
597  assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
598  SlotIndex End = LIS.getMBBEndIdx(&MBB);
599  SlotIndex Last = End.getPrevSlot();
600  DEBUG(dbgs() << "    enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
601  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
602  if (!ParentVNI) {
603    DEBUG(dbgs() << ": not live\n");
604    return End;
605  }
606  DEBUG(dbgs() << ": valno " << ParentVNI->id);
607  VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
608                              LIS.getLastSplitPoint(Edit->getParent(), &MBB));
609  RegAssign.insert(VNI->def, End, OpenIdx);
610  DEBUG(dump());
611  return VNI->def;
612}
613
614/// useIntv - indicate that all instructions in MBB should use OpenLI.
615void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
616  useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
617}
618
619void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
620  assert(OpenIdx && "openIntv not called before useIntv");
621  DEBUG(dbgs() << "    useIntv [" << Start << ';' << End << "):");
622  RegAssign.insert(Start, End, OpenIdx);
623  DEBUG(dump());
624}
625
626SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
627  assert(OpenIdx && "openIntv not called before leaveIntvAfter");
628  DEBUG(dbgs() << "    leaveIntvAfter " << Idx);
629
630  // The interval must be live beyond the instruction at Idx.
631  Idx = Idx.getBoundaryIndex();
632  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
633  if (!ParentVNI) {
634    DEBUG(dbgs() << ": not live\n");
635    return Idx.getNextSlot();
636  }
637  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
638
639  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
640  assert(MI && "No instruction at index");
641  VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
642                              llvm::next(MachineBasicBlock::iterator(MI)));
643  return VNI->def;
644}
645
646SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
647  assert(OpenIdx && "openIntv not called before leaveIntvBefore");
648  DEBUG(dbgs() << "    leaveIntvBefore " << Idx);
649
650  // The interval must be live into the instruction at Idx.
651  Idx = Idx.getBoundaryIndex();
652  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
653  if (!ParentVNI) {
654    DEBUG(dbgs() << ": not live\n");
655    return Idx.getNextSlot();
656  }
657  DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
658
659  MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
660  assert(MI && "No instruction at index");
661  VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
662  return VNI->def;
663}
664
665SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
666  assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
667  SlotIndex Start = LIS.getMBBStartIdx(&MBB);
668  DEBUG(dbgs() << "    leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
669
670  VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
671  if (!ParentVNI) {
672    DEBUG(dbgs() << ": not live\n");
673    return Start;
674  }
675
676  VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
677                              MBB.SkipPHIsAndLabels(MBB.begin()));
678  RegAssign.insert(Start, VNI->def, OpenIdx);
679  DEBUG(dump());
680  return VNI->def;
681}
682
683void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
684  assert(OpenIdx && "openIntv not called before overlapIntv");
685  const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
686  assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
687         "Parent changes value in extended range");
688  assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
689         "Range cannot span basic blocks");
690
691  // The complement interval will be extended as needed by extendRange().
692  if (ParentVNI)
693    markComplexMapped(0, ParentVNI);
694  DEBUG(dbgs() << "    overlapIntv [" << Start << ';' << End << "):");
695  RegAssign.insert(Start, End, OpenIdx);
696  DEBUG(dump());
697}
698
699/// closeIntv - Indicate that we are done editing the currently open
700/// LiveInterval, and ranges can be trimmed.
701void SplitEditor::closeIntv() {
702  assert(OpenIdx && "openIntv not called before closeIntv");
703  OpenIdx = 0;
704}
705
706/// transferSimpleValues - Transfer all simply defined values to the new live
707/// ranges.
708/// Values that were rematerialized or that have multiple defs are left alone.
709bool SplitEditor::transferSimpleValues() {
710  bool Skipped = false;
711  RegAssignMap::const_iterator AssignI = RegAssign.begin();
712  for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
713         ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
714    DEBUG(dbgs() << "  blit " << *ParentI << ':');
715    VNInfo *ParentVNI = ParentI->valno;
716    // RegAssign has holes where RegIdx 0 should be used.
717    SlotIndex Start = ParentI->start;
718    AssignI.advanceTo(Start);
719    do {
720      unsigned RegIdx;
721      SlotIndex End = ParentI->end;
722      if (!AssignI.valid()) {
723        RegIdx = 0;
724      } else if (AssignI.start() <= Start) {
725        RegIdx = AssignI.value();
726        if (AssignI.stop() < End) {
727          End = AssignI.stop();
728          ++AssignI;
729        }
730      } else {
731        RegIdx = 0;
732        End = std::min(End, AssignI.start());
733      }
734      DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
735      if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
736        DEBUG(dbgs() << ':' << VNI->id);
737        Edit->get(RegIdx)->addRange(LiveRange(Start, End, VNI));
738      } else
739        Skipped = true;
740      Start = End;
741    } while (Start != ParentI->end);
742    DEBUG(dbgs() << '\n');
743  }
744  return Skipped;
745}
746
747void SplitEditor::extendPHIKillRanges() {
748    // Extend live ranges to be live-out for successor PHI values.
749  for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
750       E = Edit->getParent().vni_end(); I != E; ++I) {
751    const VNInfo *PHIVNI = *I;
752    if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
753      continue;
754    unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
755    MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
756    for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
757         PE = MBB->pred_end(); PI != PE; ++PI) {
758      SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
759      // The predecessor may not have a live-out value. That is OK, like an
760      // undef PHI operand.
761      if (Edit->getParent().liveAt(End)) {
762        assert(RegAssign.lookup(End) == RegIdx &&
763               "Different register assignment in phi predecessor");
764        extendRange(RegIdx, End);
765      }
766    }
767  }
768}
769
770/// rewriteAssigned - Rewrite all uses of Edit->getReg().
771void SplitEditor::rewriteAssigned(bool ExtendRanges) {
772  for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
773       RE = MRI.reg_end(); RI != RE;) {
774    MachineOperand &MO = RI.getOperand();
775    MachineInstr *MI = MO.getParent();
776    ++RI;
777    // LiveDebugVariables should have handled all DBG_VALUE instructions.
778    if (MI->isDebugValue()) {
779      DEBUG(dbgs() << "Zapping " << *MI);
780      MO.setReg(0);
781      continue;
782    }
783
784    // <undef> operands don't really read the register, so just assign them to
785    // the complement.
786    if (MO.isUse() && MO.isUndef()) {
787      MO.setReg(Edit->get(0)->reg);
788      continue;
789    }
790
791    SlotIndex Idx = LIS.getInstructionIndex(MI);
792    if (MO.isDef())
793      Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex();
794
795    // Rewrite to the mapped register at Idx.
796    unsigned RegIdx = RegAssign.lookup(Idx);
797    MO.setReg(Edit->get(RegIdx)->reg);
798    DEBUG(dbgs() << "  rewr BB#" << MI->getParent()->getNumber() << '\t'
799                 << Idx << ':' << RegIdx << '\t' << *MI);
800
801    // Extend liveness to Idx if the instruction reads reg.
802    if (!ExtendRanges)
803      continue;
804
805    // Skip instructions that don't read Reg.
806    if (MO.isDef()) {
807      if (!MO.getSubReg() && !MO.isEarlyClobber())
808        continue;
809      // We may wan't to extend a live range for a partial redef, or for a use
810      // tied to an early clobber.
811      Idx = Idx.getPrevSlot();
812      if (!Edit->getParent().liveAt(Idx))
813        continue;
814    } else
815      Idx = Idx.getUseIndex();
816
817    extendRange(RegIdx, Idx);
818  }
819}
820
821void SplitEditor::deleteRematVictims() {
822  SmallVector<MachineInstr*, 8> Dead;
823  for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
824    LiveInterval *LI = *I;
825    for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
826           LII != LIE; ++LII) {
827      // Dead defs end at the store slot.
828      if (LII->end != LII->valno->def.getNextSlot())
829        continue;
830      MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
831      assert(MI && "Missing instruction for dead def");
832      MI->addRegisterDead(LI->reg, &TRI);
833
834      if (!MI->allDefsAreDead())
835        continue;
836
837      DEBUG(dbgs() << "All defs dead: " << *MI);
838      Dead.push_back(MI);
839    }
840  }
841
842  if (Dead.empty())
843    return;
844
845  Edit->eliminateDeadDefs(Dead, LIS, VRM, TII);
846}
847
848void SplitEditor::finish() {
849  assert(OpenIdx == 0 && "Previous LI not closed before rewrite");
850  ++NumFinished;
851
852  // At this point, the live intervals in Edit contain VNInfos corresponding to
853  // the inserted copies.
854
855  // Add the original defs from the parent interval.
856  for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
857         E = Edit->getParent().vni_end(); I != E; ++I) {
858    const VNInfo *ParentVNI = *I;
859    if (ParentVNI->isUnused())
860      continue;
861    unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
862    VNInfo *VNI = defValue(RegIdx, ParentVNI, ParentVNI->def);
863    VNI->setIsPHIDef(ParentVNI->isPHIDef());
864    VNI->setCopy(ParentVNI->getCopy());
865
866    // Mark rematted values as complex everywhere to force liveness computation.
867    // The new live ranges may be truncated.
868    if (Edit->didRematerialize(ParentVNI))
869      for (unsigned i = 0, e = Edit->size(); i != e; ++i)
870        markComplexMapped(i, ParentVNI);
871  }
872
873#ifndef NDEBUG
874  // Every new interval must have a def by now, otherwise the split is bogus.
875  for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
876    assert((*I)->hasAtLeastOneValue() && "Split interval has no value");
877#endif
878
879  // Transfer the simply mapped values, check if any are complex.
880  bool Complex = transferSimpleValues();
881  if (Complex)
882    extendPHIKillRanges();
883  else
884    ++NumSimple;
885
886  // Rewrite virtual registers, possibly extending ranges.
887  rewriteAssigned(Complex);
888
889  // Delete defs that were rematted everywhere.
890  if (Complex)
891    deleteRematVictims();
892
893  // Get rid of unused values and set phi-kill flags.
894  for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
895    (*I)->RenumberValues(LIS);
896
897  // Now check if any registers were separated into multiple components.
898  ConnectedVNInfoEqClasses ConEQ(LIS);
899  for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
900    // Don't use iterators, they are invalidated by create() below.
901    LiveInterval *li = Edit->get(i);
902    unsigned NumComp = ConEQ.Classify(li);
903    if (NumComp <= 1)
904      continue;
905    DEBUG(dbgs() << "  " << NumComp << " components: " << *li << '\n');
906    SmallVector<LiveInterval*, 8> dups;
907    dups.push_back(li);
908    for (unsigned i = 1; i != NumComp; ++i)
909      dups.push_back(&Edit->create(LIS, VRM));
910    ConEQ.Distribute(&dups[0], MRI);
911  }
912
913  // Calculate spill weight and allocation hints for new intervals.
914  Edit->calculateRegClassAndHint(VRM.getMachineFunction(), LIS, SA.Loops);
915}
916
917
918//===----------------------------------------------------------------------===//
919//                            Single Block Splitting
920//===----------------------------------------------------------------------===//
921
922/// getMultiUseBlocks - if CurLI has more than one use in a basic block, it
923/// may be an advantage to split CurLI for the duration of the block.
924bool SplitAnalysis::getMultiUseBlocks(BlockPtrSet &Blocks) {
925  // If CurLI is local to one block, there is no point to splitting it.
926  if (UseBlocks.size() <= 1)
927    return false;
928  // Add blocks with multiple uses.
929  for (unsigned i = 0, e = UseBlocks.size(); i != e; ++i) {
930    const BlockInfo &BI = UseBlocks[i];
931    if (BI.FirstUse == BI.LastUse)
932      continue;
933    Blocks.insert(BI.MBB);
934  }
935  return !Blocks.empty();
936}
937
938void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
939  openIntv();
940  SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
941  SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstUse,
942    LastSplitPoint));
943  if (!BI.LiveOut || BI.LastUse < LastSplitPoint) {
944    useIntv(SegStart, leaveIntvAfter(BI.LastUse));
945  } else {
946      // The last use is after the last valid split point.
947    SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
948    useIntv(SegStart, SegStop);
949    overlapIntv(SegStop, BI.LastUse);
950  }
951  closeIntv();
952}
953
954/// splitSingleBlocks - Split CurLI into a separate live interval inside each
955/// basic block in Blocks.
956void SplitEditor::splitSingleBlocks(const SplitAnalysis::BlockPtrSet &Blocks) {
957  DEBUG(dbgs() << "  splitSingleBlocks for " << Blocks.size() << " blocks.\n");
958  ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA.getUseBlocks();
959  for (unsigned i = 0; i != UseBlocks.size(); ++i) {
960    const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
961    if (Blocks.count(BI.MBB))
962      splitSingleBlock(BI);
963  }
964  finish();
965}
966