TwoAddressInstructionPass.cpp revision 1487cb3a5a0535b343e602e976af538fd87d0df2
1//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the TwoAddress instruction pass which is used 11// by most register allocators. Two-Address instructions are rewritten 12// from: 13// 14// A = B op C 15// 16// to: 17// 18// A = B 19// A op= C 20// 21// Note that if a register allocator chooses to use this pass, that it 22// has to be capable of handling the non-SSA nature of these rewritten 23// virtual registers. 24// 25// It is also worth noting that the duplicate operand of the two 26// address instruction is removed. 27// 28//===----------------------------------------------------------------------===// 29 30#define DEBUG_TYPE "twoaddrinstr" 31#include "llvm/CodeGen/Passes.h" 32#include "llvm/Function.h" 33#include "llvm/CodeGen/LiveVariables.h" 34#include "llvm/CodeGen/MachineFunctionPass.h" 35#include "llvm/CodeGen/MachineInstr.h" 36#include "llvm/CodeGen/MachineInstrBuilder.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/Analysis/AliasAnalysis.h" 39#include "llvm/MC/MCInstrItineraries.h" 40#include "llvm/Target/TargetRegisterInfo.h" 41#include "llvm/Target/TargetInstrInfo.h" 42#include "llvm/Target/TargetMachine.h" 43#include "llvm/Target/TargetOptions.h" 44#include "llvm/Support/Debug.h" 45#include "llvm/Support/ErrorHandling.h" 46#include "llvm/ADT/BitVector.h" 47#include "llvm/ADT/DenseMap.h" 48#include "llvm/ADT/SmallSet.h" 49#include "llvm/ADT/Statistic.h" 50#include "llvm/ADT/STLExtras.h" 51using namespace llvm; 52 53STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions"); 54STATISTIC(NumCommuted , "Number of instructions commuted to coalesce"); 55STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted"); 56STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address"); 57STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk"); 58STATISTIC(NumReMats, "Number of instructions re-materialized"); 59STATISTIC(NumDeletes, "Number of dead instructions deleted"); 60STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up"); 61STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down"); 62 63namespace { 64 class TwoAddressInstructionPass : public MachineFunctionPass { 65 const TargetInstrInfo *TII; 66 const TargetRegisterInfo *TRI; 67 const InstrItineraryData *InstrItins; 68 MachineRegisterInfo *MRI; 69 LiveVariables *LV; 70 AliasAnalysis *AA; 71 CodeGenOpt::Level OptLevel; 72 73 // DistanceMap - Keep track the distance of a MI from the start of the 74 // current basic block. 75 DenseMap<MachineInstr*, unsigned> DistanceMap; 76 77 // SrcRegMap - A map from virtual registers to physical registers which 78 // are likely targets to be coalesced to due to copies from physical 79 // registers to virtual registers. e.g. v1024 = move r0. 80 DenseMap<unsigned, unsigned> SrcRegMap; 81 82 // DstRegMap - A map from virtual registers to physical registers which 83 // are likely targets to be coalesced to due to copies to physical 84 // registers from virtual registers. e.g. r1 = move v1024. 85 DenseMap<unsigned, unsigned> DstRegMap; 86 87 /// RegSequences - Keep track the list of REG_SEQUENCE instructions seen 88 /// during the initial walk of the machine function. 89 SmallVector<MachineInstr*, 16> RegSequences; 90 91 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI, 92 unsigned Reg, 93 MachineBasicBlock::iterator OldPos); 94 95 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC, 96 MachineInstr *MI, MachineInstr *DefMI, 97 MachineBasicBlock *MBB, unsigned Loc); 98 99 bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist, 100 unsigned &LastDef); 101 102 MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB, 103 unsigned Dist); 104 105 bool isProfitableToCommute(unsigned regB, unsigned regC, 106 MachineInstr *MI, MachineBasicBlock *MBB, 107 unsigned Dist); 108 109 bool CommuteInstruction(MachineBasicBlock::iterator &mi, 110 MachineFunction::iterator &mbbi, 111 unsigned RegB, unsigned RegC, unsigned Dist); 112 113 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB); 114 115 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi, 116 MachineBasicBlock::iterator &nmi, 117 MachineFunction::iterator &mbbi, 118 unsigned RegA, unsigned RegB, unsigned Dist); 119 120 typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill; 121 bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills, 122 SmallVector<NewKill, 4> &NewKills, 123 MachineBasicBlock *MBB, unsigned Dist); 124 bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi, 125 MachineBasicBlock::iterator &nmi, 126 MachineFunction::iterator &mbbi, unsigned Dist); 127 128 bool isDefTooClose(unsigned Reg, unsigned Dist, 129 MachineInstr *MI, MachineBasicBlock *MBB); 130 131 bool RescheduleMIBelowKill(MachineBasicBlock *MBB, 132 MachineBasicBlock::iterator &mi, 133 MachineBasicBlock::iterator &nmi, 134 unsigned Reg); 135 bool RescheduleKillAboveMI(MachineBasicBlock *MBB, 136 MachineBasicBlock::iterator &mi, 137 MachineBasicBlock::iterator &nmi, 138 unsigned Reg); 139 140 bool TryInstructionTransform(MachineBasicBlock::iterator &mi, 141 MachineBasicBlock::iterator &nmi, 142 MachineFunction::iterator &mbbi, 143 unsigned SrcIdx, unsigned DstIdx, 144 unsigned Dist, 145 SmallPtrSet<MachineInstr*, 8> &Processed); 146 147 void ScanUses(unsigned DstReg, MachineBasicBlock *MBB, 148 SmallPtrSet<MachineInstr*, 8> &Processed); 149 150 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB, 151 SmallPtrSet<MachineInstr*, 8> &Processed); 152 153 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg); 154 155 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part 156 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as 157 /// sub-register references of the register defined by REG_SEQUENCE. 158 bool EliminateRegSequences(); 159 160 public: 161 static char ID; // Pass identification, replacement for typeid 162 TwoAddressInstructionPass() : MachineFunctionPass(ID) { 163 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry()); 164 } 165 166 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 167 AU.setPreservesCFG(); 168 AU.addRequired<AliasAnalysis>(); 169 AU.addPreserved<LiveVariables>(); 170 AU.addPreservedID(MachineLoopInfoID); 171 AU.addPreservedID(MachineDominatorsID); 172 MachineFunctionPass::getAnalysisUsage(AU); 173 } 174 175 /// runOnMachineFunction - Pass entry point. 176 bool runOnMachineFunction(MachineFunction&); 177 }; 178} 179 180char TwoAddressInstructionPass::ID = 0; 181INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction", 182 "Two-Address instruction pass", false, false) 183INITIALIZE_AG_DEPENDENCY(AliasAnalysis) 184INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction", 185 "Two-Address instruction pass", false, false) 186 187char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID; 188 189/// Sink3AddrInstruction - A two-address instruction has been converted to a 190/// three-address instruction to avoid clobbering a register. Try to sink it 191/// past the instruction that would kill the above mentioned register to reduce 192/// register pressure. 193bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB, 194 MachineInstr *MI, unsigned SavedReg, 195 MachineBasicBlock::iterator OldPos) { 196 // FIXME: Shouldn't we be trying to do this before we three-addressify the 197 // instruction? After this transformation is done, we no longer need 198 // the instruction to be in three-address form. 199 200 // Check if it's safe to move this instruction. 201 bool SeenStore = true; // Be conservative. 202 if (!MI->isSafeToMove(TII, AA, SeenStore)) 203 return false; 204 205 unsigned DefReg = 0; 206 SmallSet<unsigned, 4> UseRegs; 207 208 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 209 const MachineOperand &MO = MI->getOperand(i); 210 if (!MO.isReg()) 211 continue; 212 unsigned MOReg = MO.getReg(); 213 if (!MOReg) 214 continue; 215 if (MO.isUse() && MOReg != SavedReg) 216 UseRegs.insert(MO.getReg()); 217 if (!MO.isDef()) 218 continue; 219 if (MO.isImplicit()) 220 // Don't try to move it if it implicitly defines a register. 221 return false; 222 if (DefReg) 223 // For now, don't move any instructions that define multiple registers. 224 return false; 225 DefReg = MO.getReg(); 226 } 227 228 // Find the instruction that kills SavedReg. 229 MachineInstr *KillMI = NULL; 230 for (MachineRegisterInfo::use_nodbg_iterator 231 UI = MRI->use_nodbg_begin(SavedReg), 232 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 233 MachineOperand &UseMO = UI.getOperand(); 234 if (!UseMO.isKill()) 235 continue; 236 KillMI = UseMO.getParent(); 237 break; 238 } 239 240 // If we find the instruction that kills SavedReg, and it is in an 241 // appropriate location, we can try to sink the current instruction 242 // past it. 243 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI || 244 KillMI->isTerminator()) 245 return false; 246 247 // If any of the definitions are used by another instruction between the 248 // position and the kill use, then it's not safe to sink it. 249 // 250 // FIXME: This can be sped up if there is an easy way to query whether an 251 // instruction is before or after another instruction. Then we can use 252 // MachineRegisterInfo def / use instead. 253 MachineOperand *KillMO = NULL; 254 MachineBasicBlock::iterator KillPos = KillMI; 255 ++KillPos; 256 257 unsigned NumVisited = 0; 258 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) { 259 MachineInstr *OtherMI = I; 260 // DBG_VALUE cannot be counted against the limit. 261 if (OtherMI->isDebugValue()) 262 continue; 263 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost. 264 return false; 265 ++NumVisited; 266 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { 267 MachineOperand &MO = OtherMI->getOperand(i); 268 if (!MO.isReg()) 269 continue; 270 unsigned MOReg = MO.getReg(); 271 if (!MOReg) 272 continue; 273 if (DefReg == MOReg) 274 return false; 275 276 if (MO.isKill()) { 277 if (OtherMI == KillMI && MOReg == SavedReg) 278 // Save the operand that kills the register. We want to unset the kill 279 // marker if we can sink MI past it. 280 KillMO = &MO; 281 else if (UseRegs.count(MOReg)) 282 // One of the uses is killed before the destination. 283 return false; 284 } 285 } 286 } 287 288 // Update kill and LV information. 289 KillMO->setIsKill(false); 290 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI); 291 KillMO->setIsKill(true); 292 293 if (LV) 294 LV->replaceKillInstruction(SavedReg, KillMI, MI); 295 296 // Move instruction to its destination. 297 MBB->remove(MI); 298 MBB->insert(KillPos, MI); 299 300 ++Num3AddrSunk; 301 return true; 302} 303 304/// isTwoAddrUse - Return true if the specified MI is using the specified 305/// register as a two-address operand. 306static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) { 307 const MCInstrDesc &MCID = UseMI->getDesc(); 308 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { 309 MachineOperand &MO = UseMI->getOperand(i); 310 if (MO.isReg() && MO.getReg() == Reg && 311 (MO.isDef() || UseMI->isRegTiedToDefOperand(i))) 312 // Earlier use is a two-address one. 313 return true; 314 } 315 return false; 316} 317 318/// isProfitableToReMat - Return true if the heuristics determines it is likely 319/// to be profitable to re-materialize the definition of Reg rather than copy 320/// the register. 321bool 322TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg, 323 const TargetRegisterClass *RC, 324 MachineInstr *MI, MachineInstr *DefMI, 325 MachineBasicBlock *MBB, unsigned Loc) { 326 bool OtherUse = false; 327 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg), 328 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 329 MachineOperand &UseMO = UI.getOperand(); 330 MachineInstr *UseMI = UseMO.getParent(); 331 MachineBasicBlock *UseMBB = UseMI->getParent(); 332 if (UseMBB == MBB) { 333 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 334 if (DI != DistanceMap.end() && DI->second == Loc) 335 continue; // Current use. 336 OtherUse = true; 337 // There is at least one other use in the MBB that will clobber the 338 // register. 339 if (isTwoAddrUse(UseMI, Reg)) 340 return true; 341 } 342 } 343 344 // If other uses in MBB are not two-address uses, then don't remat. 345 if (OtherUse) 346 return false; 347 348 // No other uses in the same block, remat if it's defined in the same 349 // block so it does not unnecessarily extend the live range. 350 return MBB == DefMI->getParent(); 351} 352 353/// NoUseAfterLastDef - Return true if there are no intervening uses between the 354/// last instruction in the MBB that defines the specified register and the 355/// two-address instruction which is being processed. It also returns the last 356/// def location by reference 357bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg, 358 MachineBasicBlock *MBB, unsigned Dist, 359 unsigned &LastDef) { 360 LastDef = 0; 361 unsigned LastUse = Dist; 362 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), 363 E = MRI->reg_end(); I != E; ++I) { 364 MachineOperand &MO = I.getOperand(); 365 MachineInstr *MI = MO.getParent(); 366 if (MI->getParent() != MBB || MI->isDebugValue()) 367 continue; 368 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 369 if (DI == DistanceMap.end()) 370 continue; 371 if (MO.isUse() && DI->second < LastUse) 372 LastUse = DI->second; 373 if (MO.isDef() && DI->second > LastDef) 374 LastDef = DI->second; 375 } 376 377 return !(LastUse > LastDef && LastUse < Dist); 378} 379 380MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg, 381 MachineBasicBlock *MBB, 382 unsigned Dist) { 383 unsigned LastUseDist = 0; 384 MachineInstr *LastUse = 0; 385 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), 386 E = MRI->reg_end(); I != E; ++I) { 387 MachineOperand &MO = I.getOperand(); 388 MachineInstr *MI = MO.getParent(); 389 if (MI->getParent() != MBB || MI->isDebugValue()) 390 continue; 391 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 392 if (DI == DistanceMap.end()) 393 continue; 394 if (DI->second >= Dist) 395 continue; 396 397 if (MO.isUse() && DI->second > LastUseDist) { 398 LastUse = DI->first; 399 LastUseDist = DI->second; 400 } 401 } 402 return LastUse; 403} 404 405/// isCopyToReg - Return true if the specified MI is a copy instruction or 406/// a extract_subreg instruction. It also returns the source and destination 407/// registers and whether they are physical registers by reference. 408static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, 409 unsigned &SrcReg, unsigned &DstReg, 410 bool &IsSrcPhys, bool &IsDstPhys) { 411 SrcReg = 0; 412 DstReg = 0; 413 if (MI.isCopy()) { 414 DstReg = MI.getOperand(0).getReg(); 415 SrcReg = MI.getOperand(1).getReg(); 416 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) { 417 DstReg = MI.getOperand(0).getReg(); 418 SrcReg = MI.getOperand(2).getReg(); 419 } else 420 return false; 421 422 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); 423 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 424 return true; 425} 426 427/// isKilled - Test if the given register value, which is used by the given 428/// instruction, is killed by the given instruction. This looks through 429/// coalescable copies to see if the original value is potentially not killed. 430/// 431/// For example, in this code: 432/// 433/// %reg1034 = copy %reg1024 434/// %reg1035 = copy %reg1025<kill> 435/// %reg1036 = add %reg1034<kill>, %reg1035<kill> 436/// 437/// %reg1034 is not considered to be killed, since it is copied from a 438/// register which is not killed. Treating it as not killed lets the 439/// normal heuristics commute the (two-address) add, which lets 440/// coalescing eliminate the extra copy. 441/// 442static bool isKilled(MachineInstr &MI, unsigned Reg, 443 const MachineRegisterInfo *MRI, 444 const TargetInstrInfo *TII) { 445 MachineInstr *DefMI = &MI; 446 for (;;) { 447 if (!DefMI->killsRegister(Reg)) 448 return false; 449 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 450 return true; 451 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg); 452 // If there are multiple defs, we can't do a simple analysis, so just 453 // go with what the kill flag says. 454 if (llvm::next(Begin) != MRI->def_end()) 455 return true; 456 DefMI = &*Begin; 457 bool IsSrcPhys, IsDstPhys; 458 unsigned SrcReg, DstReg; 459 // If the def is something other than a copy, then it isn't going to 460 // be coalesced, so follow the kill flag. 461 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 462 return true; 463 Reg = SrcReg; 464 } 465} 466 467/// isTwoAddrUse - Return true if the specified MI uses the specified register 468/// as a two-address use. If so, return the destination register by reference. 469static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { 470 const MCInstrDesc &MCID = MI.getDesc(); 471 unsigned NumOps = MI.isInlineAsm() 472 ? MI.getNumOperands() : MCID.getNumOperands(); 473 for (unsigned i = 0; i != NumOps; ++i) { 474 const MachineOperand &MO = MI.getOperand(i); 475 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) 476 continue; 477 unsigned ti; 478 if (MI.isRegTiedToDefOperand(i, &ti)) { 479 DstReg = MI.getOperand(ti).getReg(); 480 return true; 481 } 482 } 483 return false; 484} 485 486/// findLocalKill - Look for an instruction below MI in the MBB that kills the 487/// specified register. Returns null if there are any other Reg use between the 488/// instructions. 489static 490MachineInstr *findLocalKill(unsigned Reg, MachineBasicBlock *MBB, 491 MachineInstr *MI, MachineRegisterInfo *MRI, 492 DenseMap<MachineInstr*, unsigned> &DistanceMap) { 493 MachineInstr *KillMI = 0; 494 for (MachineRegisterInfo::use_nodbg_iterator 495 UI = MRI->use_nodbg_begin(Reg), 496 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 497 MachineInstr *UseMI = &*UI; 498 if (UseMI == MI || UseMI->getParent() != MBB) 499 continue; 500 if (DistanceMap.count(UseMI)) 501 continue; 502 if (!UI.getOperand().isKill()) 503 return 0; 504 if (KillMI) 505 return 0; // -O0 kill markers cannot be trusted? 506 KillMI = UseMI; 507 } 508 509 return KillMI; 510} 511 512/// findOnlyInterestingUse - Given a register, if has a single in-basic block 513/// use, return the use instruction if it's a copy or a two-address use. 514static 515MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, 516 MachineRegisterInfo *MRI, 517 const TargetInstrInfo *TII, 518 bool &IsCopy, 519 unsigned &DstReg, bool &IsDstPhys) { 520 if (!MRI->hasOneNonDBGUse(Reg)) 521 // None or more than one use. 522 return 0; 523 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg); 524 if (UseMI.getParent() != MBB) 525 return 0; 526 unsigned SrcReg; 527 bool IsSrcPhys; 528 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) { 529 IsCopy = true; 530 return &UseMI; 531 } 532 IsDstPhys = false; 533 if (isTwoAddrUse(UseMI, Reg, DstReg)) { 534 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 535 return &UseMI; 536 } 537 return 0; 538} 539 540/// getMappedReg - Return the physical register the specified virtual register 541/// might be mapped to. 542static unsigned 543getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) { 544 while (TargetRegisterInfo::isVirtualRegister(Reg)) { 545 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg); 546 if (SI == RegMap.end()) 547 return 0; 548 Reg = SI->second; 549 } 550 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 551 return Reg; 552 return 0; 553} 554 555/// regsAreCompatible - Return true if the two registers are equal or aliased. 556/// 557static bool 558regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { 559 if (RegA == RegB) 560 return true; 561 if (!RegA || !RegB) 562 return false; 563 return TRI->regsOverlap(RegA, RegB); 564} 565 566 567/// isProfitableToReMat - Return true if it's potentially profitable to commute 568/// the two-address instruction that's being processed. 569bool 570TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC, 571 MachineInstr *MI, MachineBasicBlock *MBB, 572 unsigned Dist) { 573 if (OptLevel == CodeGenOpt::None) 574 return false; 575 576 // Determine if it's profitable to commute this two address instruction. In 577 // general, we want no uses between this instruction and the definition of 578 // the two-address register. 579 // e.g. 580 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 581 // %reg1029<def> = MOV8rr %reg1028 582 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 583 // insert => %reg1030<def> = MOV8rr %reg1028 584 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 585 // In this case, it might not be possible to coalesce the second MOV8rr 586 // instruction if the first one is coalesced. So it would be profitable to 587 // commute it: 588 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 589 // %reg1029<def> = MOV8rr %reg1028 590 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 591 // insert => %reg1030<def> = MOV8rr %reg1029 592 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead> 593 594 if (!MI->killsRegister(regC)) 595 return false; 596 597 // Ok, we have something like: 598 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 599 // let's see if it's worth commuting it. 600 601 // Look for situations like this: 602 // %reg1024<def> = MOV r1 603 // %reg1025<def> = MOV r0 604 // %reg1026<def> = ADD %reg1024, %reg1025 605 // r0 = MOV %reg1026 606 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy. 607 unsigned FromRegB = getMappedReg(regB, SrcRegMap); 608 unsigned FromRegC = getMappedReg(regC, SrcRegMap); 609 unsigned ToRegB = getMappedReg(regB, DstRegMap); 610 unsigned ToRegC = getMappedReg(regC, DstRegMap); 611 if ((FromRegB && ToRegB && !regsAreCompatible(FromRegB, ToRegB, TRI)) && 612 ((!FromRegC && !ToRegC) || 613 regsAreCompatible(FromRegB, ToRegC, TRI) || 614 regsAreCompatible(FromRegC, ToRegB, TRI))) 615 return true; 616 617 // If there is a use of regC between its last def (could be livein) and this 618 // instruction, then bail. 619 unsigned LastDefC = 0; 620 if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC)) 621 return false; 622 623 // If there is a use of regB between its last def (could be livein) and this 624 // instruction, then go ahead and make this transformation. 625 unsigned LastDefB = 0; 626 if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB)) 627 return true; 628 629 // Since there are no intervening uses for both registers, then commute 630 // if the def of regC is closer. Its live interval is shorter. 631 return LastDefB && LastDefC && LastDefC > LastDefB; 632} 633 634/// CommuteInstruction - Commute a two-address instruction and update the basic 635/// block, distance map, and live variables if needed. Return true if it is 636/// successful. 637bool 638TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi, 639 MachineFunction::iterator &mbbi, 640 unsigned RegB, unsigned RegC, unsigned Dist) { 641 MachineInstr *MI = mi; 642 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI); 643 MachineInstr *NewMI = TII->commuteInstruction(MI); 644 645 if (NewMI == 0) { 646 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n"); 647 return false; 648 } 649 650 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI); 651 // If the instruction changed to commute it, update livevar. 652 if (NewMI != MI) { 653 if (LV) 654 // Update live variables 655 LV->replaceKillInstruction(RegC, MI, NewMI); 656 657 mbbi->insert(mi, NewMI); // Insert the new inst 658 mbbi->erase(mi); // Nuke the old inst. 659 mi = NewMI; 660 DistanceMap.insert(std::make_pair(NewMI, Dist)); 661 } 662 663 // Update source register map. 664 unsigned FromRegC = getMappedReg(RegC, SrcRegMap); 665 if (FromRegC) { 666 unsigned RegA = MI->getOperand(0).getReg(); 667 SrcRegMap[RegA] = FromRegC; 668 } 669 670 return true; 671} 672 673/// isProfitableToConv3Addr - Return true if it is profitable to convert the 674/// given 2-address instruction to a 3-address one. 675bool 676TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){ 677 // Look for situations like this: 678 // %reg1024<def> = MOV r1 679 // %reg1025<def> = MOV r0 680 // %reg1026<def> = ADD %reg1024, %reg1025 681 // r2 = MOV %reg1026 682 // Turn ADD into a 3-address instruction to avoid a copy. 683 unsigned FromRegB = getMappedReg(RegB, SrcRegMap); 684 if (!FromRegB) 685 return false; 686 unsigned ToRegA = getMappedReg(RegA, DstRegMap); 687 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI)); 688} 689 690/// ConvertInstTo3Addr - Convert the specified two-address instruction into a 691/// three address one. Return true if this transformation was successful. 692bool 693TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi, 694 MachineBasicBlock::iterator &nmi, 695 MachineFunction::iterator &mbbi, 696 unsigned RegA, unsigned RegB, 697 unsigned Dist) { 698 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV); 699 if (NewMI) { 700 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi); 701 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI); 702 bool Sunk = false; 703 704 if (NewMI->findRegisterUseOperand(RegB, false, TRI)) 705 // FIXME: Temporary workaround. If the new instruction doesn't 706 // uses RegB, convertToThreeAddress must have created more 707 // then one instruction. 708 Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi); 709 710 mbbi->erase(mi); // Nuke the old inst. 711 712 if (!Sunk) { 713 DistanceMap.insert(std::make_pair(NewMI, Dist)); 714 mi = NewMI; 715 nmi = llvm::next(mi); 716 } 717 718 // Update source and destination register maps. 719 SrcRegMap.erase(RegA); 720 DstRegMap.erase(RegB); 721 return true; 722 } 723 724 return false; 725} 726 727/// ScanUses - Scan forward recursively for only uses, update maps if the use 728/// is a copy or a two-address instruction. 729void 730TwoAddressInstructionPass::ScanUses(unsigned DstReg, MachineBasicBlock *MBB, 731 SmallPtrSet<MachineInstr*, 8> &Processed) { 732 SmallVector<unsigned, 4> VirtRegPairs; 733 bool IsDstPhys; 734 bool IsCopy = false; 735 unsigned NewReg = 0; 736 unsigned Reg = DstReg; 737 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy, 738 NewReg, IsDstPhys)) { 739 if (IsCopy && !Processed.insert(UseMI)) 740 break; 741 742 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 743 if (DI != DistanceMap.end()) 744 // Earlier in the same MBB.Reached via a back edge. 745 break; 746 747 if (IsDstPhys) { 748 VirtRegPairs.push_back(NewReg); 749 break; 750 } 751 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second; 752 if (!isNew) 753 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!"); 754 VirtRegPairs.push_back(NewReg); 755 Reg = NewReg; 756 } 757 758 if (!VirtRegPairs.empty()) { 759 unsigned ToReg = VirtRegPairs.back(); 760 VirtRegPairs.pop_back(); 761 while (!VirtRegPairs.empty()) { 762 unsigned FromReg = VirtRegPairs.back(); 763 VirtRegPairs.pop_back(); 764 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second; 765 if (!isNew) 766 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!"); 767 ToReg = FromReg; 768 } 769 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second; 770 if (!isNew) 771 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!"); 772 } 773} 774 775/// ProcessCopy - If the specified instruction is not yet processed, process it 776/// if it's a copy. For a copy instruction, we find the physical registers the 777/// source and destination registers might be mapped to. These are kept in 778/// point-to maps used to determine future optimizations. e.g. 779/// v1024 = mov r0 780/// v1025 = mov r1 781/// v1026 = add v1024, v1025 782/// r1 = mov r1026 783/// If 'add' is a two-address instruction, v1024, v1026 are both potentially 784/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is 785/// potentially joined with r1 on the output side. It's worthwhile to commute 786/// 'add' to eliminate a copy. 787void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI, 788 MachineBasicBlock *MBB, 789 SmallPtrSet<MachineInstr*, 8> &Processed) { 790 if (Processed.count(MI)) 791 return; 792 793 bool IsSrcPhys, IsDstPhys; 794 unsigned SrcReg, DstReg; 795 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 796 return; 797 798 if (IsDstPhys && !IsSrcPhys) 799 DstRegMap.insert(std::make_pair(SrcReg, DstReg)); 800 else if (!IsDstPhys && IsSrcPhys) { 801 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second; 802 if (!isNew) 803 assert(SrcRegMap[DstReg] == SrcReg && 804 "Can't map to two src physical registers!"); 805 806 ScanUses(DstReg, MBB, Processed); 807 } 808 809 Processed.insert(MI); 810 return; 811} 812 813/// isSafeToDelete - If the specified instruction does not produce any side 814/// effects and all of its defs are dead, then it's safe to delete. 815static bool isSafeToDelete(MachineInstr *MI, 816 const TargetInstrInfo *TII, 817 SmallVector<unsigned, 4> &Kills) { 818 if (MI->mayStore() || MI->isCall()) 819 return false; 820 if (MI->isTerminator() || MI->hasUnmodeledSideEffects()) 821 return false; 822 823 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 824 MachineOperand &MO = MI->getOperand(i); 825 if (!MO.isReg()) 826 continue; 827 if (MO.isDef() && !MO.isDead()) 828 return false; 829 if (MO.isUse() && MO.isKill()) 830 Kills.push_back(MO.getReg()); 831 } 832 return true; 833} 834 835/// canUpdateDeletedKills - Check if all the registers listed in Kills are 836/// killed by instructions in MBB preceding the current instruction at 837/// position Dist. If so, return true and record information about the 838/// preceding kills in NewKills. 839bool TwoAddressInstructionPass:: 840canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills, 841 SmallVector<NewKill, 4> &NewKills, 842 MachineBasicBlock *MBB, unsigned Dist) { 843 while (!Kills.empty()) { 844 unsigned Kill = Kills.back(); 845 Kills.pop_back(); 846 if (TargetRegisterInfo::isPhysicalRegister(Kill)) 847 return false; 848 849 MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist); 850 if (!LastKill) 851 return false; 852 853 bool isModRef = LastKill->definesRegister(Kill); 854 NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef), 855 LastKill)); 856 } 857 return true; 858} 859 860/// DeleteUnusedInstr - If an instruction with a tied register operand can 861/// be safely deleted, just delete it. 862bool 863TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi, 864 MachineBasicBlock::iterator &nmi, 865 MachineFunction::iterator &mbbi, 866 unsigned Dist) { 867 // Check if the instruction has no side effects and if all its defs are dead. 868 SmallVector<unsigned, 4> Kills; 869 if (!isSafeToDelete(mi, TII, Kills)) 870 return false; 871 872 // If this instruction kills some virtual registers, we need to 873 // update the kill information. If it's not possible to do so, 874 // then bail out. 875 SmallVector<NewKill, 4> NewKills; 876 if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist)) 877 return false; 878 879 if (LV) { 880 while (!NewKills.empty()) { 881 MachineInstr *NewKill = NewKills.back().second; 882 unsigned Kill = NewKills.back().first.first; 883 bool isDead = NewKills.back().first.second; 884 NewKills.pop_back(); 885 if (LV->removeVirtualRegisterKilled(Kill, mi)) { 886 if (isDead) 887 LV->addVirtualRegisterDead(Kill, NewKill); 888 else 889 LV->addVirtualRegisterKilled(Kill, NewKill); 890 } 891 } 892 } 893 894 mbbi->erase(mi); // Nuke the old inst. 895 mi = nmi; 896 return true; 897} 898 899/// RescheduleMIBelowKill - If there is one more local instruction that reads 900/// 'Reg' and it kills 'Reg, consider moving the instruction below the kill 901/// instruction in order to eliminate the need for the copy. 902bool 903TwoAddressInstructionPass::RescheduleMIBelowKill(MachineBasicBlock *MBB, 904 MachineBasicBlock::iterator &mi, 905 MachineBasicBlock::iterator &nmi, 906 unsigned Reg) { 907 MachineInstr *MI = &*mi; 908 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 909 if (DI == DistanceMap.end()) 910 // Must be created from unfolded load. Don't waste time trying this. 911 return false; 912 913 MachineInstr *KillMI = findLocalKill(Reg, MBB, mi, MRI, DistanceMap); 914 if (!KillMI || KillMI->isCopy() || KillMI->isCopyLike()) 915 // Don't mess with copies, they may be coalesced later. 916 return false; 917 918 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() || 919 KillMI->isBranch() || KillMI->isTerminator()) 920 // Don't move pass calls, etc. 921 return false; 922 923 unsigned DstReg; 924 if (isTwoAddrUse(*KillMI, Reg, DstReg)) 925 return false; 926 927 bool SeenStore = true; 928 if (!MI->isSafeToMove(TII, AA, SeenStore)) 929 return false; 930 931 if (TII->getInstrLatency(InstrItins, MI) > 1) 932 // FIXME: Needs more sophisticated heuristics. 933 return false; 934 935 SmallSet<unsigned, 2> Uses; 936 SmallSet<unsigned, 2> Kills; 937 SmallSet<unsigned, 2> Defs; 938 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 939 const MachineOperand &MO = MI->getOperand(i); 940 if (!MO.isReg()) 941 continue; 942 unsigned MOReg = MO.getReg(); 943 if (!MOReg) 944 continue; 945 if (MO.isDef()) 946 Defs.insert(MOReg); 947 else { 948 Uses.insert(MOReg); 949 if (MO.isKill() && MOReg != Reg) 950 Kills.insert(MOReg); 951 } 952 } 953 954 // Move the copies connected to MI down as well. 955 MachineBasicBlock::iterator From = MI; 956 MachineBasicBlock::iterator To = llvm::next(From); 957 while (To->isCopy() && Defs.count(To->getOperand(1).getReg())) { 958 Defs.insert(To->getOperand(0).getReg()); 959 ++To; 960 } 961 962 // Check if the reschedule will not break depedencies. 963 unsigned NumVisited = 0; 964 MachineBasicBlock::iterator KillPos = KillMI; 965 ++KillPos; 966 for (MachineBasicBlock::iterator I = To; I != KillPos; ++I) { 967 MachineInstr *OtherMI = I; 968 // DBG_VALUE cannot be counted against the limit. 969 if (OtherMI->isDebugValue()) 970 continue; 971 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost. 972 return false; 973 ++NumVisited; 974 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() || 975 OtherMI->isBranch() || OtherMI->isTerminator()) 976 // Don't move pass calls, etc. 977 return false; 978 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { 979 const MachineOperand &MO = OtherMI->getOperand(i); 980 if (!MO.isReg()) 981 continue; 982 unsigned MOReg = MO.getReg(); 983 if (!MOReg) 984 continue; 985 if (MO.isDef()) { 986 if (Uses.count(MOReg)) 987 // Physical register use would be clobbered. 988 return false; 989 if (!MO.isDead() && Defs.count(MOReg)) 990 // May clobber a physical register def. 991 // FIXME: This may be too conservative. It's ok if the instruction 992 // is sunken completely below the use. 993 return false; 994 } else { 995 if (Defs.count(MOReg)) 996 return false; 997 if (MOReg != Reg && 998 ((MO.isKill() && Uses.count(MOReg)) || Kills.count(MOReg))) 999 // Don't want to extend other live ranges and update kills. 1000 return false; 1001 } 1002 } 1003 } 1004 1005 // Move debug info as well. 1006 while (From != MBB->begin() && llvm::prior(From)->isDebugValue()) 1007 --From; 1008 1009 // Copies following MI may have been moved as well. 1010 nmi = To; 1011 MBB->splice(KillPos, MBB, From, To); 1012 DistanceMap.erase(DI); 1013 1014 if (LV) { 1015 // Update live variables 1016 LV->removeVirtualRegisterKilled(Reg, KillMI); 1017 LV->addVirtualRegisterKilled(Reg, MI); 1018 } else { 1019 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) { 1020 MachineOperand &MO = KillMI->getOperand(i); 1021 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) 1022 continue; 1023 MO.setIsKill(false); 1024 } 1025 MI->addRegisterKilled(Reg, 0); 1026 } 1027 1028 return true; 1029} 1030 1031/// isDefTooClose - Return true if the re-scheduling will put the given 1032/// instruction too close to the defs of its register dependencies. 1033bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist, 1034 MachineInstr *MI, 1035 MachineBasicBlock *MBB) { 1036 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg), 1037 DE = MRI->def_end(); DI != DE; ++DI) { 1038 MachineInstr *DefMI = &*DI; 1039 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike()) 1040 continue; 1041 if (DefMI == MI) 1042 return true; // MI is defining something KillMI uses 1043 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI); 1044 if (DDI == DistanceMap.end()) 1045 return true; // Below MI 1046 unsigned DefDist = DDI->second; 1047 assert(Dist > DefDist && "Visited def already?"); 1048 if (TII->getInstrLatency(InstrItins, DefMI) > (int)(Dist - DefDist)) 1049 return true; 1050 } 1051 return false; 1052} 1053 1054/// RescheduleKillAboveMI - If there is one more local instruction that reads 1055/// 'Reg' and it kills 'Reg, consider moving the kill instruction above the 1056/// current two-address instruction in order to eliminate the need for the 1057/// copy. 1058bool 1059TwoAddressInstructionPass::RescheduleKillAboveMI(MachineBasicBlock *MBB, 1060 MachineBasicBlock::iterator &mi, 1061 MachineBasicBlock::iterator &nmi, 1062 unsigned Reg) { 1063 MachineInstr *MI = &*mi; 1064 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 1065 if (DI == DistanceMap.end()) 1066 // Must be created from unfolded load. Don't waste time trying this. 1067 return false; 1068 1069 MachineInstr *KillMI = findLocalKill(Reg, MBB, mi, MRI, DistanceMap); 1070 if (!KillMI || KillMI->isCopy() || KillMI->isCopyLike()) 1071 // Don't mess with copies, they may be coalesced later. 1072 return false; 1073 1074 unsigned DstReg; 1075 if (isTwoAddrUse(*KillMI, Reg, DstReg)) 1076 return false; 1077 1078 bool SeenStore = true; 1079 if (!KillMI->isSafeToMove(TII, AA, SeenStore)) 1080 return false; 1081 1082 SmallSet<unsigned, 2> Uses; 1083 SmallSet<unsigned, 2> Kills; 1084 SmallSet<unsigned, 2> Defs; 1085 SmallSet<unsigned, 2> LiveDefs; 1086 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) { 1087 const MachineOperand &MO = KillMI->getOperand(i); 1088 if (!MO.isReg()) 1089 continue; 1090 unsigned MOReg = MO.getReg(); 1091 if (MO.isUse()) { 1092 if (!MOReg) 1093 continue; 1094 if (isDefTooClose(MOReg, DI->second, MI, MBB)) 1095 return false; 1096 Uses.insert(MOReg); 1097 if (MO.isKill() && MOReg != Reg) 1098 Kills.insert(MOReg); 1099 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) { 1100 Defs.insert(MOReg); 1101 if (!MO.isDead()) 1102 LiveDefs.insert(MOReg); 1103 } 1104 } 1105 1106 // Check if the reschedule will not break depedencies. 1107 unsigned NumVisited = 0; 1108 MachineBasicBlock::iterator KillPos = KillMI; 1109 for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) { 1110 MachineInstr *OtherMI = I; 1111 // DBG_VALUE cannot be counted against the limit. 1112 if (OtherMI->isDebugValue()) 1113 continue; 1114 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost. 1115 return false; 1116 ++NumVisited; 1117 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() || 1118 OtherMI->isBranch() || OtherMI->isTerminator()) 1119 // Don't move pass calls, etc. 1120 return false; 1121 SmallVector<unsigned, 2> OtherDefs; 1122 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { 1123 const MachineOperand &MO = OtherMI->getOperand(i); 1124 if (!MO.isReg()) 1125 continue; 1126 unsigned MOReg = MO.getReg(); 1127 if (!MOReg) 1128 continue; 1129 if (MO.isUse()) { 1130 if (Defs.count(MOReg)) 1131 // Moving KillMI can clobber the physical register if the def has 1132 // not been seen. 1133 return false; 1134 if (Kills.count(MOReg)) 1135 // Don't want to extend other live ranges and update kills. 1136 return false; 1137 } else { 1138 OtherDefs.push_back(MOReg); 1139 } 1140 } 1141 1142 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) { 1143 unsigned MOReg = OtherDefs[i]; 1144 if (Uses.count(MOReg)) 1145 return false; 1146 if (TargetRegisterInfo::isPhysicalRegister(MOReg) && 1147 LiveDefs.count(MOReg)) 1148 return false; 1149 // Physical register def is seen. 1150 Defs.erase(MOReg); 1151 } 1152 } 1153 1154 // Move the old kill above MI, don't forget to move debug info as well. 1155 MachineBasicBlock::iterator InsertPos = mi; 1156 while (InsertPos != MBB->begin() && llvm::prior(InsertPos)->isDebugValue()) 1157 --InsertPos; 1158 MachineBasicBlock::iterator From = KillMI; 1159 MachineBasicBlock::iterator To = llvm::next(From); 1160 while (llvm::prior(From)->isDebugValue()) 1161 --From; 1162 MBB->splice(InsertPos, MBB, From, To); 1163 1164 nmi = llvm::prior(InsertPos); // Backtrack so we process the moved instr. 1165 DistanceMap.erase(DI); 1166 1167 if (LV) { 1168 // Update live variables 1169 LV->removeVirtualRegisterKilled(Reg, KillMI); 1170 LV->addVirtualRegisterKilled(Reg, MI); 1171 } else { 1172 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) { 1173 MachineOperand &MO = KillMI->getOperand(i); 1174 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) 1175 continue; 1176 MO.setIsKill(false); 1177 } 1178 MI->addRegisterKilled(Reg, 0); 1179 } 1180 return true; 1181} 1182 1183/// TryInstructionTransform - For the case where an instruction has a single 1184/// pair of tied register operands, attempt some transformations that may 1185/// either eliminate the tied operands or improve the opportunities for 1186/// coalescing away the register copy. Returns true if the tied operands 1187/// are eliminated altogether. 1188bool TwoAddressInstructionPass:: 1189TryInstructionTransform(MachineBasicBlock::iterator &mi, 1190 MachineBasicBlock::iterator &nmi, 1191 MachineFunction::iterator &mbbi, 1192 unsigned SrcIdx, unsigned DstIdx, unsigned Dist, 1193 SmallPtrSet<MachineInstr*, 8> &Processed) { 1194 if (OptLevel == CodeGenOpt::None) 1195 return false; 1196 1197 MachineInstr &MI = *mi; 1198 unsigned regA = MI.getOperand(DstIdx).getReg(); 1199 unsigned regB = MI.getOperand(SrcIdx).getReg(); 1200 1201 assert(TargetRegisterInfo::isVirtualRegister(regB) && 1202 "cannot make instruction into two-address form"); 1203 1204 // If regA is dead and the instruction can be deleted, just delete 1205 // it so it doesn't clobber regB. 1206 bool regBKilled = isKilled(MI, regB, MRI, TII); 1207 if (!regBKilled && MI.getOperand(DstIdx).isDead() && 1208 DeleteUnusedInstr(mi, nmi, mbbi, Dist)) { 1209 ++NumDeletes; 1210 return true; // Done with this instruction. 1211 } 1212 1213 // Check if it is profitable to commute the operands. 1214 unsigned SrcOp1, SrcOp2; 1215 unsigned regC = 0; 1216 unsigned regCIdx = ~0U; 1217 bool TryCommute = false; 1218 bool AggressiveCommute = false; 1219 if (MI.isCommutable() && MI.getNumOperands() >= 3 && 1220 TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) { 1221 if (SrcIdx == SrcOp1) 1222 regCIdx = SrcOp2; 1223 else if (SrcIdx == SrcOp2) 1224 regCIdx = SrcOp1; 1225 1226 if (regCIdx != ~0U) { 1227 regC = MI.getOperand(regCIdx).getReg(); 1228 if (!regBKilled && isKilled(MI, regC, MRI, TII)) 1229 // If C dies but B does not, swap the B and C operands. 1230 // This makes the live ranges of A and C joinable. 1231 TryCommute = true; 1232 else if (isProfitableToCommute(regB, regC, &MI, mbbi, Dist)) { 1233 TryCommute = true; 1234 AggressiveCommute = true; 1235 } 1236 } 1237 } 1238 1239 // If it's profitable to commute, try to do so. 1240 if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) { 1241 ++NumCommuted; 1242 if (AggressiveCommute) 1243 ++NumAggrCommuted; 1244 return false; 1245 } 1246 1247 // If there is one more use of regB later in the same MBB, consider 1248 // re-schedule this MI below it. 1249 if (RescheduleMIBelowKill(mbbi, mi, nmi, regB)) { 1250 ++NumReSchedDowns; 1251 return false; 1252 } 1253 1254 if (TargetRegisterInfo::isVirtualRegister(regA)) 1255 ScanUses(regA, &*mbbi, Processed); 1256 1257 if (MI.isConvertibleTo3Addr()) { 1258 // This instruction is potentially convertible to a true 1259 // three-address instruction. Check if it is profitable. 1260 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) { 1261 // Try to convert it. 1262 if (ConvertInstTo3Addr(mi, nmi, mbbi, regA, regB, Dist)) { 1263 ++NumConvertedTo3Addr; 1264 return true; // Done with this instruction. 1265 } 1266 } 1267 } 1268 1269 // If there is one more use of regB later in the same MBB, consider 1270 // re-schedule it before this MI if it's legal. 1271 if (RescheduleKillAboveMI(mbbi, mi, nmi, regB)) { 1272 ++NumReSchedUps; 1273 return false; 1274 } 1275 1276 // If this is an instruction with a load folded into it, try unfolding 1277 // the load, e.g. avoid this: 1278 // movq %rdx, %rcx 1279 // addq (%rax), %rcx 1280 // in favor of this: 1281 // movq (%rax), %rcx 1282 // addq %rdx, %rcx 1283 // because it's preferable to schedule a load than a register copy. 1284 if (MI.mayLoad() && !regBKilled) { 1285 // Determine if a load can be unfolded. 1286 unsigned LoadRegIndex; 1287 unsigned NewOpc = 1288 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), 1289 /*UnfoldLoad=*/true, 1290 /*UnfoldStore=*/false, 1291 &LoadRegIndex); 1292 if (NewOpc != 0) { 1293 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc); 1294 if (UnfoldMCID.getNumDefs() == 1) { 1295 MachineFunction &MF = *mbbi->getParent(); 1296 1297 // Unfold the load. 1298 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI); 1299 const TargetRegisterClass *RC = 1300 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI); 1301 unsigned Reg = MRI->createVirtualRegister(RC); 1302 SmallVector<MachineInstr *, 2> NewMIs; 1303 if (!TII->unfoldMemoryOperand(MF, &MI, Reg, 1304 /*UnfoldLoad=*/true,/*UnfoldStore=*/false, 1305 NewMIs)) { 1306 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); 1307 return false; 1308 } 1309 assert(NewMIs.size() == 2 && 1310 "Unfolded a load into multiple instructions!"); 1311 // The load was previously folded, so this is the only use. 1312 NewMIs[1]->addRegisterKilled(Reg, TRI); 1313 1314 // Tentatively insert the instructions into the block so that they 1315 // look "normal" to the transformation logic. 1316 mbbi->insert(mi, NewMIs[0]); 1317 mbbi->insert(mi, NewMIs[1]); 1318 1319 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] 1320 << "2addr: NEW INST: " << *NewMIs[1]); 1321 1322 // Transform the instruction, now that it no longer has a load. 1323 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); 1324 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); 1325 MachineBasicBlock::iterator NewMI = NewMIs[1]; 1326 bool TransformSuccess = 1327 TryInstructionTransform(NewMI, mi, mbbi, 1328 NewSrcIdx, NewDstIdx, Dist, Processed); 1329 if (TransformSuccess || 1330 NewMIs[1]->getOperand(NewSrcIdx).isKill()) { 1331 // Success, or at least we made an improvement. Keep the unfolded 1332 // instructions and discard the original. 1333 if (LV) { 1334 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 1335 MachineOperand &MO = MI.getOperand(i); 1336 if (MO.isReg() && 1337 TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 1338 if (MO.isUse()) { 1339 if (MO.isKill()) { 1340 if (NewMIs[0]->killsRegister(MO.getReg())) 1341 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]); 1342 else { 1343 assert(NewMIs[1]->killsRegister(MO.getReg()) && 1344 "Kill missing after load unfold!"); 1345 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]); 1346 } 1347 } 1348 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) { 1349 if (NewMIs[1]->registerDefIsDead(MO.getReg())) 1350 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]); 1351 else { 1352 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) && 1353 "Dead flag missing after load unfold!"); 1354 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]); 1355 } 1356 } 1357 } 1358 } 1359 LV->addVirtualRegisterKilled(Reg, NewMIs[1]); 1360 } 1361 MI.eraseFromParent(); 1362 mi = NewMIs[1]; 1363 if (TransformSuccess) 1364 return true; 1365 } else { 1366 // Transforming didn't eliminate the tie and didn't lead to an 1367 // improvement. Clean up the unfolded instructions and keep the 1368 // original. 1369 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); 1370 NewMIs[0]->eraseFromParent(); 1371 NewMIs[1]->eraseFromParent(); 1372 } 1373 } 1374 } 1375 } 1376 1377 return false; 1378} 1379 1380/// runOnMachineFunction - Reduce two-address instructions to two operands. 1381/// 1382bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { 1383 const TargetMachine &TM = MF.getTarget(); 1384 MRI = &MF.getRegInfo(); 1385 TII = TM.getInstrInfo(); 1386 TRI = TM.getRegisterInfo(); 1387 InstrItins = TM.getInstrItineraryData(); 1388 LV = getAnalysisIfAvailable<LiveVariables>(); 1389 AA = &getAnalysis<AliasAnalysis>(); 1390 OptLevel = TM.getOptLevel(); 1391 1392 bool MadeChange = false; 1393 1394 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n"); 1395 DEBUG(dbgs() << "********** Function: " 1396 << MF.getFunction()->getName() << '\n'); 1397 1398 // This pass takes the function out of SSA form. 1399 MRI->leaveSSA(); 1400 1401 // ReMatRegs - Keep track of the registers whose def's are remat'ed. 1402 BitVector ReMatRegs(MRI->getNumVirtRegs()); 1403 1404 typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> > 1405 TiedOperandMap; 1406 TiedOperandMap TiedOperands(4); 1407 1408 SmallPtrSet<MachineInstr*, 8> Processed; 1409 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); 1410 mbbi != mbbe; ++mbbi) { 1411 unsigned Dist = 0; 1412 DistanceMap.clear(); 1413 SrcRegMap.clear(); 1414 DstRegMap.clear(); 1415 Processed.clear(); 1416 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); 1417 mi != me; ) { 1418 MachineBasicBlock::iterator nmi = llvm::next(mi); 1419 if (mi->isDebugValue()) { 1420 mi = nmi; 1421 continue; 1422 } 1423 1424 // Remember REG_SEQUENCE instructions, we'll deal with them later. 1425 if (mi->isRegSequence()) 1426 RegSequences.push_back(&*mi); 1427 1428 const MCInstrDesc &MCID = mi->getDesc(); 1429 bool FirstTied = true; 1430 1431 DistanceMap.insert(std::make_pair(mi, ++Dist)); 1432 1433 ProcessCopy(&*mi, &*mbbi, Processed); 1434 1435 // First scan through all the tied register uses in this instruction 1436 // and record a list of pairs of tied operands for each register. 1437 unsigned NumOps = mi->isInlineAsm() 1438 ? mi->getNumOperands() : MCID.getNumOperands(); 1439 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { 1440 unsigned DstIdx = 0; 1441 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx)) 1442 continue; 1443 1444 if (FirstTied) { 1445 FirstTied = false; 1446 ++NumTwoAddressInstrs; 1447 DEBUG(dbgs() << '\t' << *mi); 1448 } 1449 1450 assert(mi->getOperand(SrcIdx).isReg() && 1451 mi->getOperand(SrcIdx).getReg() && 1452 mi->getOperand(SrcIdx).isUse() && 1453 "two address instruction invalid"); 1454 1455 unsigned regB = mi->getOperand(SrcIdx).getReg(); 1456 TiedOperands[regB].push_back(std::make_pair(SrcIdx, DstIdx)); 1457 } 1458 1459 // Now iterate over the information collected above. 1460 for (TiedOperandMap::iterator OI = TiedOperands.begin(), 1461 OE = TiedOperands.end(); OI != OE; ++OI) { 1462 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second; 1463 1464 // If the instruction has a single pair of tied operands, try some 1465 // transformations that may either eliminate the tied operands or 1466 // improve the opportunities for coalescing away the register copy. 1467 if (TiedOperands.size() == 1 && TiedPairs.size() == 1) { 1468 unsigned SrcIdx = TiedPairs[0].first; 1469 unsigned DstIdx = TiedPairs[0].second; 1470 1471 // If the registers are already equal, nothing needs to be done. 1472 if (mi->getOperand(SrcIdx).getReg() == 1473 mi->getOperand(DstIdx).getReg()) 1474 break; // Done with this instruction. 1475 1476 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist, 1477 Processed)) 1478 break; // The tied operands have been eliminated. 1479 } 1480 1481 bool IsEarlyClobber = false; 1482 bool RemovedKillFlag = false; 1483 bool AllUsesCopied = true; 1484 unsigned LastCopiedReg = 0; 1485 unsigned regB = OI->first; 1486 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) { 1487 unsigned SrcIdx = TiedPairs[tpi].first; 1488 unsigned DstIdx = TiedPairs[tpi].second; 1489 1490 const MachineOperand &DstMO = mi->getOperand(DstIdx); 1491 unsigned regA = DstMO.getReg(); 1492 IsEarlyClobber |= DstMO.isEarlyClobber(); 1493 1494 // Grab regB from the instruction because it may have changed if the 1495 // instruction was commuted. 1496 regB = mi->getOperand(SrcIdx).getReg(); 1497 1498 if (regA == regB) { 1499 // The register is tied to multiple destinations (or else we would 1500 // not have continued this far), but this use of the register 1501 // already matches the tied destination. Leave it. 1502 AllUsesCopied = false; 1503 continue; 1504 } 1505 LastCopiedReg = regA; 1506 1507 assert(TargetRegisterInfo::isVirtualRegister(regB) && 1508 "cannot make instruction into two-address form"); 1509 1510#ifndef NDEBUG 1511 // First, verify that we don't have a use of "a" in the instruction 1512 // (a = b + a for example) because our transformation will not 1513 // work. This should never occur because we are in SSA form. 1514 for (unsigned i = 0; i != mi->getNumOperands(); ++i) 1515 assert(i == DstIdx || 1516 !mi->getOperand(i).isReg() || 1517 mi->getOperand(i).getReg() != regA); 1518#endif 1519 1520 // Emit a copy or rematerialize the definition. 1521 const TargetRegisterClass *rc = MRI->getRegClass(regB); 1522 MachineInstr *DefMI = MRI->getVRegDef(regB); 1523 // If it's safe and profitable, remat the definition instead of 1524 // copying it. 1525 if (DefMI && 1526 DefMI->isAsCheapAsAMove() && 1527 DefMI->isSafeToReMat(TII, AA, regB) && 1528 isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){ 1529 DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n"); 1530 unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg(); 1531 TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI); 1532 ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB)); 1533 ++NumReMats; 1534 } else { 1535 BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY), 1536 regA).addReg(regB); 1537 } 1538 1539 MachineBasicBlock::iterator prevMI = prior(mi); 1540 // Update DistanceMap. 1541 DistanceMap.insert(std::make_pair(prevMI, Dist)); 1542 DistanceMap[mi] = ++Dist; 1543 1544 DEBUG(dbgs() << "\t\tprepend:\t" << *prevMI); 1545 1546 MachineOperand &MO = mi->getOperand(SrcIdx); 1547 assert(MO.isReg() && MO.getReg() == regB && MO.isUse() && 1548 "inconsistent operand info for 2-reg pass"); 1549 if (MO.isKill()) { 1550 MO.setIsKill(false); 1551 RemovedKillFlag = true; 1552 } 1553 MO.setReg(regA); 1554 } 1555 1556 if (AllUsesCopied) { 1557 if (!IsEarlyClobber) { 1558 // Replace other (un-tied) uses of regB with LastCopiedReg. 1559 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { 1560 MachineOperand &MO = mi->getOperand(i); 1561 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) { 1562 if (MO.isKill()) { 1563 MO.setIsKill(false); 1564 RemovedKillFlag = true; 1565 } 1566 MO.setReg(LastCopiedReg); 1567 } 1568 } 1569 } 1570 1571 // Update live variables for regB. 1572 if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi)) 1573 LV->addVirtualRegisterKilled(regB, prior(mi)); 1574 1575 } else if (RemovedKillFlag) { 1576 // Some tied uses of regB matched their destination registers, so 1577 // regB is still used in this instruction, but a kill flag was 1578 // removed from a different tied use of regB, so now we need to add 1579 // a kill flag to one of the remaining uses of regB. 1580 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { 1581 MachineOperand &MO = mi->getOperand(i); 1582 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) { 1583 MO.setIsKill(true); 1584 break; 1585 } 1586 } 1587 } 1588 1589 // Schedule the source copy / remat inserted to form two-address 1590 // instruction. FIXME: Does it matter the distance map may not be 1591 // accurate after it's scheduled? 1592 TII->scheduleTwoAddrSource(prior(mi), mi, *TRI); 1593 1594 MadeChange = true; 1595 1596 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi); 1597 } 1598 1599 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form. 1600 if (mi->isInsertSubreg()) { 1601 // From %reg = INSERT_SUBREG %reg, %subreg, subidx 1602 // To %reg:subidx = COPY %subreg 1603 unsigned SubIdx = mi->getOperand(3).getImm(); 1604 mi->RemoveOperand(3); 1605 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx"); 1606 mi->getOperand(0).setSubReg(SubIdx); 1607 mi->RemoveOperand(1); 1608 mi->setDesc(TII->get(TargetOpcode::COPY)); 1609 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi); 1610 } 1611 1612 // Clear TiedOperands here instead of at the top of the loop 1613 // since most instructions do not have tied operands. 1614 TiedOperands.clear(); 1615 mi = nmi; 1616 } 1617 } 1618 1619 // Some remat'ed instructions are dead. 1620 for (int i = ReMatRegs.find_first(); i != -1; i = ReMatRegs.find_next(i)) { 1621 unsigned VReg = TargetRegisterInfo::index2VirtReg(i); 1622 if (MRI->use_nodbg_empty(VReg)) { 1623 MachineInstr *DefMI = MRI->getVRegDef(VReg); 1624 DefMI->eraseFromParent(); 1625 } 1626 } 1627 1628 // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve 1629 // SSA form. It's now safe to de-SSA. 1630 MadeChange |= EliminateRegSequences(); 1631 1632 return MadeChange; 1633} 1634 1635static void UpdateRegSequenceSrcs(unsigned SrcReg, 1636 unsigned DstReg, unsigned SubIdx, 1637 MachineRegisterInfo *MRI, 1638 const TargetRegisterInfo &TRI) { 1639 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg), 1640 RE = MRI->reg_end(); RI != RE; ) { 1641 MachineOperand &MO = RI.getOperand(); 1642 ++RI; 1643 MO.substVirtReg(DstReg, SubIdx, TRI); 1644 } 1645} 1646 1647// Find the first def of Reg, assuming they are all in the same basic block. 1648static MachineInstr *findFirstDef(unsigned Reg, MachineRegisterInfo *MRI) { 1649 SmallPtrSet<MachineInstr*, 8> Defs; 1650 MachineInstr *First = 0; 1651 for (MachineRegisterInfo::def_iterator RI = MRI->def_begin(Reg); 1652 MachineInstr *MI = RI.skipInstruction(); Defs.insert(MI)) 1653 First = MI; 1654 if (!First) 1655 return 0; 1656 1657 MachineBasicBlock *MBB = First->getParent(); 1658 MachineBasicBlock::iterator A = First, B = First; 1659 bool Moving; 1660 do { 1661 Moving = false; 1662 if (A != MBB->begin()) { 1663 Moving = true; 1664 --A; 1665 if (Defs.erase(A)) First = A; 1666 } 1667 if (B != MBB->end()) { 1668 Defs.erase(B); 1669 ++B; 1670 Moving = true; 1671 } 1672 } while (Moving && !Defs.empty()); 1673 assert(Defs.empty() && "Instructions outside basic block!"); 1674 return First; 1675} 1676 1677/// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are 1678/// EXTRACT_SUBREG from the same register and to the same virtual register 1679/// with different sub-register indices, attempt to combine the 1680/// EXTRACT_SUBREGs and pre-coalesce them. e.g. 1681/// %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 1682/// %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6 1683/// %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5 1684/// Since D subregs 5, 6 can combine to a Q register, we can coalesce 1685/// reg1026 to reg1029. 1686void 1687TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, 1688 unsigned DstReg) { 1689 SmallSet<unsigned, 4> Seen; 1690 for (unsigned i = 0, e = Srcs.size(); i != e; ++i) { 1691 unsigned SrcReg = Srcs[i]; 1692 if (!Seen.insert(SrcReg)) 1693 continue; 1694 1695 // Check that the instructions are all in the same basic block. 1696 MachineInstr *SrcDefMI = MRI->getVRegDef(SrcReg); 1697 MachineInstr *DstDefMI = MRI->getVRegDef(DstReg); 1698 if (SrcDefMI->getParent() != DstDefMI->getParent()) 1699 continue; 1700 1701 // If there are no other uses than copies which feed into 1702 // the reg_sequence, then we might be able to coalesce them. 1703 bool CanCoalesce = true; 1704 SmallVector<unsigned, 4> SrcSubIndices, DstSubIndices; 1705 for (MachineRegisterInfo::use_nodbg_iterator 1706 UI = MRI->use_nodbg_begin(SrcReg), 1707 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 1708 MachineInstr *UseMI = &*UI; 1709 if (!UseMI->isCopy() || UseMI->getOperand(0).getReg() != DstReg) { 1710 CanCoalesce = false; 1711 break; 1712 } 1713 SrcSubIndices.push_back(UseMI->getOperand(1).getSubReg()); 1714 DstSubIndices.push_back(UseMI->getOperand(0).getSubReg()); 1715 } 1716 1717 if (!CanCoalesce || SrcSubIndices.size() < 2) 1718 continue; 1719 1720 // Check that the source subregisters can be combined. 1721 std::sort(SrcSubIndices.begin(), SrcSubIndices.end()); 1722 unsigned NewSrcSubIdx = 0; 1723 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices, 1724 NewSrcSubIdx)) 1725 continue; 1726 1727 // Check that the destination subregisters can also be combined. 1728 std::sort(DstSubIndices.begin(), DstSubIndices.end()); 1729 unsigned NewDstSubIdx = 0; 1730 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices, 1731 NewDstSubIdx)) 1732 continue; 1733 1734 // If neither source nor destination can be combined to the full register, 1735 // just give up. This could be improved if it ever matters. 1736 if (NewSrcSubIdx != 0 && NewDstSubIdx != 0) 1737 continue; 1738 1739 // Now that we know that all the uses are extract_subregs and that those 1740 // subregs can somehow be combined, scan all the extract_subregs again to 1741 // make sure the subregs are in the right order and can be composed. 1742 MachineInstr *SomeMI = 0; 1743 CanCoalesce = true; 1744 for (MachineRegisterInfo::use_nodbg_iterator 1745 UI = MRI->use_nodbg_begin(SrcReg), 1746 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 1747 MachineInstr *UseMI = &*UI; 1748 assert(UseMI->isCopy()); 1749 unsigned DstSubIdx = UseMI->getOperand(0).getSubReg(); 1750 unsigned SrcSubIdx = UseMI->getOperand(1).getSubReg(); 1751 assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination"); 1752 if ((NewDstSubIdx == 0 && 1753 TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) || 1754 (NewSrcSubIdx == 0 && 1755 TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) { 1756 CanCoalesce = false; 1757 break; 1758 } 1759 // Keep track of one of the uses. Preferably the first one which has a 1760 // <def,undef> flag. 1761 if (!SomeMI || UseMI->getOperand(0).isUndef()) 1762 SomeMI = UseMI; 1763 } 1764 if (!CanCoalesce) 1765 continue; 1766 1767 // Insert a copy to replace the original. 1768 MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI, 1769 SomeMI->getDebugLoc(), 1770 TII->get(TargetOpcode::COPY)) 1771 .addReg(DstReg, RegState::Define | 1772 getUndefRegState(SomeMI->getOperand(0).isUndef()), 1773 NewDstSubIdx) 1774 .addReg(SrcReg, 0, NewSrcSubIdx); 1775 1776 // Remove all the old extract instructions. 1777 for (MachineRegisterInfo::use_nodbg_iterator 1778 UI = MRI->use_nodbg_begin(SrcReg), 1779 UE = MRI->use_nodbg_end(); UI != UE; ) { 1780 MachineInstr *UseMI = &*UI; 1781 ++UI; 1782 if (UseMI == CopyMI) 1783 continue; 1784 assert(UseMI->isCopy()); 1785 // Move any kills to the new copy or extract instruction. 1786 if (UseMI->getOperand(1).isKill()) { 1787 CopyMI->getOperand(1).setIsKill(); 1788 if (LV) 1789 // Update live variables 1790 LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI); 1791 } 1792 UseMI->eraseFromParent(); 1793 } 1794 } 1795} 1796 1797static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq, 1798 MachineRegisterInfo *MRI) { 1799 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg), 1800 UE = MRI->use_end(); UI != UE; ++UI) { 1801 MachineInstr *UseMI = &*UI; 1802 if (UseMI != RegSeq && UseMI->isRegSequence()) 1803 return true; 1804 } 1805 return false; 1806} 1807 1808/// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part 1809/// of the de-ssa process. This replaces sources of REG_SEQUENCE as 1810/// sub-register references of the register defined by REG_SEQUENCE. e.g. 1811/// 1812/// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ... 1813/// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6 1814/// => 1815/// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ... 1816bool TwoAddressInstructionPass::EliminateRegSequences() { 1817 if (RegSequences.empty()) 1818 return false; 1819 1820 for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) { 1821 MachineInstr *MI = RegSequences[i]; 1822 unsigned DstReg = MI->getOperand(0).getReg(); 1823 if (MI->getOperand(0).getSubReg() || 1824 TargetRegisterInfo::isPhysicalRegister(DstReg) || 1825 !(MI->getNumOperands() & 1)) { 1826 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI); 1827 llvm_unreachable(0); 1828 } 1829 1830 bool IsImpDef = true; 1831 SmallVector<unsigned, 4> RealSrcs; 1832 SmallSet<unsigned, 4> Seen; 1833 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { 1834 unsigned SrcReg = MI->getOperand(i).getReg(); 1835 unsigned SubIdx = MI->getOperand(i+1).getImm(); 1836 // DefMI of NULL means the value does not have a vreg in this block 1837 // i.e., its a physical register or a subreg. 1838 // In either case we force a copy to be generated. 1839 MachineInstr *DefMI = NULL; 1840 if (!MI->getOperand(i).getSubReg() && 1841 !TargetRegisterInfo::isPhysicalRegister(SrcReg)) { 1842 DefMI = MRI->getVRegDef(SrcReg); 1843 } 1844 1845 if (DefMI && DefMI->isImplicitDef()) { 1846 DefMI->eraseFromParent(); 1847 continue; 1848 } 1849 IsImpDef = false; 1850 1851 // Remember COPY sources. These might be candidate for coalescing. 1852 if (DefMI && DefMI->isCopy() && DefMI->getOperand(1).getSubReg()) 1853 RealSrcs.push_back(DefMI->getOperand(1).getReg()); 1854 1855 bool isKill = MI->getOperand(i).isKill(); 1856 if (!DefMI || !Seen.insert(SrcReg) || 1857 MI->getParent() != DefMI->getParent() || 1858 !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI) || 1859 !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg), 1860 MRI->getRegClass(SrcReg), SubIdx)) { 1861 // REG_SEQUENCE cannot have duplicated operands, add a copy. 1862 // Also add an copy if the source is live-in the block. We don't want 1863 // to end up with a partial-redef of a livein, e.g. 1864 // BB0: 1865 // reg1051:10<def> = 1866 // ... 1867 // BB1: 1868 // ... = reg1051:10 1869 // BB2: 1870 // reg1051:9<def> = 1871 // LiveIntervalAnalysis won't like it. 1872 // 1873 // If the REG_SEQUENCE doesn't kill its source, keeping live variables 1874 // correctly up to date becomes very difficult. Insert a copy. 1875 1876 // Defer any kill flag to the last operand using SrcReg. Otherwise, we 1877 // might insert a COPY that uses SrcReg after is was killed. 1878 if (isKill) 1879 for (unsigned j = i + 2; j < e; j += 2) 1880 if (MI->getOperand(j).getReg() == SrcReg) { 1881 MI->getOperand(j).setIsKill(); 1882 isKill = false; 1883 break; 1884 } 1885 1886 MachineBasicBlock::iterator InsertLoc = MI; 1887 MachineInstr *CopyMI = BuildMI(*MI->getParent(), InsertLoc, 1888 MI->getDebugLoc(), TII->get(TargetOpcode::COPY)) 1889 .addReg(DstReg, RegState::Define, SubIdx) 1890 .addReg(SrcReg, getKillRegState(isKill)); 1891 MI->getOperand(i).setReg(0); 1892 if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg)) 1893 LV->replaceKillInstruction(SrcReg, MI, CopyMI); 1894 DEBUG(dbgs() << "Inserted: " << *CopyMI); 1895 } 1896 } 1897 1898 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { 1899 unsigned SrcReg = MI->getOperand(i).getReg(); 1900 if (!SrcReg) continue; 1901 unsigned SubIdx = MI->getOperand(i+1).getImm(); 1902 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI); 1903 } 1904 1905 // Set <def,undef> flags on the first DstReg def in the basic block. 1906 // It marks the beginning of the live range. All the other defs are 1907 // read-modify-write. 1908 if (MachineInstr *Def = findFirstDef(DstReg, MRI)) { 1909 for (unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) { 1910 MachineOperand &MO = Def->getOperand(i); 1911 if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg) 1912 MO.setIsUndef(); 1913 } 1914 // Make sure there is a full non-subreg imp-def operand on the 1915 // instruction. This shouldn't be necessary, but it seems that at least 1916 // RAFast requires it. 1917 Def->addRegisterDefined(DstReg, TRI); 1918 DEBUG(dbgs() << "First def: " << *Def); 1919 } 1920 1921 if (IsImpDef) { 1922 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF"); 1923 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); 1924 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j) 1925 MI->RemoveOperand(j); 1926 } else { 1927 DEBUG(dbgs() << "Eliminated: " << *MI); 1928 MI->eraseFromParent(); 1929 } 1930 1931 // Try coalescing some EXTRACT_SUBREG instructions. This can create 1932 // INSERT_SUBREG instructions that must have <undef> flags added by 1933 // LiveIntervalAnalysis, so only run it when LiveVariables is available. 1934 if (LV) 1935 CoalesceExtSubRegs(RealSrcs, DstReg); 1936 } 1937 1938 RegSequences.clear(); 1939 return true; 1940} 1941