TwoAddressInstructionPass.cpp revision b8ff934e94637462901ebd1c849aeaf71350dacc
1//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the TwoAddress instruction pass which is used 11// by most register allocators. Two-Address instructions are rewritten 12// from: 13// 14// A = B op C 15// 16// to: 17// 18// A = B 19// A op= C 20// 21// Note that if a register allocator chooses to use this pass, that it 22// has to be capable of handling the non-SSA nature of these rewritten 23// virtual registers. 24// 25// It is also worth noting that the duplicate operand of the two 26// address instruction is removed. 27// 28//===----------------------------------------------------------------------===// 29 30#define DEBUG_TYPE "twoaddrinstr" 31#include "llvm/CodeGen/Passes.h" 32#include "llvm/Function.h" 33#include "llvm/CodeGen/LiveVariables.h" 34#include "llvm/CodeGen/MachineFunctionPass.h" 35#include "llvm/CodeGen/MachineInstr.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/Analysis/AliasAnalysis.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include "llvm/Target/TargetInstrInfo.h" 40#include "llvm/Target/TargetMachine.h" 41#include "llvm/Target/TargetOptions.h" 42#include "llvm/Support/Debug.h" 43#include "llvm/ADT/BitVector.h" 44#include "llvm/ADT/DenseMap.h" 45#include "llvm/ADT/SmallSet.h" 46#include "llvm/ADT/Statistic.h" 47#include "llvm/ADT/STLExtras.h" 48using namespace llvm; 49 50STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions"); 51STATISTIC(NumCommuted , "Number of instructions commuted to coalesce"); 52STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted"); 53STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address"); 54STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk"); 55STATISTIC(NumReMats, "Number of instructions re-materialized"); 56STATISTIC(NumDeletes, "Number of dead instructions deleted"); 57 58namespace { 59 class TwoAddressInstructionPass : public MachineFunctionPass { 60 const TargetInstrInfo *TII; 61 const TargetRegisterInfo *TRI; 62 MachineRegisterInfo *MRI; 63 LiveVariables *LV; 64 AliasAnalysis *AA; 65 66 // DistanceMap - Keep track the distance of a MI from the start of the 67 // current basic block. 68 DenseMap<MachineInstr*, unsigned> DistanceMap; 69 70 // SrcRegMap - A map from virtual registers to physical registers which 71 // are likely targets to be coalesced to due to copies from physical 72 // registers to virtual registers. e.g. v1024 = move r0. 73 DenseMap<unsigned, unsigned> SrcRegMap; 74 75 // DstRegMap - A map from virtual registers to physical registers which 76 // are likely targets to be coalesced to due to copies to physical 77 // registers from virtual registers. e.g. r1 = move v1024. 78 DenseMap<unsigned, unsigned> DstRegMap; 79 80 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI, 81 unsigned Reg, 82 MachineBasicBlock::iterator OldPos); 83 84 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC, 85 MachineInstr *MI, MachineInstr *DefMI, 86 MachineBasicBlock *MBB, unsigned Loc); 87 88 bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist, 89 unsigned &LastDef); 90 91 MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB, 92 unsigned Dist); 93 94 bool isProfitableToCommute(unsigned regB, unsigned regC, 95 MachineInstr *MI, MachineBasicBlock *MBB, 96 unsigned Dist); 97 98 bool CommuteInstruction(MachineBasicBlock::iterator &mi, 99 MachineFunction::iterator &mbbi, 100 unsigned RegB, unsigned RegC, unsigned Dist); 101 102 bool isProfitableToConv3Addr(unsigned RegA); 103 104 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi, 105 MachineBasicBlock::iterator &nmi, 106 MachineFunction::iterator &mbbi, 107 unsigned RegB, unsigned Dist); 108 109 typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill; 110 bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills, 111 SmallVector<NewKill, 4> &NewKills, 112 MachineBasicBlock *MBB, unsigned Dist); 113 bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi, 114 MachineBasicBlock::iterator &nmi, 115 MachineFunction::iterator &mbbi, unsigned Dist); 116 117 bool TryInstructionTransform(MachineBasicBlock::iterator &mi, 118 MachineBasicBlock::iterator &nmi, 119 MachineFunction::iterator &mbbi, 120 unsigned SrcIdx, unsigned DstIdx, 121 unsigned Dist); 122 123 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB, 124 SmallPtrSet<MachineInstr*, 8> &Processed); 125 126 public: 127 static char ID; // Pass identification, replacement for typeid 128 TwoAddressInstructionPass() : MachineFunctionPass(&ID) {} 129 130 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 131 AU.setPreservesCFG(); 132 AU.addRequired<AliasAnalysis>(); 133 AU.addPreserved<LiveVariables>(); 134 AU.addPreservedID(MachineLoopInfoID); 135 AU.addPreservedID(MachineDominatorsID); 136 if (StrongPHIElim) 137 AU.addPreservedID(StrongPHIEliminationID); 138 else 139 AU.addPreservedID(PHIEliminationID); 140 MachineFunctionPass::getAnalysisUsage(AU); 141 } 142 143 /// runOnMachineFunction - Pass entry point. 144 bool runOnMachineFunction(MachineFunction&); 145 }; 146} 147 148char TwoAddressInstructionPass::ID = 0; 149static RegisterPass<TwoAddressInstructionPass> 150X("twoaddressinstruction", "Two-Address instruction pass"); 151 152const PassInfo *const llvm::TwoAddressInstructionPassID = &X; 153 154/// Sink3AddrInstruction - A two-address instruction has been converted to a 155/// three-address instruction to avoid clobbering a register. Try to sink it 156/// past the instruction that would kill the above mentioned register to reduce 157/// register pressure. 158bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB, 159 MachineInstr *MI, unsigned SavedReg, 160 MachineBasicBlock::iterator OldPos) { 161 // Check if it's safe to move this instruction. 162 bool SeenStore = true; // Be conservative. 163 if (!MI->isSafeToMove(TII, SeenStore, AA)) 164 return false; 165 166 unsigned DefReg = 0; 167 SmallSet<unsigned, 4> UseRegs; 168 169 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 170 const MachineOperand &MO = MI->getOperand(i); 171 if (!MO.isReg()) 172 continue; 173 unsigned MOReg = MO.getReg(); 174 if (!MOReg) 175 continue; 176 if (MO.isUse() && MOReg != SavedReg) 177 UseRegs.insert(MO.getReg()); 178 if (!MO.isDef()) 179 continue; 180 if (MO.isImplicit()) 181 // Don't try to move it if it implicitly defines a register. 182 return false; 183 if (DefReg) 184 // For now, don't move any instructions that define multiple registers. 185 return false; 186 DefReg = MO.getReg(); 187 } 188 189 // Find the instruction that kills SavedReg. 190 MachineInstr *KillMI = NULL; 191 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg), 192 UE = MRI->use_end(); UI != UE; ++UI) { 193 MachineOperand &UseMO = UI.getOperand(); 194 if (!UseMO.isKill()) 195 continue; 196 KillMI = UseMO.getParent(); 197 break; 198 } 199 200 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI) 201 return false; 202 203 // If any of the definitions are used by another instruction between the 204 // position and the kill use, then it's not safe to sink it. 205 // 206 // FIXME: This can be sped up if there is an easy way to query whether an 207 // instruction is before or after another instruction. Then we can use 208 // MachineRegisterInfo def / use instead. 209 MachineOperand *KillMO = NULL; 210 MachineBasicBlock::iterator KillPos = KillMI; 211 ++KillPos; 212 213 unsigned NumVisited = 0; 214 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) { 215 MachineInstr *OtherMI = I; 216 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost. 217 return false; 218 ++NumVisited; 219 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { 220 MachineOperand &MO = OtherMI->getOperand(i); 221 if (!MO.isReg()) 222 continue; 223 unsigned MOReg = MO.getReg(); 224 if (!MOReg) 225 continue; 226 if (DefReg == MOReg) 227 return false; 228 229 if (MO.isKill()) { 230 if (OtherMI == KillMI && MOReg == SavedReg) 231 // Save the operand that kills the register. We want to unset the kill 232 // marker if we can sink MI past it. 233 KillMO = &MO; 234 else if (UseRegs.count(MOReg)) 235 // One of the uses is killed before the destination. 236 return false; 237 } 238 } 239 } 240 241 // Update kill and LV information. 242 KillMO->setIsKill(false); 243 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI); 244 KillMO->setIsKill(true); 245 246 if (LV) 247 LV->replaceKillInstruction(SavedReg, KillMI, MI); 248 249 // Move instruction to its destination. 250 MBB->remove(MI); 251 MBB->insert(KillPos, MI); 252 253 ++Num3AddrSunk; 254 return true; 255} 256 257/// isTwoAddrUse - Return true if the specified MI is using the specified 258/// register as a two-address operand. 259static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) { 260 const TargetInstrDesc &TID = UseMI->getDesc(); 261 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { 262 MachineOperand &MO = UseMI->getOperand(i); 263 if (MO.isReg() && MO.getReg() == Reg && 264 (MO.isDef() || UseMI->isRegTiedToDefOperand(i))) 265 // Earlier use is a two-address one. 266 return true; 267 } 268 return false; 269} 270 271/// isProfitableToReMat - Return true if the heuristics determines it is likely 272/// to be profitable to re-materialize the definition of Reg rather than copy 273/// the register. 274bool 275TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg, 276 const TargetRegisterClass *RC, 277 MachineInstr *MI, MachineInstr *DefMI, 278 MachineBasicBlock *MBB, unsigned Loc) { 279 bool OtherUse = false; 280 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg), 281 UE = MRI->use_end(); UI != UE; ++UI) { 282 MachineOperand &UseMO = UI.getOperand(); 283 MachineInstr *UseMI = UseMO.getParent(); 284 MachineBasicBlock *UseMBB = UseMI->getParent(); 285 if (UseMBB == MBB) { 286 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 287 if (DI != DistanceMap.end() && DI->second == Loc) 288 continue; // Current use. 289 OtherUse = true; 290 // There is at least one other use in the MBB that will clobber the 291 // register. 292 if (isTwoAddrUse(UseMI, Reg)) 293 return true; 294 } 295 } 296 297 // If other uses in MBB are not two-address uses, then don't remat. 298 if (OtherUse) 299 return false; 300 301 // No other uses in the same block, remat if it's defined in the same 302 // block so it does not unnecessarily extend the live range. 303 return MBB == DefMI->getParent(); 304} 305 306/// NoUseAfterLastDef - Return true if there are no intervening uses between the 307/// last instruction in the MBB that defines the specified register and the 308/// two-address instruction which is being processed. It also returns the last 309/// def location by reference 310bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg, 311 MachineBasicBlock *MBB, unsigned Dist, 312 unsigned &LastDef) { 313 LastDef = 0; 314 unsigned LastUse = Dist; 315 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), 316 E = MRI->reg_end(); I != E; ++I) { 317 MachineOperand &MO = I.getOperand(); 318 MachineInstr *MI = MO.getParent(); 319 if (MI->getParent() != MBB || MI->isDebugValue()) 320 continue; 321 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 322 if (DI == DistanceMap.end()) 323 continue; 324 if (MO.isUse() && DI->second < LastUse) 325 LastUse = DI->second; 326 if (MO.isDef() && DI->second > LastDef) 327 LastDef = DI->second; 328 } 329 330 return !(LastUse > LastDef && LastUse < Dist); 331} 332 333MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg, 334 MachineBasicBlock *MBB, 335 unsigned Dist) { 336 unsigned LastUseDist = 0; 337 MachineInstr *LastUse = 0; 338 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), 339 E = MRI->reg_end(); I != E; ++I) { 340 MachineOperand &MO = I.getOperand(); 341 MachineInstr *MI = MO.getParent(); 342 if (MI->getParent() != MBB || MI->isDebugValue()) 343 continue; 344 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 345 if (DI == DistanceMap.end()) 346 continue; 347 if (DI->second >= Dist) 348 continue; 349 350 if (MO.isUse() && DI->second > LastUseDist) { 351 LastUse = DI->first; 352 LastUseDist = DI->second; 353 } 354 } 355 return LastUse; 356} 357 358/// isCopyToReg - Return true if the specified MI is a copy instruction or 359/// a extract_subreg instruction. It also returns the source and destination 360/// registers and whether they are physical registers by reference. 361static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, 362 unsigned &SrcReg, unsigned &DstReg, 363 bool &IsSrcPhys, bool &IsDstPhys) { 364 SrcReg = 0; 365 DstReg = 0; 366 unsigned SrcSubIdx, DstSubIdx; 367 if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) { 368 if (MI.isExtractSubreg()) { 369 DstReg = MI.getOperand(0).getReg(); 370 SrcReg = MI.getOperand(1).getReg(); 371 } else if (MI.isInsertSubreg()) { 372 DstReg = MI.getOperand(0).getReg(); 373 SrcReg = MI.getOperand(2).getReg(); 374 } else if (MI.isSubregToReg()) { 375 DstReg = MI.getOperand(0).getReg(); 376 SrcReg = MI.getOperand(2).getReg(); 377 } 378 } 379 380 if (DstReg) { 381 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); 382 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 383 return true; 384 } 385 return false; 386} 387 388/// isKilled - Test if the given register value, which is used by the given 389/// instruction, is killed by the given instruction. This looks through 390/// coalescable copies to see if the original value is potentially not killed. 391/// 392/// For example, in this code: 393/// 394/// %reg1034 = copy %reg1024 395/// %reg1035 = copy %reg1025<kill> 396/// %reg1036 = add %reg1034<kill>, %reg1035<kill> 397/// 398/// %reg1034 is not considered to be killed, since it is copied from a 399/// register which is not killed. Treating it as not killed lets the 400/// normal heuristics commute the (two-address) add, which lets 401/// coalescing eliminate the extra copy. 402/// 403static bool isKilled(MachineInstr &MI, unsigned Reg, 404 const MachineRegisterInfo *MRI, 405 const TargetInstrInfo *TII) { 406 MachineInstr *DefMI = &MI; 407 for (;;) { 408 if (!DefMI->killsRegister(Reg)) 409 return false; 410 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 411 return true; 412 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg); 413 // If there are multiple defs, we can't do a simple analysis, so just 414 // go with what the kill flag says. 415 if (llvm::next(Begin) != MRI->def_end()) 416 return true; 417 DefMI = &*Begin; 418 bool IsSrcPhys, IsDstPhys; 419 unsigned SrcReg, DstReg; 420 // If the def is something other than a copy, then it isn't going to 421 // be coalesced, so follow the kill flag. 422 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 423 return true; 424 Reg = SrcReg; 425 } 426} 427 428/// isTwoAddrUse - Return true if the specified MI uses the specified register 429/// as a two-address use. If so, return the destination register by reference. 430static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { 431 const TargetInstrDesc &TID = MI.getDesc(); 432 unsigned NumOps = MI.isInlineAsm() ? MI.getNumOperands():TID.getNumOperands(); 433 for (unsigned i = 0; i != NumOps; ++i) { 434 const MachineOperand &MO = MI.getOperand(i); 435 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) 436 continue; 437 unsigned ti; 438 if (MI.isRegTiedToDefOperand(i, &ti)) { 439 DstReg = MI.getOperand(ti).getReg(); 440 return true; 441 } 442 } 443 return false; 444} 445 446/// findOnlyInterestingUse - Given a register, if has a single in-basic block 447/// use, return the use instruction if it's a copy or a two-address use. 448static 449MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, 450 MachineRegisterInfo *MRI, 451 const TargetInstrInfo *TII, 452 bool &IsCopy, 453 unsigned &DstReg, bool &IsDstPhys) { 454 MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg); 455 if (UI == MRI->use_nodbg_end()) 456 return 0; 457 MachineInstr &UseMI = *UI; 458 if (++UI != MRI->use_nodbg_end()) 459 // More than one use. 460 return 0; 461 if (UseMI.getParent() != MBB) 462 return 0; 463 unsigned SrcReg; 464 bool IsSrcPhys; 465 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) { 466 IsCopy = true; 467 return &UseMI; 468 } 469 IsDstPhys = false; 470 if (isTwoAddrUse(UseMI, Reg, DstReg)) { 471 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 472 return &UseMI; 473 } 474 return 0; 475} 476 477/// getMappedReg - Return the physical register the specified virtual register 478/// might be mapped to. 479static unsigned 480getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) { 481 while (TargetRegisterInfo::isVirtualRegister(Reg)) { 482 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg); 483 if (SI == RegMap.end()) 484 return 0; 485 Reg = SI->second; 486 } 487 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 488 return Reg; 489 return 0; 490} 491 492/// regsAreCompatible - Return true if the two registers are equal or aliased. 493/// 494static bool 495regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { 496 if (RegA == RegB) 497 return true; 498 if (!RegA || !RegB) 499 return false; 500 return TRI->regsOverlap(RegA, RegB); 501} 502 503 504/// isProfitableToReMat - Return true if it's potentially profitable to commute 505/// the two-address instruction that's being processed. 506bool 507TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC, 508 MachineInstr *MI, MachineBasicBlock *MBB, 509 unsigned Dist) { 510 // Determine if it's profitable to commute this two address instruction. In 511 // general, we want no uses between this instruction and the definition of 512 // the two-address register. 513 // e.g. 514 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 515 // %reg1029<def> = MOV8rr %reg1028 516 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 517 // insert => %reg1030<def> = MOV8rr %reg1028 518 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 519 // In this case, it might not be possible to coalesce the second MOV8rr 520 // instruction if the first one is coalesced. So it would be profitable to 521 // commute it: 522 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 523 // %reg1029<def> = MOV8rr %reg1028 524 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 525 // insert => %reg1030<def> = MOV8rr %reg1029 526 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead> 527 528 if (!MI->killsRegister(regC)) 529 return false; 530 531 // Ok, we have something like: 532 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 533 // let's see if it's worth commuting it. 534 535 // Look for situations like this: 536 // %reg1024<def> = MOV r1 537 // %reg1025<def> = MOV r0 538 // %reg1026<def> = ADD %reg1024, %reg1025 539 // r0 = MOV %reg1026 540 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy. 541 unsigned FromRegB = getMappedReg(regB, SrcRegMap); 542 unsigned FromRegC = getMappedReg(regC, SrcRegMap); 543 unsigned ToRegB = getMappedReg(regB, DstRegMap); 544 unsigned ToRegC = getMappedReg(regC, DstRegMap); 545 if (!regsAreCompatible(FromRegB, ToRegB, TRI) && 546 (regsAreCompatible(FromRegB, ToRegC, TRI) || 547 regsAreCompatible(FromRegC, ToRegB, TRI))) 548 return true; 549 550 // If there is a use of regC between its last def (could be livein) and this 551 // instruction, then bail. 552 unsigned LastDefC = 0; 553 if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC)) 554 return false; 555 556 // If there is a use of regB between its last def (could be livein) and this 557 // instruction, then go ahead and make this transformation. 558 unsigned LastDefB = 0; 559 if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB)) 560 return true; 561 562 // Since there are no intervening uses for both registers, then commute 563 // if the def of regC is closer. Its live interval is shorter. 564 return LastDefB && LastDefC && LastDefC > LastDefB; 565} 566 567/// CommuteInstruction - Commute a two-address instruction and update the basic 568/// block, distance map, and live variables if needed. Return true if it is 569/// successful. 570bool 571TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi, 572 MachineFunction::iterator &mbbi, 573 unsigned RegB, unsigned RegC, unsigned Dist) { 574 MachineInstr *MI = mi; 575 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI); 576 MachineInstr *NewMI = TII->commuteInstruction(MI); 577 578 if (NewMI == 0) { 579 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n"); 580 return false; 581 } 582 583 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI); 584 // If the instruction changed to commute it, update livevar. 585 if (NewMI != MI) { 586 if (LV) 587 // Update live variables 588 LV->replaceKillInstruction(RegC, MI, NewMI); 589 590 mbbi->insert(mi, NewMI); // Insert the new inst 591 mbbi->erase(mi); // Nuke the old inst. 592 mi = NewMI; 593 DistanceMap.insert(std::make_pair(NewMI, Dist)); 594 } 595 596 // Update source register map. 597 unsigned FromRegC = getMappedReg(RegC, SrcRegMap); 598 if (FromRegC) { 599 unsigned RegA = MI->getOperand(0).getReg(); 600 SrcRegMap[RegA] = FromRegC; 601 } 602 603 return true; 604} 605 606/// isProfitableToConv3Addr - Return true if it is profitable to convert the 607/// given 2-address instruction to a 3-address one. 608bool 609TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA) { 610 // Look for situations like this: 611 // %reg1024<def> = MOV r1 612 // %reg1025<def> = MOV r0 613 // %reg1026<def> = ADD %reg1024, %reg1025 614 // r2 = MOV %reg1026 615 // Turn ADD into a 3-address instruction to avoid a copy. 616 unsigned FromRegA = getMappedReg(RegA, SrcRegMap); 617 unsigned ToRegA = getMappedReg(RegA, DstRegMap); 618 return (FromRegA && ToRegA && !regsAreCompatible(FromRegA, ToRegA, TRI)); 619} 620 621/// ConvertInstTo3Addr - Convert the specified two-address instruction into a 622/// three address one. Return true if this transformation was successful. 623bool 624TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi, 625 MachineBasicBlock::iterator &nmi, 626 MachineFunction::iterator &mbbi, 627 unsigned RegB, unsigned Dist) { 628 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV); 629 if (NewMI) { 630 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi); 631 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI); 632 bool Sunk = false; 633 634 if (NewMI->findRegisterUseOperand(RegB, false, TRI)) 635 // FIXME: Temporary workaround. If the new instruction doesn't 636 // uses RegB, convertToThreeAddress must have created more 637 // then one instruction. 638 Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi); 639 640 mbbi->erase(mi); // Nuke the old inst. 641 642 if (!Sunk) { 643 DistanceMap.insert(std::make_pair(NewMI, Dist)); 644 mi = NewMI; 645 nmi = llvm::next(mi); 646 } 647 return true; 648 } 649 650 return false; 651} 652 653/// ProcessCopy - If the specified instruction is not yet processed, process it 654/// if it's a copy. For a copy instruction, we find the physical registers the 655/// source and destination registers might be mapped to. These are kept in 656/// point-to maps used to determine future optimizations. e.g. 657/// v1024 = mov r0 658/// v1025 = mov r1 659/// v1026 = add v1024, v1025 660/// r1 = mov r1026 661/// If 'add' is a two-address instruction, v1024, v1026 are both potentially 662/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is 663/// potentially joined with r1 on the output side. It's worthwhile to commute 664/// 'add' to eliminate a copy. 665void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI, 666 MachineBasicBlock *MBB, 667 SmallPtrSet<MachineInstr*, 8> &Processed) { 668 if (Processed.count(MI)) 669 return; 670 671 bool IsSrcPhys, IsDstPhys; 672 unsigned SrcReg, DstReg; 673 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 674 return; 675 676 if (IsDstPhys && !IsSrcPhys) 677 DstRegMap.insert(std::make_pair(SrcReg, DstReg)); 678 else if (!IsDstPhys && IsSrcPhys) { 679 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second; 680 if (!isNew) 681 assert(SrcRegMap[DstReg] == SrcReg && 682 "Can't map to two src physical registers!"); 683 684 SmallVector<unsigned, 4> VirtRegPairs; 685 bool IsCopy = false; 686 unsigned NewReg = 0; 687 while (MachineInstr *UseMI = findOnlyInterestingUse(DstReg, MBB, MRI,TII, 688 IsCopy, NewReg, IsDstPhys)) { 689 if (IsCopy) { 690 if (!Processed.insert(UseMI)) 691 break; 692 } 693 694 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 695 if (DI != DistanceMap.end()) 696 // Earlier in the same MBB.Reached via a back edge. 697 break; 698 699 if (IsDstPhys) { 700 VirtRegPairs.push_back(NewReg); 701 break; 702 } 703 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, DstReg)).second; 704 if (!isNew) 705 assert(SrcRegMap[NewReg] == DstReg && 706 "Can't map to two src physical registers!"); 707 VirtRegPairs.push_back(NewReg); 708 DstReg = NewReg; 709 } 710 711 if (!VirtRegPairs.empty()) { 712 unsigned ToReg = VirtRegPairs.back(); 713 VirtRegPairs.pop_back(); 714 while (!VirtRegPairs.empty()) { 715 unsigned FromReg = VirtRegPairs.back(); 716 VirtRegPairs.pop_back(); 717 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second; 718 if (!isNew) 719 assert(DstRegMap[FromReg] == ToReg && 720 "Can't map to two dst physical registers!"); 721 ToReg = FromReg; 722 } 723 } 724 } 725 726 Processed.insert(MI); 727} 728 729/// isSafeToDelete - If the specified instruction does not produce any side 730/// effects and all of its defs are dead, then it's safe to delete. 731static bool isSafeToDelete(MachineInstr *MI, 732 const TargetInstrInfo *TII, 733 SmallVector<unsigned, 4> &Kills) { 734 const TargetInstrDesc &TID = MI->getDesc(); 735 if (TID.mayStore() || TID.isCall()) 736 return false; 737 if (TID.isTerminator() || TID.hasUnmodeledSideEffects()) 738 return false; 739 740 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 741 MachineOperand &MO = MI->getOperand(i); 742 if (!MO.isReg()) 743 continue; 744 if (MO.isDef() && !MO.isDead()) 745 return false; 746 if (MO.isUse() && MO.isKill()) 747 Kills.push_back(MO.getReg()); 748 } 749 return true; 750} 751 752/// canUpdateDeletedKills - Check if all the registers listed in Kills are 753/// killed by instructions in MBB preceding the current instruction at 754/// position Dist. If so, return true and record information about the 755/// preceding kills in NewKills. 756bool TwoAddressInstructionPass:: 757canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills, 758 SmallVector<NewKill, 4> &NewKills, 759 MachineBasicBlock *MBB, unsigned Dist) { 760 while (!Kills.empty()) { 761 unsigned Kill = Kills.back(); 762 Kills.pop_back(); 763 if (TargetRegisterInfo::isPhysicalRegister(Kill)) 764 return false; 765 766 MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist); 767 if (!LastKill) 768 return false; 769 770 bool isModRef = LastKill->modifiesRegister(Kill); 771 NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef), 772 LastKill)); 773 } 774 return true; 775} 776 777/// DeleteUnusedInstr - If an instruction with a tied register operand can 778/// be safely deleted, just delete it. 779bool 780TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi, 781 MachineBasicBlock::iterator &nmi, 782 MachineFunction::iterator &mbbi, 783 unsigned Dist) { 784 // Check if the instruction has no side effects and if all its defs are dead. 785 SmallVector<unsigned, 4> Kills; 786 if (!isSafeToDelete(mi, TII, Kills)) 787 return false; 788 789 // If this instruction kills some virtual registers, we need to 790 // update the kill information. If it's not possible to do so, 791 // then bail out. 792 SmallVector<NewKill, 4> NewKills; 793 if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist)) 794 return false; 795 796 if (LV) { 797 while (!NewKills.empty()) { 798 MachineInstr *NewKill = NewKills.back().second; 799 unsigned Kill = NewKills.back().first.first; 800 bool isDead = NewKills.back().first.second; 801 NewKills.pop_back(); 802 if (LV->removeVirtualRegisterKilled(Kill, mi)) { 803 if (isDead) 804 LV->addVirtualRegisterDead(Kill, NewKill); 805 else 806 LV->addVirtualRegisterKilled(Kill, NewKill); 807 } 808 } 809 } 810 811 mbbi->erase(mi); // Nuke the old inst. 812 mi = nmi; 813 return true; 814} 815 816/// TryInstructionTransform - For the case where an instruction has a single 817/// pair of tied register operands, attempt some transformations that may 818/// either eliminate the tied operands or improve the opportunities for 819/// coalescing away the register copy. Returns true if the tied operands 820/// are eliminated altogether. 821bool TwoAddressInstructionPass:: 822TryInstructionTransform(MachineBasicBlock::iterator &mi, 823 MachineBasicBlock::iterator &nmi, 824 MachineFunction::iterator &mbbi, 825 unsigned SrcIdx, unsigned DstIdx, unsigned Dist) { 826 const TargetInstrDesc &TID = mi->getDesc(); 827 unsigned regA = mi->getOperand(DstIdx).getReg(); 828 unsigned regB = mi->getOperand(SrcIdx).getReg(); 829 830 assert(TargetRegisterInfo::isVirtualRegister(regB) && 831 "cannot make instruction into two-address form"); 832 833 // If regA is dead and the instruction can be deleted, just delete 834 // it so it doesn't clobber regB. 835 bool regBKilled = isKilled(*mi, regB, MRI, TII); 836 if (!regBKilled && mi->getOperand(DstIdx).isDead() && 837 DeleteUnusedInstr(mi, nmi, mbbi, Dist)) { 838 ++NumDeletes; 839 return true; // Done with this instruction. 840 } 841 842 // Check if it is profitable to commute the operands. 843 unsigned SrcOp1, SrcOp2; 844 unsigned regC = 0; 845 unsigned regCIdx = ~0U; 846 bool TryCommute = false; 847 bool AggressiveCommute = false; 848 if (TID.isCommutable() && mi->getNumOperands() >= 3 && 849 TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) { 850 if (SrcIdx == SrcOp1) 851 regCIdx = SrcOp2; 852 else if (SrcIdx == SrcOp2) 853 regCIdx = SrcOp1; 854 855 if (regCIdx != ~0U) { 856 regC = mi->getOperand(regCIdx).getReg(); 857 if (!regBKilled && isKilled(*mi, regC, MRI, TII)) 858 // If C dies but B does not, swap the B and C operands. 859 // This makes the live ranges of A and C joinable. 860 TryCommute = true; 861 else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) { 862 TryCommute = true; 863 AggressiveCommute = true; 864 } 865 } 866 } 867 868 // If it's profitable to commute, try to do so. 869 if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) { 870 ++NumCommuted; 871 if (AggressiveCommute) 872 ++NumAggrCommuted; 873 return false; 874 } 875 876 if (TID.isConvertibleTo3Addr()) { 877 // This instruction is potentially convertible to a true 878 // three-address instruction. Check if it is profitable. 879 if (!regBKilled || isProfitableToConv3Addr(regA)) { 880 // Try to convert it. 881 if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) { 882 ++NumConvertedTo3Addr; 883 return true; // Done with this instruction. 884 } 885 } 886 } 887 return false; 888} 889 890/// runOnMachineFunction - Reduce two-address instructions to two operands. 891/// 892bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { 893 DEBUG(dbgs() << "Machine Function\n"); 894 const TargetMachine &TM = MF.getTarget(); 895 MRI = &MF.getRegInfo(); 896 TII = TM.getInstrInfo(); 897 TRI = TM.getRegisterInfo(); 898 LV = getAnalysisIfAvailable<LiveVariables>(); 899 AA = &getAnalysis<AliasAnalysis>(); 900 901 bool MadeChange = false; 902 903 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n"); 904 DEBUG(dbgs() << "********** Function: " 905 << MF.getFunction()->getName() << '\n'); 906 907 // ReMatRegs - Keep track of the registers whose def's are remat'ed. 908 BitVector ReMatRegs; 909 ReMatRegs.resize(MRI->getLastVirtReg()+1); 910 911 typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> > 912 TiedOperandMap; 913 TiedOperandMap TiedOperands(4); 914 915 SmallPtrSet<MachineInstr*, 8> Processed; 916 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); 917 mbbi != mbbe; ++mbbi) { 918 unsigned Dist = 0; 919 DistanceMap.clear(); 920 SrcRegMap.clear(); 921 DstRegMap.clear(); 922 Processed.clear(); 923 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); 924 mi != me; ) { 925 MachineBasicBlock::iterator nmi = llvm::next(mi); 926 if (mi->isDebugValue()) { 927 mi = nmi; 928 continue; 929 } 930 const TargetInstrDesc &TID = mi->getDesc(); 931 bool FirstTied = true; 932 933 DistanceMap.insert(std::make_pair(mi, ++Dist)); 934 935 ProcessCopy(&*mi, &*mbbi, Processed); 936 937 // First scan through all the tied register uses in this instruction 938 // and record a list of pairs of tied operands for each register. 939 unsigned NumOps = mi->isInlineAsm() 940 ? mi->getNumOperands() : TID.getNumOperands(); 941 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { 942 unsigned DstIdx = 0; 943 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx)) 944 continue; 945 946 if (FirstTied) { 947 FirstTied = false; 948 ++NumTwoAddressInstrs; 949 DEBUG(dbgs() << '\t' << *mi); 950 } 951 952 assert(mi->getOperand(SrcIdx).isReg() && 953 mi->getOperand(SrcIdx).getReg() && 954 mi->getOperand(SrcIdx).isUse() && 955 "two address instruction invalid"); 956 957 unsigned regB = mi->getOperand(SrcIdx).getReg(); 958 TiedOperandMap::iterator OI = TiedOperands.find(regB); 959 if (OI == TiedOperands.end()) { 960 SmallVector<std::pair<unsigned, unsigned>, 4> TiedPair; 961 OI = TiedOperands.insert(std::make_pair(regB, TiedPair)).first; 962 } 963 OI->second.push_back(std::make_pair(SrcIdx, DstIdx)); 964 } 965 966 // Now iterate over the information collected above. 967 for (TiedOperandMap::iterator OI = TiedOperands.begin(), 968 OE = TiedOperands.end(); OI != OE; ++OI) { 969 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second; 970 971 // If the instruction has a single pair of tied operands, try some 972 // transformations that may either eliminate the tied operands or 973 // improve the opportunities for coalescing away the register copy. 974 if (TiedOperands.size() == 1 && TiedPairs.size() == 1) { 975 unsigned SrcIdx = TiedPairs[0].first; 976 unsigned DstIdx = TiedPairs[0].second; 977 978 // If the registers are already equal, nothing needs to be done. 979 if (mi->getOperand(SrcIdx).getReg() == 980 mi->getOperand(DstIdx).getReg()) 981 break; // Done with this instruction. 982 983 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist)) 984 break; // The tied operands have been eliminated. 985 } 986 987 bool RemovedKillFlag = false; 988 bool AllUsesCopied = true; 989 unsigned LastCopiedReg = 0; 990 unsigned regB = OI->first; 991 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) { 992 unsigned SrcIdx = TiedPairs[tpi].first; 993 unsigned DstIdx = TiedPairs[tpi].second; 994 unsigned regA = mi->getOperand(DstIdx).getReg(); 995 // Grab regB from the instruction because it may have changed if the 996 // instruction was commuted. 997 regB = mi->getOperand(SrcIdx).getReg(); 998 999 if (regA == regB) { 1000 // The register is tied to multiple destinations (or else we would 1001 // not have continued this far), but this use of the register 1002 // already matches the tied destination. Leave it. 1003 AllUsesCopied = false; 1004 continue; 1005 } 1006 LastCopiedReg = regA; 1007 1008 assert(TargetRegisterInfo::isVirtualRegister(regB) && 1009 "cannot make instruction into two-address form"); 1010 1011#ifndef NDEBUG 1012 // First, verify that we don't have a use of "a" in the instruction 1013 // (a = b + a for example) because our transformation will not 1014 // work. This should never occur because we are in SSA form. 1015 for (unsigned i = 0; i != mi->getNumOperands(); ++i) 1016 assert(i == DstIdx || 1017 !mi->getOperand(i).isReg() || 1018 mi->getOperand(i).getReg() != regA); 1019#endif 1020 1021 // Emit a copy or rematerialize the definition. 1022 const TargetRegisterClass *rc = MRI->getRegClass(regB); 1023 MachineInstr *DefMI = MRI->getVRegDef(regB); 1024 // If it's safe and profitable, remat the definition instead of 1025 // copying it. 1026 if (DefMI && 1027 DefMI->getDesc().isAsCheapAsAMove() && 1028 DefMI->isSafeToReMat(TII, regB, AA) && 1029 isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){ 1030 DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n"); 1031 unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg(); 1032 TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, TRI); 1033 ReMatRegs.set(regB); 1034 ++NumReMats; 1035 } else { 1036 bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc); 1037 (void)Emitted; 1038 assert(Emitted && "Unable to issue a copy instruction!\n"); 1039 } 1040 1041 MachineBasicBlock::iterator prevMI = prior(mi); 1042 // Update DistanceMap. 1043 DistanceMap.insert(std::make_pair(prevMI, Dist)); 1044 DistanceMap[mi] = ++Dist; 1045 1046 DEBUG(dbgs() << "\t\tprepend:\t" << *prevMI); 1047 1048 MachineOperand &MO = mi->getOperand(SrcIdx); 1049 assert(MO.isReg() && MO.getReg() == regB && MO.isUse() && 1050 "inconsistent operand info for 2-reg pass"); 1051 if (MO.isKill()) { 1052 MO.setIsKill(false); 1053 RemovedKillFlag = true; 1054 } 1055 MO.setReg(regA); 1056 } 1057 1058 if (AllUsesCopied) { 1059 // Replace other (un-tied) uses of regB with LastCopiedReg. 1060 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { 1061 MachineOperand &MO = mi->getOperand(i); 1062 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) { 1063 if (MO.isKill()) { 1064 MO.setIsKill(false); 1065 RemovedKillFlag = true; 1066 } 1067 MO.setReg(LastCopiedReg); 1068 } 1069 } 1070 1071 // Update live variables for regB. 1072 if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi)) 1073 LV->addVirtualRegisterKilled(regB, prior(mi)); 1074 1075 } else if (RemovedKillFlag) { 1076 // Some tied uses of regB matched their destination registers, so 1077 // regB is still used in this instruction, but a kill flag was 1078 // removed from a different tied use of regB, so now we need to add 1079 // a kill flag to one of the remaining uses of regB. 1080 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { 1081 MachineOperand &MO = mi->getOperand(i); 1082 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) { 1083 MO.setIsKill(true); 1084 break; 1085 } 1086 } 1087 } 1088 1089 MadeChange = true; 1090 1091 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi); 1092 } 1093 1094 // Clear TiedOperands here instead of at the top of the loop 1095 // since most instructions do not have tied operands. 1096 TiedOperands.clear(); 1097 mi = nmi; 1098 } 1099 } 1100 1101 // Some remat'ed instructions are dead. 1102 int VReg = ReMatRegs.find_first(); 1103 while (VReg != -1) { 1104 if (MRI->use_empty(VReg)) { 1105 MachineInstr *DefMI = MRI->getVRegDef(VReg); 1106 DefMI->eraseFromParent(); 1107 } 1108 VReg = ReMatRegs.find_next(VReg); 1109 } 1110 1111 return MadeChange; 1112} 1113