TwoAddressInstructionPass.cpp revision cfa0f2edd31a32d58ffa6e5224c6f476932d82b5
1//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the TwoAddress instruction pass which is used 11// by most register allocators. Two-Address instructions are rewritten 12// from: 13// 14// A = B op C 15// 16// to: 17// 18// A = B 19// A op= C 20// 21// Note that if a register allocator chooses to use this pass, that it 22// has to be capable of handling the non-SSA nature of these rewritten 23// virtual registers. 24// 25// It is also worth noting that the duplicate operand of the two 26// address instruction is removed. 27// 28//===----------------------------------------------------------------------===// 29 30#define DEBUG_TYPE "twoaddrinstr" 31#include "llvm/CodeGen/Passes.h" 32#include "llvm/Function.h" 33#include "llvm/CodeGen/LiveVariables.h" 34#include "llvm/CodeGen/MachineFunctionPass.h" 35#include "llvm/CodeGen/MachineInstr.h" 36#include "llvm/CodeGen/SSARegMap.h" 37#include "llvm/Target/MRegisterInfo.h" 38#include "llvm/Target/TargetInstrInfo.h" 39#include "llvm/Target/TargetMachine.h" 40#include "llvm/Support/Debug.h" 41#include "llvm/ADT/Statistic.h" 42#include "llvm/ADT/STLExtras.h" 43using namespace llvm; 44 45namespace { 46 Statistic<> NumTwoAddressInstrs("twoaddressinstruction", 47 "Number of two-address instructions"); 48 Statistic<> NumCommuted("twoaddressinstruction", 49 "Number of instructions commuted to coallesce"); 50 Statistic<> NumConvertedTo3Addr("twoaddressinstruction", 51 "Number of instructions promoted to 3-address"); 52 53 struct TwoAddressInstructionPass : public MachineFunctionPass { 54 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 55 56 /// runOnMachineFunction - pass entry point 57 bool runOnMachineFunction(MachineFunction&); 58 }; 59 60 RegisterPass<TwoAddressInstructionPass> 61 X("twoaddressinstruction", "Two-Address instruction pass"); 62}; 63 64const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo(); 65 66void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const { 67 AU.addRequired<LiveVariables>(); 68 AU.addPreserved<LiveVariables>(); 69 AU.addPreservedID(PHIEliminationID); 70 MachineFunctionPass::getAnalysisUsage(AU); 71} 72 73/// runOnMachineFunction - Reduce two-address instructions to two 74/// operands. 75/// 76bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { 77 DEBUG(std::cerr << "Machine Function\n"); 78 const TargetMachine &TM = MF.getTarget(); 79 const MRegisterInfo &MRI = *TM.getRegisterInfo(); 80 const TargetInstrInfo &TII = *TM.getInstrInfo(); 81 LiveVariables &LV = getAnalysis<LiveVariables>(); 82 83 bool MadeChange = false; 84 85 DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n"); 86 DEBUG(std::cerr << "********** Function: " 87 << MF.getFunction()->getName() << '\n'); 88 89 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); 90 mbbi != mbbe; ++mbbi) { 91 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); 92 mi != me; ++mi) { 93 unsigned opcode = mi->getOpcode(); 94 95 // ignore if it is not a two-address instruction 96 if (!TII.isTwoAddrInstr(opcode)) 97 continue; 98 99 ++NumTwoAddressInstrs; 100 DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM)); 101 assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() && 102 mi->getOperand(1).isUse() && "two address instruction invalid"); 103 104 // if the two operands are the same we just remove the use 105 // and mark the def as def&use, otherwise we have to insert a copy. 106 if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) { 107 // rewrite: 108 // a = b op c 109 // to: 110 // a = b 111 // a = a op c 112 unsigned regA = mi->getOperand(0).getReg(); 113 unsigned regB = mi->getOperand(1).getReg(); 114 115 assert(MRegisterInfo::isVirtualRegister(regA) && 116 MRegisterInfo::isVirtualRegister(regB) && 117 "cannot update physical register live information"); 118 119#ifndef NDEBUG 120 // First, verify that we do not have a use of a in the instruction (a = 121 // b + a for example) because our transformation will not work. This 122 // should never occur because we are in SSA form. 123 for (unsigned i = 1; i != mi->getNumOperands(); ++i) 124 assert(!mi->getOperand(i).isRegister() || 125 mi->getOperand(i).getReg() != regA); 126#endif 127 128 // If this instruction is not the killing user of B, see if we can 129 // rearrange the code to make it so. Making it the killing user will 130 // allow us to coallesce A and B together, eliminating the copy we are 131 // about to insert. 132 if (!LV.KillsRegister(mi, regB)) { 133 const TargetInstrDescriptor &TID = TII.get(opcode); 134 135 // If this instruction is commutative, check to see if C dies. If so, 136 // swap the B and C operands. This makes the live ranges of A and C 137 // joinable. 138 if (TID.Flags & M_COMMUTABLE) { 139 assert(mi->getOperand(2).isRegister() && 140 "Not a proper commutative instruction!"); 141 unsigned regC = mi->getOperand(2).getReg(); 142 if (LV.KillsRegister(mi, regC)) { 143 DEBUG(std::cerr << "2addr: COMMUTING : " << *mi); 144 mi->SetMachineOperandReg(2, regB); 145 mi->SetMachineOperandReg(1, regC); 146 DEBUG(std::cerr << "2addr: COMMUTED TO: " << *mi); 147 ++NumCommuted; 148 regB = regC; 149 goto InstructionRearranged; 150 } 151 } 152 // If this instruction is potentially convertible to a true 153 // three-address instruction, 154 if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR) 155 if (MachineInstr *New = TII.convertToThreeAddress(mi)) { 156 DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi); 157 DEBUG(std::cerr << "2addr: TO 3-ADDR: " << *New); 158 LV.instructionChanged(mi, New); // Update live variables 159 mbbi->insert(mi, New); // Insert the new inst 160 mbbi->erase(mi); // Nuke the old inst. 161 mi = New; 162 ++NumConvertedTo3Addr; 163 assert(!TII.isTwoAddrInstr(New->getOpcode()) && 164 "convertToThreeAddress returned a 2-addr instruction??"); 165 // Done with this instruction. 166 continue; 167 } 168 } 169 InstructionRearranged: 170 const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA); 171 MRI.copyRegToReg(*mbbi, mi, regA, regB, rc); 172 173 MachineBasicBlock::iterator prevMi = prior(mi); 174 DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM)); 175 176 // Update live variables for regA 177 LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA); 178 varInfo.DefInst = prevMi; 179 180 // update live variables for regB 181 if (LV.removeVirtualRegisterKilled(regB, mbbi, mi)) 182 LV.addVirtualRegisterKilled(regB, prevMi); 183 184 if (LV.removeVirtualRegisterDead(regB, mbbi, mi)) 185 LV.addVirtualRegisterDead(regB, prevMi); 186 187 // replace all occurences of regB with regA 188 for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) { 189 if (mi->getOperand(i).isRegister() && 190 mi->getOperand(i).getReg() == regB) 191 mi->SetMachineOperandReg(i, regA); 192 } 193 } 194 195 assert(mi->getOperand(0).isDef()); 196 mi->getOperand(0).setUse(); 197 mi->RemoveOperand(1); 198 MadeChange = true; 199 200 DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM)); 201 } 202 } 203 204 return MadeChange; 205} 206