ARMSubtarget.h revision 5b1b4489cf3a0f56f8be0673fc5cc380a32d277b
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file declares the ARM specific subclass of TargetSubtargetInfo. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef ARMSUBTARGET_H 15#define ARMSUBTARGET_H 16 17#include "llvm/Target/TargetSubtargetInfo.h" 18#include "llvm/MC/MCInstrItineraries.h" 19#include "llvm/ADT/Triple.h" 20#include <string> 21 22#define GET_SUBTARGETINFO_HEADER 23#include "ARMGenSubtarget.inc" 24 25namespace llvm { 26class GlobalValue; 27 28class ARMSubtarget : public ARMGenSubtargetInfo { 29protected: 30 enum ARMArchEnum { 31 V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M 32 }; 33 34 enum ARMProcFamilyEnum { 35 Others, CortexA8, CortexA9 36 }; 37 38 enum ARMFPEnum { 39 None, VFPv2, VFPv3, NEON 40 }; 41 42 enum ThumbTypeEnum { 43 Thumb1, 44 Thumb2 45 }; 46 47 /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE, 48 /// V6, V6T2, V7A, V7M. 49 ARMArchEnum ARMArchVersion; 50 51 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. 52 ARMProcFamilyEnum ARMProcFamily; 53 54 /// ARMFPUType - Floating Point Unit type. 55 ARMFPEnum ARMFPUType; 56 57 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been 58 /// specified. Use the method useNEONForSinglePrecisionFP() to 59 /// determine if NEON should actually be used. 60 bool UseNEONForSinglePrecisionFP; 61 62 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates 63 /// whether the FP VML[AS] instructions are slow (if so, don't use them). 64 bool SlowFPVMLx; 65 66 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator 67 /// forwarding to allow mul + mla being issued back to back. 68 bool HasVMLxForwarding; 69 70 /// SlowFPBrcc - True if floating point compare + branch is slow. 71 bool SlowFPBrcc; 72 73 /// IsThumb - True if we are in thumb mode, false if in ARM mode. 74 bool IsThumb; 75 76 /// ThumbMode - Indicates supported Thumb version. 77 ThumbTypeEnum ThumbMode; 78 79 /// NoARM - True if subtarget does not support ARM mode execution. 80 bool NoARM; 81 82 /// PostRAScheduler - True if using post-register-allocation scheduler. 83 bool PostRAScheduler; 84 85 /// IsR9Reserved - True if R9 is a not available as general purpose register. 86 bool IsR9Reserved; 87 88 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit 89 /// imms (including global addresses). 90 bool UseMovt; 91 92 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF 93 /// only so far) 94 bool HasFP16; 95 96 /// HasD16 - True if subtarget is limited to 16 double precision 97 /// FP registers for VFPv3. 98 bool HasD16; 99 100 /// HasHardwareDivide - True if subtarget supports [su]div 101 bool HasHardwareDivide; 102 103 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack 104 /// instructions. 105 bool HasT2ExtractPack; 106 107 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier 108 /// instructions. 109 bool HasDataBarrier; 110 111 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions 112 /// over 16-bit ones. 113 bool Pref32BitThumb; 114 115 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions 116 /// that partially update CPSR and add false dependency on the previous 117 /// CPSR setting instruction. 118 bool AvoidCPSRPartialUpdate; 119 120 /// HasMPExtension - True if the subtarget supports Multiprocessing 121 /// extension (ARMv7 only). 122 bool HasMPExtension; 123 124 /// FPOnlySP - If true, the floating point unit only supports single 125 /// precision. 126 bool FPOnlySP; 127 128 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory 129 /// accesses for some types. For details, see 130 /// ARMTargetLowering::allowsUnalignedMemoryAccesses(). 131 bool AllowsUnalignedMem; 132 133 /// stackAlignment - The minimum alignment known to hold of the stack frame on 134 /// entry to the function and which must be maintained by every function. 135 unsigned stackAlignment; 136 137 /// CPUString - String name of used CPU. 138 std::string CPUString; 139 140 /// TargetTriple - What processor and OS we're targeting. 141 Triple TargetTriple; 142 143 /// Selected instruction itineraries (one entry per itinerary class.) 144 InstrItineraryData InstrItins; 145 146 public: 147 enum { 148 isELF, isDarwin 149 } TargetType; 150 151 enum { 152 ARM_ABI_APCS, 153 ARM_ABI_AAPCS // ARM EABI 154 } TargetABI; 155 156 /// This constructor initializes the data members to match that 157 /// of the specified triple. 158 /// 159 ARMSubtarget(const std::string &TT, const std::string &CPU, 160 const std::string &FS, bool isThumb); 161 162 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 163 /// that still makes it profitable to inline the call. 164 unsigned getMaxInlineSizeThreshold() const { 165 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1. 166 // Change this once Thumb1 ldmia / stmia support is added. 167 return isThumb1Only() ? 0 : 64; 168 } 169 /// ParseSubtargetFeatures - Parses features string setting specified 170 /// subtarget options. Definition of function is auto generated by tblgen. 171 void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); 172 173 void computeIssueWidth(); 174 175 bool hasV4TOps() const { return ARMArchVersion >= V4T; } 176 bool hasV5TOps() const { return ARMArchVersion >= V5T; } 177 bool hasV5TEOps() const { return ARMArchVersion >= V5TE; } 178 bool hasV6Ops() const { return ARMArchVersion >= V6; } 179 bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } 180 bool hasV7Ops() const { return ARMArchVersion >= V7A; } 181 182 bool isCortexA8() const { return ARMProcFamily == CortexA8; } 183 bool isCortexA9() const { return ARMProcFamily == CortexA9; } 184 185 bool hasARMOps() const { return !NoARM; } 186 187 bool hasVFP2() const { return ARMFPUType >= VFPv2; } 188 bool hasVFP3() const { return ARMFPUType >= VFPv3; } 189 bool hasNEON() const { return ARMFPUType >= NEON; } 190 bool useNEONForSinglePrecisionFP() const { 191 return hasNEON() && UseNEONForSinglePrecisionFP; } 192 bool hasDivide() const { return HasHardwareDivide; } 193 bool hasT2ExtractPack() const { return HasT2ExtractPack; } 194 bool hasDataBarrier() const { return HasDataBarrier; } 195 bool useFPVMLx() const { return !SlowFPVMLx; } 196 bool hasVMLxForwarding() const { return HasVMLxForwarding; } 197 bool isFPBrccSlow() const { return SlowFPBrcc; } 198 bool isFPOnlySP() const { return FPOnlySP; } 199 bool prefers32BitThumb() const { return Pref32BitThumb; } 200 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; } 201 bool hasMPExtension() const { return HasMPExtension; } 202 203 bool hasFP16() const { return HasFP16; } 204 bool hasD16() const { return HasD16; } 205 206 const Triple &getTargetTriple() const { return TargetTriple; } 207 208 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 209 bool isTargetELF() const { return !isTargetDarwin(); } 210 211 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; } 212 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } 213 214 bool isThumb() const { return IsThumb; } 215 bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); } 216 bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); } 217 bool hasThumb2() const { return ThumbMode >= Thumb2; } 218 219 bool isR9Reserved() const { return IsR9Reserved; } 220 221 bool useMovt() const { return UseMovt && hasV6T2Ops(); } 222 223 bool allowsUnalignedMem() const { return AllowsUnalignedMem; } 224 225 const std::string & getCPUString() const { return CPUString; } 226 227 unsigned getMispredictionPenalty() const; 228 229 /// enablePostRAScheduler - True at 'More' optimization. 230 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 231 TargetSubtargetInfo::AntiDepBreakMode& Mode, 232 RegClassVector& CriticalPathRCs) const; 233 234 /// getInstrItins - Return the instruction itineraies based on subtarget 235 /// selection. 236 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } 237 238 /// getStackAlignment - Returns the minimum alignment known to hold of the 239 /// stack frame on entry to the function and which must be maintained by every 240 /// function for this subtarget. 241 unsigned getStackAlignment() const { return stackAlignment; } 242 243 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect 244 /// symbol. 245 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const; 246}; 247} // End llvm namespace 248 249#endif // ARMSUBTARGET_H 250