Thumb1RegisterInfo.cpp revision 65c58daa8b8985d2116216043103009815a55e77 
1//===- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-1 implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMMachineFunctionInfo.h"
18#include "ARMSubtarget.h"
19#include "Thumb1InstrInfo.h"
20#include "Thumb1RegisterInfo.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/Target/TargetFrameInfo.h"
32#include "llvm/Target/TargetMachine.h"
33#include "llvm/ADT/BitVector.h"
34#include "llvm/ADT/SmallVector.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38using namespace llvm;
39
40Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
41                                       const ARMSubtarget &sti)
42  : ARMBaseRegisterInfo(tii, sti) {
43}
44
45/// emitLoadConstPool - Emits a load from constpool to materialize the
46/// specified immediate.
47void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
48                                           MachineBasicBlock::iterator &MBBI,
49                                           DebugLoc dl,
50                                           unsigned DestReg, unsigned SubIdx,
51                                           int Val,
52                                           ARMCC::CondCodes Pred,
53                                           unsigned PredReg) const {
54  MachineFunction &MF = *MBB.getParent();
55  MachineConstantPool *ConstantPool = MF.getConstantPool();
56  Constant *C = ConstantInt::get(
57          Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
58  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
59
60  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp))
61          .addReg(DestReg, getDefRegState(true), SubIdx)
62          .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
63}
64
65const TargetRegisterClass*
66Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
67  if (isARMLowRegister(Reg))
68    return ARM::tGPRRegisterClass;
69  switch (Reg) {
70   default:
71    break;
72   case ARM::R8:  case ARM::R9:  case ARM::R10:  case ARM::R11:
73   case ARM::R12: case ARM::SP:  case ARM::LR:   case ARM::PC:
74    return ARM::GPRRegisterClass;
75  }
76
77  return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
78}
79
80bool
81Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
82  return true;
83}
84
85bool
86Thumb1RegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF)
87  const {
88  return true;
89}
90
91
92bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
93  const MachineFrameInfo *FFI = MF.getFrameInfo();
94  unsigned CFSize = FFI->getMaxCallFrameSize();
95  // It's not always a good idea to include the call frame as part of the
96  // stack frame. ARM (especially Thumb) has small immediate offset to
97  // address the stack frame. So a large call frame can cause poor codegen
98  // and may even makes it impossible to scavenge a register.
99  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
100    return false;
101
102  return !MF.getFrameInfo()->hasVarSizedObjects();
103}
104
105
106/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
107/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
108/// in a register using mov / mvn sequences or load the immediate from a
109/// constpool entry.
110static
111void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
112                              MachineBasicBlock::iterator &MBBI,
113                              unsigned DestReg, unsigned BaseReg,
114                              int NumBytes, bool CanChangeCC,
115                              const TargetInstrInfo &TII,
116                              const Thumb1RegisterInfo& MRI,
117                              DebugLoc dl) {
118    MachineFunction &MF = *MBB.getParent();
119    bool isHigh = !isARMLowRegister(DestReg) ||
120                  (BaseReg != 0 && !isARMLowRegister(BaseReg));
121    bool isSub = false;
122    // Subtract doesn't have high register version. Load the negative value
123    // if either base or dest register is a high register. Also, if do not
124    // issue sub as part of the sequence if condition register is to be
125    // preserved.
126    if (NumBytes < 0 && !isHigh && CanChangeCC) {
127      isSub = true;
128      NumBytes = -NumBytes;
129    }
130    unsigned LdReg = DestReg;
131    if (DestReg == ARM::SP) {
132      assert(BaseReg == ARM::SP && "Unexpected!");
133      LdReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
134    }
135
136    if (NumBytes <= 255 && NumBytes >= 0)
137      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
138        .addImm(NumBytes);
139    else if (NumBytes < 0 && NumBytes >= -255) {
140      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
141        .addImm(NumBytes);
142      AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
143        .addReg(LdReg, RegState::Kill);
144    } else
145      MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
146
147    // Emit add / sub.
148    int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
149    MachineInstrBuilder MIB =
150      BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
151    if (Opc != ARM::tADDhirr)
152      MIB = AddDefaultT1CC(MIB);
153    if (DestReg == ARM::SP || isSub)
154      MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
155    else
156      MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
157    AddDefaultPred(MIB);
158}
159
160/// calcNumMI - Returns the number of instructions required to materialize
161/// the specific add / sub r, c instruction.
162static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
163                          unsigned NumBits, unsigned Scale) {
164  unsigned NumMIs = 0;
165  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
166
167  if (Opc == ARM::tADDrSPi) {
168    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
169    Bytes -= ThisVal;
170    NumMIs++;
171    NumBits = 8;
172    Scale = 1;  // Followed by a number of tADDi8.
173    Chunk = ((1 << NumBits) - 1) * Scale;
174  }
175
176  NumMIs += Bytes / Chunk;
177  if ((Bytes % Chunk) != 0)
178    NumMIs++;
179  if (ExtraOpc)
180    NumMIs++;
181  return NumMIs;
182}
183
184/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
185/// a destreg = basereg + immediate in Thumb code.
186static
187void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
188                               MachineBasicBlock::iterator &MBBI,
189                               unsigned DestReg, unsigned BaseReg,
190                               int NumBytes, const TargetInstrInfo &TII,
191                               const Thumb1RegisterInfo& MRI,
192                               DebugLoc dl) {
193  bool isSub = NumBytes < 0;
194  unsigned Bytes = (unsigned)NumBytes;
195  if (isSub) Bytes = -NumBytes;
196  bool isMul4 = (Bytes & 3) == 0;
197  bool isTwoAddr = false;
198  bool DstNotEqBase = false;
199  unsigned NumBits = 1;
200  unsigned Scale = 1;
201  int Opc = 0;
202  int ExtraOpc = 0;
203  bool NeedCC = false;
204  bool NeedPred = false;
205
206  if (DestReg == BaseReg && BaseReg == ARM::SP) {
207    assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
208    NumBits = 7;
209    Scale = 4;
210    Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
211    isTwoAddr = true;
212  } else if (!isSub && BaseReg == ARM::SP) {
213    // r1 = add sp, 403
214    // =>
215    // r1 = add sp, 100 * 4
216    // r1 = add r1, 3
217    if (!isMul4) {
218      Bytes &= ~3;
219      ExtraOpc = ARM::tADDi3;
220    }
221    NumBits = 8;
222    Scale = 4;
223    Opc = ARM::tADDrSPi;
224  } else {
225    // sp = sub sp, c
226    // r1 = sub sp, c
227    // r8 = sub sp, c
228    if (DestReg != BaseReg)
229      DstNotEqBase = true;
230    NumBits = 8;
231    if (DestReg == ARM::SP) {
232      Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
233      assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
234      NumBits = 7;
235      Scale = 4;
236    } else {
237      Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
238      NumBits = 8;
239      NeedPred = NeedCC = true;
240    }
241    isTwoAddr = true;
242  }
243
244  unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
245  unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
246  if (NumMIs > Threshold) {
247    // This will expand into too many instructions. Load the immediate from a
248    // constpool entry.
249    emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII,
250                             MRI, dl);
251    return;
252  }
253
254  if (DstNotEqBase) {
255    if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
256      // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
257      unsigned Chunk = (1 << 3) - 1;
258      unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
259      Bytes -= ThisVal;
260      const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
261      const MachineInstrBuilder MIB =
262        AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
263      AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
264    } else {
265      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
266        .addReg(BaseReg, RegState::Kill);
267    }
268    BaseReg = DestReg;
269  }
270
271  unsigned Chunk = ((1 << NumBits) - 1) * Scale;
272  while (Bytes) {
273    unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
274    Bytes -= ThisVal;
275    ThisVal /= Scale;
276    // Build the new tADD / tSUB.
277    if (isTwoAddr) {
278      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
279      if (NeedCC)
280        MIB = AddDefaultT1CC(MIB);
281      MIB .addReg(DestReg).addImm(ThisVal);
282      if (NeedPred)
283        MIB = AddDefaultPred(MIB);
284    }
285    else {
286      bool isKill = BaseReg != ARM::SP;
287      MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
288      if (NeedCC)
289        MIB = AddDefaultT1CC(MIB);
290      MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
291      if (NeedPred)
292        MIB = AddDefaultPred(MIB);
293      BaseReg = DestReg;
294
295      if (Opc == ARM::tADDrSPi) {
296        // r4 = add sp, imm
297        // r4 = add r4, imm
298        // ...
299        NumBits = 8;
300        Scale = 1;
301        Chunk = ((1 << NumBits) - 1) * Scale;
302        Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
303        NeedPred = NeedCC = isTwoAddr = true;
304      }
305    }
306  }
307
308  if (ExtraOpc) {
309    const TargetInstrDesc &TID = TII.get(ExtraOpc);
310    AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
311                   .addReg(DestReg, RegState::Kill)
312                   .addImm(((unsigned)NumBytes) & 3));
313  }
314}
315
316static void emitSPUpdate(MachineBasicBlock &MBB,
317                         MachineBasicBlock::iterator &MBBI,
318                         const TargetInstrInfo &TII, DebugLoc dl,
319                         const Thumb1RegisterInfo &MRI,
320                         int NumBytes) {
321  emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
322                            MRI, dl);
323}
324
325void Thumb1RegisterInfo::
326eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
327                              MachineBasicBlock::iterator I) const {
328  if (!hasReservedCallFrame(MF)) {
329    // If we have alloca, convert as follows:
330    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
331    // ADJCALLSTACKUP   -> add, sp, sp, amount
332    MachineInstr *Old = I;
333    DebugLoc dl = Old->getDebugLoc();
334    unsigned Amount = Old->getOperand(0).getImm();
335    if (Amount != 0) {
336      // We need to keep the stack aligned properly.  To do this, we round the
337      // amount of space needed for the outgoing arguments up to the next
338      // alignment boundary.
339      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
340      Amount = (Amount+Align-1)/Align*Align;
341
342      // Replace the pseudo instruction with a new instruction...
343      unsigned Opc = Old->getOpcode();
344      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
345        emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
346      } else {
347        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
348        emitSPUpdate(MBB, I, TII, dl, *this, Amount);
349      }
350    }
351  }
352  MBB.erase(I);
353}
354
355/// emitThumbConstant - Emit a series of instructions to materialize a
356/// constant.
357static void emitThumbConstant(MachineBasicBlock &MBB,
358                              MachineBasicBlock::iterator &MBBI,
359                              unsigned DestReg, int Imm,
360                              const TargetInstrInfo &TII,
361                              const Thumb1RegisterInfo& MRI,
362                              DebugLoc dl) {
363  bool isSub = Imm < 0;
364  if (isSub) Imm = -Imm;
365
366  int Chunk = (1 << 8) - 1;
367  int ThisVal = (Imm > Chunk) ? Chunk : Imm;
368  Imm -= ThisVal;
369  AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
370                                        DestReg))
371                 .addImm(ThisVal));
372  if (Imm > 0)
373    emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
374  if (isSub) {
375    const TargetInstrDesc &TID = TII.get(ARM::tRSB);
376    AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
377                   .addReg(DestReg, RegState::Kill));
378  }
379}
380
381static void removeOperands(MachineInstr &MI, unsigned i) {
382  unsigned Op = i;
383  for (unsigned e = MI.getNumOperands(); i != e; ++i)
384    MI.RemoveOperand(Op);
385}
386
387int Thumb1RegisterInfo::
388rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
389                  unsigned FrameReg, int Offset,
390                  unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc) const
391{
392  // if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo
393  // version then can pull out Thumb1 specific parts here
394  return 0;
395}
396
397/// saveScavengerRegister - Save the register so it can be used by the
398/// register scavenger. Return true.
399bool Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
400                                               MachineBasicBlock::iterator I,
401                                               const TargetRegisterClass *RC,
402                                               unsigned Reg) const {
403  // Thumb1 can't use the emergency spill slot on the stack because
404  // ldr/str immediate offsets must be positive, and if we're referencing
405  // off the frame pointer (if, for example, there are alloca() calls in
406  // the function, the offset will be negative. Use R12 instead since that's
407  // a call clobbered register that we know won't be used in Thumb1 mode.
408
409  TII.copyRegToReg(MBB, I, ARM::R12, Reg, ARM::GPRRegisterClass, RC);
410  return true;
411}
412
413/// restoreScavengerRegister - restore a registers saved by
414// saveScavengerRegister().
415void Thumb1RegisterInfo::restoreScavengerRegister(MachineBasicBlock &MBB,
416                                               MachineBasicBlock::iterator I,
417                                               const TargetRegisterClass *RC,
418                                               unsigned Reg) const {
419  TII.copyRegToReg(MBB, I, Reg, ARM::R12, RC, ARM::GPRRegisterClass);
420}
421
422unsigned
423Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
424                                        int SPAdj, int *Value,
425                                        RegScavenger *RS) const{
426  unsigned VReg = 0;
427  unsigned i = 0;
428  MachineInstr &MI = *II;
429  MachineBasicBlock &MBB = *MI.getParent();
430  MachineFunction &MF = *MBB.getParent();
431  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
432  DebugLoc dl = MI.getDebugLoc();
433
434  while (!MI.getOperand(i).isFI()) {
435    ++i;
436    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
437  }
438
439  unsigned FrameReg = ARM::SP;
440  int FrameIndex = MI.getOperand(i).getIndex();
441  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
442               MF.getFrameInfo()->getStackSize() + SPAdj;
443
444  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
445    Offset -= AFI->getGPRCalleeSavedArea1Offset();
446  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
447    Offset -= AFI->getGPRCalleeSavedArea2Offset();
448  else if (hasFP(MF)) {
449    assert(SPAdj == 0 && "Unexpected");
450    // There is alloca()'s in this function, must reference off the frame
451    // pointer instead.
452    FrameReg = getFrameRegister(MF);
453    Offset -= AFI->getFramePtrSpillOffset();
454  }
455
456  unsigned Opcode = MI.getOpcode();
457  const TargetInstrDesc &Desc = MI.getDesc();
458  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
459
460  if (Opcode == ARM::tADDrSPi) {
461    Offset += MI.getOperand(i+1).getImm();
462
463    // Can't use tADDrSPi if it's based off the frame pointer.
464    unsigned NumBits = 0;
465    unsigned Scale = 1;
466    if (FrameReg != ARM::SP) {
467      Opcode = ARM::tADDi3;
468      MI.setDesc(TII.get(Opcode));
469      NumBits = 3;
470    } else {
471      NumBits = 8;
472      Scale = 4;
473      assert((Offset & 3) == 0 &&
474             "Thumb add/sub sp, #imm immediate must be multiple of 4!");
475    }
476
477    if (Offset == 0) {
478      // Turn it into a move.
479      MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
480      MI.getOperand(i).ChangeToRegister(FrameReg, false);
481      MI.RemoveOperand(i+1);
482      return 0;
483    }
484
485    // Common case: small offset, fits into instruction.
486    unsigned Mask = (1 << NumBits) - 1;
487    if (((Offset / Scale) & ~Mask) == 0) {
488      // Replace the FrameIndex with sp / fp
489      if (Opcode == ARM::tADDi3) {
490        removeOperands(MI, i);
491        MachineInstrBuilder MIB(&MI);
492        AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
493                       .addImm(Offset / Scale));
494      } else {
495        MI.getOperand(i).ChangeToRegister(FrameReg, false);
496        MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
497      }
498      return 0;
499    }
500
501    unsigned DestReg = MI.getOperand(0).getReg();
502    unsigned Bytes = (Offset > 0) ? Offset : -Offset;
503    unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
504    // MI would expand into a large number of instructions. Don't try to
505    // simplify the immediate.
506    if (NumMIs > 2) {
507      emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII,
508                                *this, dl);
509      MBB.erase(II);
510      return 0;
511    }
512
513    if (Offset > 0) {
514      // Translate r0 = add sp, imm to
515      // r0 = add sp, 255*4
516      // r0 = add r0, (imm - 255*4)
517      if (Opcode == ARM::tADDi3) {
518        removeOperands(MI, i);
519        MachineInstrBuilder MIB(&MI);
520        AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
521      } else {
522        MI.getOperand(i).ChangeToRegister(FrameReg, false);
523        MI.getOperand(i+1).ChangeToImmediate(Mask);
524      }
525      Offset = (Offset - Mask * Scale);
526      MachineBasicBlock::iterator NII = next(II);
527      emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII,
528                                *this, dl);
529    } else {
530      // Translate r0 = add sp, -imm to
531      // r0 = -imm (this is then translated into a series of instructons)
532      // r0 = add r0, sp
533      emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
534
535      MI.setDesc(TII.get(ARM::tADDhirr));
536      MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
537      MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
538      if (Opcode == ARM::tADDi3) {
539        MachineInstrBuilder MIB(&MI);
540        AddDefaultPred(MIB);
541      }
542    }
543    return 0;
544  } else {
545    unsigned ImmIdx = 0;
546    int InstrOffs = 0;
547    unsigned NumBits = 0;
548    unsigned Scale = 1;
549    switch (AddrMode) {
550    case ARMII::AddrModeT1_s: {
551      ImmIdx = i+1;
552      InstrOffs = MI.getOperand(ImmIdx).getImm();
553      NumBits = (FrameReg == ARM::SP) ? 8 : 5;
554      Scale = 4;
555      break;
556    }
557    default:
558      llvm_unreachable("Unsupported addressing mode!");
559      break;
560    }
561
562    Offset += InstrOffs * Scale;
563    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
564
565    // Common case: small offset, fits into instruction.
566    MachineOperand &ImmOp = MI.getOperand(ImmIdx);
567    int ImmedOffset = Offset / Scale;
568    unsigned Mask = (1 << NumBits) - 1;
569    if ((unsigned)Offset <= Mask * Scale) {
570      // Replace the FrameIndex with sp
571      MI.getOperand(i).ChangeToRegister(FrameReg, false);
572      ImmOp.ChangeToImmediate(ImmedOffset);
573      return 0;
574    }
575
576    bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
577    if (AddrMode == ARMII::AddrModeT1_s) {
578      // Thumb tLDRspi, tSTRspi. These will change to instructions that use
579      // a different base register.
580      NumBits = 5;
581      Mask = (1 << NumBits) - 1;
582    }
583    // If this is a thumb spill / restore, we will be using a constpool load to
584    // materialize the offset.
585    if (AddrMode == ARMII::AddrModeT1_s && isThumSpillRestore)
586      ImmOp.ChangeToImmediate(0);
587    else {
588      // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
589      ImmedOffset = ImmedOffset & Mask;
590      ImmOp.ChangeToImmediate(ImmedOffset);
591      Offset &= ~(Mask*Scale);
592    }
593  }
594
595  // If we get here, the immediate doesn't fit into the instruction.  We folded
596  // as much as possible above, handle the rest, providing a register that is
597  // SP+LargeImm.
598  assert(Offset && "This code isn't needed if offset already handled!");
599
600  // Remove predicate first.
601  int PIdx = MI.findFirstPredOperandIdx();
602  if (PIdx != -1)
603    removeOperands(MI, PIdx);
604
605  if (Desc.mayLoad()) {
606    // Use the destination register to materialize sp + offset.
607    unsigned TmpReg = MI.getOperand(0).getReg();
608    bool UseRR = false;
609    if (Opcode == ARM::tRestore) {
610      if (FrameReg == ARM::SP)
611        emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
612                                 Offset, false, TII, *this, dl);
613      else {
614        emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
615        UseRR = true;
616      }
617    } else {
618      emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII,
619                                *this, dl);
620    }
621
622    MI.setDesc(TII.get(ARM::tLDR));
623    MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
624    if (UseRR)
625      // Use [reg, reg] addrmode.
626      MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
627    else  // tLDR has an extra register operand.
628      MI.addOperand(MachineOperand::CreateReg(0, false));
629  } else if (Desc.mayStore()) {
630      VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
631      assert (Value && "Frame index virtual allocated, but Value arg is NULL!");
632      *Value = Offset;
633      bool UseRR = false;
634
635      if (Opcode == ARM::tSpill) {
636        if (FrameReg == ARM::SP)
637          emitThumbRegPlusImmInReg(MBB, II, VReg, FrameReg,
638                                   Offset, false, TII, *this, dl);
639        else {
640          emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
641          UseRR = true;
642        }
643      } else
644        emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
645                                  *this, dl);
646      MI.setDesc(TII.get(ARM::tSTR));
647      MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
648      if (UseRR)  // Use [reg, reg] addrmode.
649        MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
650      else // tSTR has an extra register operand.
651        MI.addOperand(MachineOperand::CreateReg(0, false));
652  } else
653    assert(false && "Unexpected opcode!");
654
655  // Add predicate back if it's needed.
656  if (MI.getDesc().isPredicable()) {
657    MachineInstrBuilder MIB(&MI);
658    AddDefaultPred(MIB);
659  }
660  return VReg;
661}
662
663void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
664  MachineBasicBlock &MBB = MF.front();
665  MachineBasicBlock::iterator MBBI = MBB.begin();
666  MachineFrameInfo  *MFI = MF.getFrameInfo();
667  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
668  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
669  unsigned NumBytes = MFI->getStackSize();
670  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
671  DebugLoc dl = (MBBI != MBB.end() ?
672                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
673
674  // Check if R3 is live in. It might have to be used as a scratch register.
675  for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
676         E = MF.getRegInfo().livein_end(); I != E; ++I) {
677    if (I->first == ARM::R3) {
678      AFI->setR3IsLiveIn(true);
679      break;
680    }
681  }
682
683  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
684  NumBytes = (NumBytes + 3) & ~3;
685  MFI->setStackSize(NumBytes);
686
687  // Determine the sizes of each callee-save spill areas and record which frame
688  // belongs to which callee-save spill areas.
689  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
690  int FramePtrSpillFI = 0;
691
692  if (VARegSaveSize)
693    emitSPUpdate(MBB, MBBI, TII, dl, *this, -VARegSaveSize);
694
695  if (!AFI->hasStackFrame()) {
696    if (NumBytes != 0)
697      emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
698    return;
699  }
700
701  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
702    unsigned Reg = CSI[i].getReg();
703    int FI = CSI[i].getFrameIdx();
704    switch (Reg) {
705    case ARM::R4:
706    case ARM::R5:
707    case ARM::R6:
708    case ARM::R7:
709    case ARM::LR:
710      if (Reg == FramePtr)
711        FramePtrSpillFI = FI;
712      AFI->addGPRCalleeSavedArea1Frame(FI);
713      GPRCS1Size += 4;
714      break;
715    case ARM::R8:
716    case ARM::R9:
717    case ARM::R10:
718    case ARM::R11:
719      if (Reg == FramePtr)
720        FramePtrSpillFI = FI;
721      if (STI.isTargetDarwin()) {
722        AFI->addGPRCalleeSavedArea2Frame(FI);
723        GPRCS2Size += 4;
724      } else {
725        AFI->addGPRCalleeSavedArea1Frame(FI);
726        GPRCS1Size += 4;
727      }
728      break;
729    default:
730      AFI->addDPRCalleeSavedAreaFrame(FI);
731      DPRCSSize += 8;
732    }
733  }
734
735  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
736    ++MBBI;
737    if (MBBI != MBB.end())
738      dl = MBBI->getDebugLoc();
739  }
740
741  // Darwin ABI requires FP to point to the stack slot that contains the
742  // previous FP.
743  if (STI.isTargetDarwin() || hasFP(MF)) {
744    BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
745      .addFrameIndex(FramePtrSpillFI).addImm(0);
746  }
747
748  // Determine starting offsets of spill areas.
749  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
750  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
751  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
752  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
753  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
754  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
755  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
756
757  NumBytes = DPRCSOffset;
758  if (NumBytes) {
759    // Insert it after all the callee-save spills.
760    emitSPUpdate(MBB, MBBI, TII, dl, *this, -NumBytes);
761  }
762
763  if (STI.isTargetELF() && hasFP(MF)) {
764    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
765                             AFI->getFramePtrSpillOffset());
766  }
767
768  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
769  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
770  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
771}
772
773static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
774  for (unsigned i = 0; CSRegs[i]; ++i)
775    if (Reg == CSRegs[i])
776      return true;
777  return false;
778}
779
780static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
781  return (MI->getOpcode() == ARM::tRestore &&
782          MI->getOperand(1).isFI() &&
783          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
784}
785
786void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
787                                      MachineBasicBlock &MBB) const {
788  MachineBasicBlock::iterator MBBI = prior(MBB.end());
789  assert((MBBI->getOpcode() == ARM::tBX_RET ||
790          MBBI->getOpcode() == ARM::tPOP_RET) &&
791         "Can only insert epilog into returning blocks");
792  DebugLoc dl = MBBI->getDebugLoc();
793  MachineFrameInfo *MFI = MF.getFrameInfo();
794  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
795  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
796  int NumBytes = (int)MFI->getStackSize();
797
798  if (!AFI->hasStackFrame()) {
799    if (NumBytes != 0)
800      emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
801  } else {
802    // Unwind MBBI to point to first LDR / FLDD.
803    const unsigned *CSRegs = getCalleeSavedRegs();
804    if (MBBI != MBB.begin()) {
805      do
806        --MBBI;
807      while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
808      if (!isCSRestore(MBBI, CSRegs))
809        ++MBBI;
810    }
811
812    // Move SP to start of FP callee save spill area.
813    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
814                 AFI->getGPRCalleeSavedArea2Size() +
815                 AFI->getDPRCalleeSavedAreaSize());
816
817    if (hasFP(MF)) {
818      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
819      // Reset SP based on frame pointer only if the stack frame extends beyond
820      // frame pointer stack slot or target is ELF and the function has FP.
821      if (NumBytes)
822        emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes,
823                                  TII, *this, dl);
824      else
825        BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
826          .addReg(FramePtr);
827    } else {
828      if (MBBI->getOpcode() == ARM::tBX_RET &&
829          &MBB.front() != MBBI &&
830          prior(MBBI)->getOpcode() == ARM::tPOP) {
831        MachineBasicBlock::iterator PMBBI = prior(MBBI);
832        emitSPUpdate(MBB, PMBBI, TII, dl, *this, NumBytes);
833      } else
834        emitSPUpdate(MBB, MBBI, TII, dl, *this, NumBytes);
835    }
836  }
837
838  if (VARegSaveSize) {
839    // Epilogue for vararg functions: pop LR to R3 and branch off it.
840    // FIXME: Verify this is still ok when R3 is no longer being reserved.
841    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
842      .addReg(0) // No write back.
843      .addReg(ARM::R3, RegState::Define);
844
845    emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);
846
847    BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
848      .addReg(ARM::R3, RegState::Kill);
849    MBB.erase(MBBI);
850  }
851}
852