MSP430ISelLowering.cpp revision 5b3fca50a08865f0db55fc92ad1c037a04e12177 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430Subtarget.h"
20#include "MSP430TargetMachine.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/SelectionDAGISel.h"
27#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28#include "llvm/CodeGen/ValueTypes.h"
29#include "llvm/IR/CallingConv.h"
30#include "llvm/IR/DerivedTypes.h"
31#include "llvm/IR/Function.h"
32#include "llvm/IR/GlobalAlias.h"
33#include "llvm/IR/GlobalVariable.h"
34#include "llvm/IR/Intrinsics.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39using namespace llvm;
40
41typedef enum {
42  NoHWMult,
43  HWMultIntr,
44  HWMultNoIntr
45} HWMultUseMode;
46
47static cl::opt<HWMultUseMode>
48HWMultMode("msp430-hwmult-mode",
49           cl::desc("Hardware multiplier use mode"),
50           cl::init(HWMultNoIntr),
51           cl::values(
52             clEnumValN(NoHWMult, "no",
53                "Do not use hardware multiplier"),
54             clEnumValN(HWMultIntr, "interrupts",
55                "Assume hardware multiplier can be used inside interrupts"),
56             clEnumValN(HWMultNoIntr, "use",
57                "Assume hardware multiplier cannot be used inside interrupts"),
58             clEnumValEnd));
59
60MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
61  TargetLowering(tm, new TargetLoweringObjectFileELF()),
62  Subtarget(*tm.getSubtargetImpl()) {
63
64  TD = getDataLayout();
65
66  // Set up the register classes.
67  addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
68  addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
69
70  // Compute derived properties from the register classes
71  computeRegisterProperties();
72
73  // Provide all sorts of operation actions
74
75  // Division is expensive
76  setIntDivIsCheap(false);
77
78  setStackPointerRegisterToSaveRestore(MSP430::SPW);
79  setBooleanContents(ZeroOrOneBooleanContent);
80  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
81
82  // We have post-incremented loads / stores.
83  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
84  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
85
86  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
87  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
88  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
89  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
90  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
91
92  // We don't have any truncstores
93  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
94
95  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
96  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
97  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
98  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
99  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
100  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
101  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
102  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
103  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
104  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
105  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
106  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
107  setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
108  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
109  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
110  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
111  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
112  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
113  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
114  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
115  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
116  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
117  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
118  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
119  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
120  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
121
122  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
123  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
124  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i8,    Expand);
125  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i16,   Expand);
126  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
127  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
128  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i8,    Expand);
129  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i16,   Expand);
130  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
131  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
132
133  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
134  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
135  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
136  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
137  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
138  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
139
140  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
141
142  // FIXME: Implement efficiently multiplication by a constant
143  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
144  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
145  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
146  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
147  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
148  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
149  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
150  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
151  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
152  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
153
154  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
155  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
156  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
157  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
158  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
159  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
160  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
161  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
162  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
163  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
164  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
165  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
166
167  // varargs support
168  setOperationAction(ISD::VASTART,          MVT::Other, Custom);
169  setOperationAction(ISD::VAARG,            MVT::Other, Expand);
170  setOperationAction(ISD::VAEND,            MVT::Other, Expand);
171  setOperationAction(ISD::VACOPY,           MVT::Other, Expand);
172
173  // Libcalls names.
174  if (HWMultMode == HWMultIntr) {
175    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
176    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
177  } else if (HWMultMode == HWMultNoIntr) {
178    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
179    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
180  }
181
182  setMinFunctionAlignment(1);
183  setPrefFunctionAlignment(2);
184}
185
186SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
187                                             SelectionDAG &DAG) const {
188  switch (Op.getOpcode()) {
189  case ISD::SHL: // FALLTHROUGH
190  case ISD::SRL:
191  case ISD::SRA:              return LowerShifts(Op, DAG);
192  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
193  case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
194  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
195  case ISD::SETCC:            return LowerSETCC(Op, DAG);
196  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
197  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
198  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
199  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
200  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
201  case ISD::VASTART:          return LowerVASTART(Op, DAG);
202  default:
203    llvm_unreachable("unimplemented operand");
204  }
205}
206
207//===----------------------------------------------------------------------===//
208//                       MSP430 Inline Assembly Support
209//===----------------------------------------------------------------------===//
210
211/// getConstraintType - Given a constraint letter, return the type of
212/// constraint it is for this target.
213TargetLowering::ConstraintType
214MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
215  if (Constraint.size() == 1) {
216    switch (Constraint[0]) {
217    case 'r':
218      return C_RegisterClass;
219    default:
220      break;
221    }
222  }
223  return TargetLowering::getConstraintType(Constraint);
224}
225
226std::pair<unsigned, const TargetRegisterClass*>
227MSP430TargetLowering::
228getRegForInlineAsmConstraint(const std::string &Constraint,
229                             MVT VT) const {
230  if (Constraint.size() == 1) {
231    // GCC Constraint Letters
232    switch (Constraint[0]) {
233    default: break;
234    case 'r':   // GENERAL_REGS
235      if (VT == MVT::i8)
236        return std::make_pair(0U, &MSP430::GR8RegClass);
237
238      return std::make_pair(0U, &MSP430::GR16RegClass);
239    }
240  }
241
242  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
243}
244
245//===----------------------------------------------------------------------===//
246//                      Calling Convention Implementation
247//===----------------------------------------------------------------------===//
248
249#include "MSP430GenCallingConv.inc"
250
251SDValue
252MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
253                                           CallingConv::ID CallConv,
254                                           bool isVarArg,
255                                           const SmallVectorImpl<ISD::InputArg>
256                                             &Ins,
257                                           SDLoc dl,
258                                           SelectionDAG &DAG,
259                                           SmallVectorImpl<SDValue> &InVals)
260                                             const {
261
262  switch (CallConv) {
263  default:
264    llvm_unreachable("Unsupported calling convention");
265  case CallingConv::C:
266  case CallingConv::Fast:
267    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
268  case CallingConv::MSP430_INTR:
269    if (Ins.empty())
270      return Chain;
271    report_fatal_error("ISRs cannot have arguments");
272  }
273}
274
275SDValue
276MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
277                                SmallVectorImpl<SDValue> &InVals) const {
278  SelectionDAG &DAG                     = CLI.DAG;
279  SDLoc &dl                             = CLI.DL;
280  SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
281  SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;
282  SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;
283  SDValue Chain                         = CLI.Chain;
284  SDValue Callee                        = CLI.Callee;
285  bool &isTailCall                      = CLI.IsTailCall;
286  CallingConv::ID CallConv              = CLI.CallConv;
287  bool isVarArg                         = CLI.IsVarArg;
288
289  // MSP430 target does not yet support tail call optimization.
290  isTailCall = false;
291
292  switch (CallConv) {
293  default:
294    llvm_unreachable("Unsupported calling convention");
295  case CallingConv::Fast:
296  case CallingConv::C:
297    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
298                          Outs, OutVals, Ins, dl, DAG, InVals);
299  case CallingConv::MSP430_INTR:
300    report_fatal_error("ISRs cannot be called directly");
301  }
302}
303
304/// LowerCCCArguments - transform physical registers into virtual registers and
305/// generate load operations for arguments places on the stack.
306// FIXME: struct return stuff
307SDValue
308MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
309                                        CallingConv::ID CallConv,
310                                        bool isVarArg,
311                                        const SmallVectorImpl<ISD::InputArg>
312                                          &Ins,
313                                        SDLoc dl,
314                                        SelectionDAG &DAG,
315                                        SmallVectorImpl<SDValue> &InVals)
316                                          const {
317  MachineFunction &MF = DAG.getMachineFunction();
318  MachineFrameInfo *MFI = MF.getFrameInfo();
319  MachineRegisterInfo &RegInfo = MF.getRegInfo();
320  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
321
322  // Assign locations to all of the incoming arguments.
323  SmallVector<CCValAssign, 16> ArgLocs;
324  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
325                 getTargetMachine(), ArgLocs, *DAG.getContext());
326  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
327
328  // Create frame index for the start of the first vararg value
329  if (isVarArg) {
330    unsigned Offset = CCInfo.getNextStackOffset();
331    FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, Offset, true));
332  }
333
334  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
335    CCValAssign &VA = ArgLocs[i];
336    if (VA.isRegLoc()) {
337      // Arguments passed in registers
338      EVT RegVT = VA.getLocVT();
339      switch (RegVT.getSimpleVT().SimpleTy) {
340      default:
341        {
342#ifndef NDEBUG
343          errs() << "LowerFormalArguments Unhandled argument type: "
344               << RegVT.getSimpleVT().SimpleTy << "\n";
345#endif
346          llvm_unreachable(0);
347        }
348      case MVT::i16:
349        unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
350        RegInfo.addLiveIn(VA.getLocReg(), VReg);
351        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
352
353        // If this is an 8-bit value, it is really passed promoted to 16
354        // bits. Insert an assert[sz]ext to capture this, then truncate to the
355        // right size.
356        if (VA.getLocInfo() == CCValAssign::SExt)
357          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
358                                 DAG.getValueType(VA.getValVT()));
359        else if (VA.getLocInfo() == CCValAssign::ZExt)
360          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
361                                 DAG.getValueType(VA.getValVT()));
362
363        if (VA.getLocInfo() != CCValAssign::Full)
364          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
365
366        InVals.push_back(ArgValue);
367      }
368    } else {
369      // Sanity check
370      assert(VA.isMemLoc());
371
372      SDValue InVal;
373      ISD::ArgFlagsTy Flags = Ins[i].Flags;
374
375      if (Flags.isByVal()) {
376        int FI = MFI->CreateFixedObject(Flags.getByValSize(),
377                                        VA.getLocMemOffset(), true);
378        InVal = DAG.getFrameIndex(FI, getPointerTy());
379      } else {
380        // Load the argument to a virtual register
381        unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
382        if (ObjSize > 2) {
383            errs() << "LowerFormalArguments Unhandled argument type: "
384                << EVT(VA.getLocVT()).getEVTString()
385                << "\n";
386        }
387        // Create the frame index object for this incoming parameter...
388        int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
389
390        // Create the SelectionDAG nodes corresponding to a load
391        //from this parameter
392        SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
393        InVal = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
394                            MachinePointerInfo::getFixedStack(FI),
395                            false, false, false, 0);
396      }
397
398      InVals.push_back(InVal);
399    }
400  }
401
402  return Chain;
403}
404
405SDValue
406MSP430TargetLowering::LowerReturn(SDValue Chain,
407                                  CallingConv::ID CallConv, bool isVarArg,
408                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
409                                  const SmallVectorImpl<SDValue> &OutVals,
410                                  SDLoc dl, SelectionDAG &DAG) const {
411
412  // CCValAssign - represent the assignment of the return value to a location
413  SmallVector<CCValAssign, 16> RVLocs;
414
415  // ISRs cannot return any value.
416  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
417    report_fatal_error("ISRs cannot return any value");
418
419  // CCState - Info about the registers and stack slot.
420  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
421                 getTargetMachine(), RVLocs, *DAG.getContext());
422
423  // Analize return values.
424  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
425
426  SDValue Flag;
427  SmallVector<SDValue, 4> RetOps(1, Chain);
428
429  // Copy the result values into the output registers.
430  for (unsigned i = 0; i != RVLocs.size(); ++i) {
431    CCValAssign &VA = RVLocs[i];
432    assert(VA.isRegLoc() && "Can only return in registers!");
433
434    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
435                             OutVals[i], Flag);
436
437    // Guarantee that all emitted copies are stuck together,
438    // avoiding something bad.
439    Flag = Chain.getValue(1);
440    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
441  }
442
443  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
444                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
445
446  RetOps[0] = Chain;  // Update chain.
447
448  // Add the flag if we have it.
449  if (Flag.getNode())
450    RetOps.push_back(Flag);
451
452  return DAG.getNode(Opc, dl, MVT::Other, &RetOps[0], RetOps.size());
453}
454
455/// LowerCCCCallTo - functions arguments are copied from virtual regs to
456/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
457/// TODO: sret.
458SDValue
459MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
460                                     CallingConv::ID CallConv, bool isVarArg,
461                                     bool isTailCall,
462                                     const SmallVectorImpl<ISD::OutputArg>
463                                       &Outs,
464                                     const SmallVectorImpl<SDValue> &OutVals,
465                                     const SmallVectorImpl<ISD::InputArg> &Ins,
466                                     SDLoc dl, SelectionDAG &DAG,
467                                     SmallVectorImpl<SDValue> &InVals) const {
468  // Analyze operands of the call, assigning locations to each operand.
469  SmallVector<CCValAssign, 16> ArgLocs;
470  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
471                 getTargetMachine(), ArgLocs, *DAG.getContext());
472
473  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
474
475  // Get a count of how many bytes are to be pushed on the stack.
476  unsigned NumBytes = CCInfo.getNextStackOffset();
477
478  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
479                                                      getPointerTy(), true),
480                               dl);
481
482  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
483  SmallVector<SDValue, 12> MemOpChains;
484  SDValue StackPtr;
485
486  // Walk the register/memloc assignments, inserting copies/loads.
487  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
488    CCValAssign &VA = ArgLocs[i];
489
490    SDValue Arg = OutVals[i];
491
492    // Promote the value if needed.
493    switch (VA.getLocInfo()) {
494      default: llvm_unreachable("Unknown loc info!");
495      case CCValAssign::Full: break;
496      case CCValAssign::SExt:
497        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
498        break;
499      case CCValAssign::ZExt:
500        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
501        break;
502      case CCValAssign::AExt:
503        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
504        break;
505    }
506
507    // Arguments that can be passed on register must be kept at RegsToPass
508    // vector
509    if (VA.isRegLoc()) {
510      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
511    } else {
512      assert(VA.isMemLoc());
513
514      if (StackPtr.getNode() == 0)
515        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
516
517      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
518                                   StackPtr,
519                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
520
521      SDValue MemOp;
522      ISD::ArgFlagsTy Flags = Outs[i].Flags;
523
524      if (Flags.isByVal()) {
525        SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i16);
526        MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
527                              Flags.getByValAlign(),
528                              /*isVolatile*/false,
529                              /*AlwaysInline=*/true,
530                              MachinePointerInfo(),
531                              MachinePointerInfo());
532      } else {
533        MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(),
534                             false, false, 0);
535      }
536
537      MemOpChains.push_back(MemOp);
538    }
539  }
540
541  // Transform all store nodes into one single node because all store nodes are
542  // independent of each other.
543  if (!MemOpChains.empty())
544    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
545                        &MemOpChains[0], MemOpChains.size());
546
547  // Build a sequence of copy-to-reg nodes chained together with token chain and
548  // flag operands which copy the outgoing args into registers.  The InFlag in
549  // necessary since all emitted instructions must be stuck together.
550  SDValue InFlag;
551  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
552    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
553                             RegsToPass[i].second, InFlag);
554    InFlag = Chain.getValue(1);
555  }
556
557  // If the callee is a GlobalAddress node (quite common, every direct call is)
558  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
559  // Likewise ExternalSymbol -> TargetExternalSymbol.
560  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
561    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
562  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
563    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
564
565  // Returns a chain & a flag for retval copy to use.
566  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
567  SmallVector<SDValue, 8> Ops;
568  Ops.push_back(Chain);
569  Ops.push_back(Callee);
570
571  // Add argument registers to the end of the list so that they are
572  // known live into the call.
573  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
574    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
575                                  RegsToPass[i].second.getValueType()));
576
577  if (InFlag.getNode())
578    Ops.push_back(InFlag);
579
580  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
581  InFlag = Chain.getValue(1);
582
583  // Create the CALLSEQ_END node.
584  Chain = DAG.getCALLSEQ_END(Chain,
585                             DAG.getConstant(NumBytes, getPointerTy(), true),
586                             DAG.getConstant(0, getPointerTy(), true),
587                             InFlag, dl);
588  InFlag = Chain.getValue(1);
589
590  // Handle result values, copying them out of physregs into vregs that we
591  // return.
592  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
593                         DAG, InVals);
594}
595
596/// LowerCallResult - Lower the result values of a call into the
597/// appropriate copies out of appropriate physical registers.
598///
599SDValue
600MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
601                                      CallingConv::ID CallConv, bool isVarArg,
602                                      const SmallVectorImpl<ISD::InputArg> &Ins,
603                                      SDLoc dl, SelectionDAG &DAG,
604                                      SmallVectorImpl<SDValue> &InVals) const {
605
606  // Assign locations to each value returned by this call.
607  SmallVector<CCValAssign, 16> RVLocs;
608  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
609                 getTargetMachine(), RVLocs, *DAG.getContext());
610
611  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
612
613  // Copy all of the result registers out of their specified physreg.
614  for (unsigned i = 0; i != RVLocs.size(); ++i) {
615    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
616                               RVLocs[i].getValVT(), InFlag).getValue(1);
617    InFlag = Chain.getValue(2);
618    InVals.push_back(Chain.getValue(0));
619  }
620
621  return Chain;
622}
623
624SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
625                                          SelectionDAG &DAG) const {
626  unsigned Opc = Op.getOpcode();
627  SDNode* N = Op.getNode();
628  EVT VT = Op.getValueType();
629  SDLoc dl(N);
630
631  // Expand non-constant shifts to loops:
632  if (!isa<ConstantSDNode>(N->getOperand(1)))
633    switch (Opc) {
634    default: llvm_unreachable("Invalid shift opcode!");
635    case ISD::SHL:
636      return DAG.getNode(MSP430ISD::SHL, dl,
637                         VT, N->getOperand(0), N->getOperand(1));
638    case ISD::SRA:
639      return DAG.getNode(MSP430ISD::SRA, dl,
640                         VT, N->getOperand(0), N->getOperand(1));
641    case ISD::SRL:
642      return DAG.getNode(MSP430ISD::SRL, dl,
643                         VT, N->getOperand(0), N->getOperand(1));
644    }
645
646  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
647
648  // Expand the stuff into sequence of shifts.
649  // FIXME: for some shift amounts this might be done better!
650  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
651  SDValue Victim = N->getOperand(0);
652
653  if (Opc == ISD::SRL && ShiftAmount) {
654    // Emit a special goodness here:
655    // srl A, 1 => clrc; rrc A
656    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
657    ShiftAmount -= 1;
658  }
659
660  while (ShiftAmount--)
661    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
662                         dl, VT, Victim);
663
664  return Victim;
665}
666
667SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
668                                                 SelectionDAG &DAG) const {
669  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
670  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
671
672  // Create the TargetGlobalAddress node, folding in the constant offset.
673  SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
674                                              getPointerTy(), Offset);
675  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op),
676                     getPointerTy(), Result);
677}
678
679SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
680                                                  SelectionDAG &DAG) const {
681  SDLoc dl(Op);
682  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
683  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
684
685  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
686}
687
688SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
689                                                SelectionDAG &DAG) const {
690  SDLoc dl(Op);
691  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
692  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy());
693
694  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
695}
696
697static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
698                       ISD::CondCode CC,
699                       SDLoc dl, SelectionDAG &DAG) {
700  // FIXME: Handle bittests someday
701  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
702
703  // FIXME: Handle jump negative someday
704  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
705  switch (CC) {
706  default: llvm_unreachable("Invalid integer condition!");
707  case ISD::SETEQ:
708    TCC = MSP430CC::COND_E;     // aka COND_Z
709    // Minor optimization: if LHS is a constant, swap operands, then the
710    // constant can be folded into comparison.
711    if (LHS.getOpcode() == ISD::Constant)
712      std::swap(LHS, RHS);
713    break;
714  case ISD::SETNE:
715    TCC = MSP430CC::COND_NE;    // aka COND_NZ
716    // Minor optimization: if LHS is a constant, swap operands, then the
717    // constant can be folded into comparison.
718    if (LHS.getOpcode() == ISD::Constant)
719      std::swap(LHS, RHS);
720    break;
721  case ISD::SETULE:
722    std::swap(LHS, RHS);        // FALLTHROUGH
723  case ISD::SETUGE:
724    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
725    // fold constant into instruction.
726    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
727      LHS = RHS;
728      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
729      TCC = MSP430CC::COND_LO;
730      break;
731    }
732    TCC = MSP430CC::COND_HS;    // aka COND_C
733    break;
734  case ISD::SETUGT:
735    std::swap(LHS, RHS);        // FALLTHROUGH
736  case ISD::SETULT:
737    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
738    // fold constant into instruction.
739    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
740      LHS = RHS;
741      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
742      TCC = MSP430CC::COND_HS;
743      break;
744    }
745    TCC = MSP430CC::COND_LO;    // aka COND_NC
746    break;
747  case ISD::SETLE:
748    std::swap(LHS, RHS);        // FALLTHROUGH
749  case ISD::SETGE:
750    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
751    // fold constant into instruction.
752    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
753      LHS = RHS;
754      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
755      TCC = MSP430CC::COND_L;
756      break;
757    }
758    TCC = MSP430CC::COND_GE;
759    break;
760  case ISD::SETGT:
761    std::swap(LHS, RHS);        // FALLTHROUGH
762  case ISD::SETLT:
763    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
764    // fold constant into instruction.
765    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
766      LHS = RHS;
767      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
768      TCC = MSP430CC::COND_GE;
769      break;
770    }
771    TCC = MSP430CC::COND_L;
772    break;
773  }
774
775  TargetCC = DAG.getConstant(TCC, MVT::i8);
776  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
777}
778
779
780SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
781  SDValue Chain = Op.getOperand(0);
782  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
783  SDValue LHS   = Op.getOperand(2);
784  SDValue RHS   = Op.getOperand(3);
785  SDValue Dest  = Op.getOperand(4);
786  SDLoc dl  (Op);
787
788  SDValue TargetCC;
789  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
790
791  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
792                     Chain, Dest, TargetCC, Flag);
793}
794
795SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
796  SDValue LHS   = Op.getOperand(0);
797  SDValue RHS   = Op.getOperand(1);
798  SDLoc dl  (Op);
799
800  // If we are doing an AND and testing against zero, then the CMP
801  // will not be generated.  The AND (or BIT) will generate the condition codes,
802  // but they are different from CMP.
803  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
804  // lowering & isel wouldn't diverge.
805  bool andCC = false;
806  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
807    if (RHSC->isNullValue() && LHS.hasOneUse() &&
808        (LHS.getOpcode() == ISD::AND ||
809         (LHS.getOpcode() == ISD::TRUNCATE &&
810          LHS.getOperand(0).getOpcode() == ISD::AND))) {
811      andCC = true;
812    }
813  }
814  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
815  SDValue TargetCC;
816  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
817
818  // Get the condition codes directly from the status register, if its easy.
819  // Otherwise a branch will be generated.  Note that the AND and BIT
820  // instructions generate different flags than CMP, the carry bit can be used
821  // for NE/EQ.
822  bool Invert = false;
823  bool Shift = false;
824  bool Convert = true;
825  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
826   default:
827    Convert = false;
828    break;
829   case MSP430CC::COND_HS:
830     // Res = SRW & 1, no processing is required
831     break;
832   case MSP430CC::COND_LO:
833     // Res = ~(SRW & 1)
834     Invert = true;
835     break;
836   case MSP430CC::COND_NE:
837     if (andCC) {
838       // C = ~Z, thus Res = SRW & 1, no processing is required
839     } else {
840       // Res = ~((SRW >> 1) & 1)
841       Shift = true;
842       Invert = true;
843     }
844     break;
845   case MSP430CC::COND_E:
846     Shift = true;
847     // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
848     // Res = (SRW >> 1) & 1 is 1 word shorter.
849     break;
850  }
851  EVT VT = Op.getValueType();
852  SDValue One  = DAG.getConstant(1, VT);
853  if (Convert) {
854    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
855                                    MVT::i16, Flag);
856    if (Shift)
857      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
858      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
859    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
860    if (Invert)
861      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
862    return SR;
863  } else {
864    SDValue Zero = DAG.getConstant(0, VT);
865    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
866    SmallVector<SDValue, 4> Ops;
867    Ops.push_back(One);
868    Ops.push_back(Zero);
869    Ops.push_back(TargetCC);
870    Ops.push_back(Flag);
871    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
872  }
873}
874
875SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
876                                             SelectionDAG &DAG) const {
877  SDValue LHS    = Op.getOperand(0);
878  SDValue RHS    = Op.getOperand(1);
879  SDValue TrueV  = Op.getOperand(2);
880  SDValue FalseV = Op.getOperand(3);
881  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
882  SDLoc dl   (Op);
883
884  SDValue TargetCC;
885  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
886
887  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
888  SmallVector<SDValue, 4> Ops;
889  Ops.push_back(TrueV);
890  Ops.push_back(FalseV);
891  Ops.push_back(TargetCC);
892  Ops.push_back(Flag);
893
894  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
895}
896
897SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
898                                               SelectionDAG &DAG) const {
899  SDValue Val = Op.getOperand(0);
900  EVT VT      = Op.getValueType();
901  SDLoc dl(Op);
902
903  assert(VT == MVT::i16 && "Only support i16 for now!");
904
905  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
906                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
907                     DAG.getValueType(Val.getValueType()));
908}
909
910SDValue
911MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
912  MachineFunction &MF = DAG.getMachineFunction();
913  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
914  int ReturnAddrIndex = FuncInfo->getRAIndex();
915
916  if (ReturnAddrIndex == 0) {
917    // Set up a frame object for the return address.
918    uint64_t SlotSize = TD->getPointerSize();
919    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
920                                                           true);
921    FuncInfo->setRAIndex(ReturnAddrIndex);
922  }
923
924  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
925}
926
927SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
928                                              SelectionDAG &DAG) const {
929  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
930  MFI->setReturnAddressIsTaken(true);
931
932  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
933  SDLoc dl(Op);
934
935  if (Depth > 0) {
936    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
937    SDValue Offset =
938      DAG.getConstant(TD->getPointerSize(), MVT::i16);
939    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
940                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
941                                   FrameAddr, Offset),
942                       MachinePointerInfo(), false, false, false, 0);
943  }
944
945  // Just load the return address.
946  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
947  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
948                     RetAddrFI, MachinePointerInfo(), false, false, false, 0);
949}
950
951SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
952                                             SelectionDAG &DAG) const {
953  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
954  MFI->setFrameAddressIsTaken(true);
955
956  EVT VT = Op.getValueType();
957  SDLoc dl(Op);  // FIXME probably not meaningful
958  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
959  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
960                                         MSP430::FPW, VT);
961  while (Depth--)
962    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
963                            MachinePointerInfo(),
964                            false, false, false, 0);
965  return FrameAddr;
966}
967
968SDValue MSP430TargetLowering::LowerVASTART(SDValue Op,
969                                           SelectionDAG &DAG) const {
970  MachineFunction &MF = DAG.getMachineFunction();
971  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
972
973  // Frame index of first vararg argument
974  SDValue FrameIndex = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
975                                         getPointerTy());
976  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
977
978  // Create a store of the frame index to the location operand
979  return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex,
980                      Op.getOperand(1), MachinePointerInfo(SV),
981                      false, false, 0);
982}
983
984/// getPostIndexedAddressParts - returns true by value, base pointer and
985/// offset pointer and addressing mode by reference if this node can be
986/// combined with a load / store to form a post-indexed load / store.
987bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
988                                                      SDValue &Base,
989                                                      SDValue &Offset,
990                                                      ISD::MemIndexedMode &AM,
991                                                      SelectionDAG &DAG) const {
992
993  LoadSDNode *LD = cast<LoadSDNode>(N);
994  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
995    return false;
996
997  EVT VT = LD->getMemoryVT();
998  if (VT != MVT::i8 && VT != MVT::i16)
999    return false;
1000
1001  if (Op->getOpcode() != ISD::ADD)
1002    return false;
1003
1004  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1005    uint64_t RHSC = RHS->getZExtValue();
1006    if ((VT == MVT::i16 && RHSC != 2) ||
1007        (VT == MVT::i8 && RHSC != 1))
1008      return false;
1009
1010    Base = Op->getOperand(0);
1011    Offset = DAG.getConstant(RHSC, VT);
1012    AM = ISD::POST_INC;
1013    return true;
1014  }
1015
1016  return false;
1017}
1018
1019
1020const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1021  switch (Opcode) {
1022  default: return NULL;
1023  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
1024  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
1025  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
1026  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
1027  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
1028  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
1029  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
1030  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
1031  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
1032  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
1033  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
1034  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
1035  }
1036}
1037
1038bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
1039                                          Type *Ty2) const {
1040  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1041    return false;
1042
1043  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1044}
1045
1046bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1047  if (!VT1.isInteger() || !VT2.isInteger())
1048    return false;
1049
1050  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1051}
1052
1053bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1054  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1055  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1056}
1057
1058bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1059  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1060  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1061}
1062
1063bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
1064  return isZExtFree(Val.getValueType(), VT2);
1065}
1066
1067//===----------------------------------------------------------------------===//
1068//  Other Lowering Code
1069//===----------------------------------------------------------------------===//
1070
1071MachineBasicBlock*
1072MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1073                                     MachineBasicBlock *BB) const {
1074  MachineFunction *F = BB->getParent();
1075  MachineRegisterInfo &RI = F->getRegInfo();
1076  DebugLoc dl = MI->getDebugLoc();
1077  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1078
1079  unsigned Opc;
1080  const TargetRegisterClass * RC;
1081  switch (MI->getOpcode()) {
1082  default: llvm_unreachable("Invalid shift opcode!");
1083  case MSP430::Shl8:
1084   Opc = MSP430::SHL8r1;
1085   RC = &MSP430::GR8RegClass;
1086   break;
1087  case MSP430::Shl16:
1088   Opc = MSP430::SHL16r1;
1089   RC = &MSP430::GR16RegClass;
1090   break;
1091  case MSP430::Sra8:
1092   Opc = MSP430::SAR8r1;
1093   RC = &MSP430::GR8RegClass;
1094   break;
1095  case MSP430::Sra16:
1096   Opc = MSP430::SAR16r1;
1097   RC = &MSP430::GR16RegClass;
1098   break;
1099  case MSP430::Srl8:
1100   Opc = MSP430::SAR8r1c;
1101   RC = &MSP430::GR8RegClass;
1102   break;
1103  case MSP430::Srl16:
1104   Opc = MSP430::SAR16r1c;
1105   RC = &MSP430::GR16RegClass;
1106   break;
1107  }
1108
1109  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1110  MachineFunction::iterator I = BB;
1111  ++I;
1112
1113  // Create loop block
1114  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1115  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1116
1117  F->insert(I, LoopBB);
1118  F->insert(I, RemBB);
1119
1120  // Update machine-CFG edges by transferring all successors of the current
1121  // block to the block containing instructions after shift.
1122  RemBB->splice(RemBB->begin(), BB,
1123                llvm::next(MachineBasicBlock::iterator(MI)),
1124                BB->end());
1125  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1126
1127  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1128  BB->addSuccessor(LoopBB);
1129  BB->addSuccessor(RemBB);
1130  LoopBB->addSuccessor(RemBB);
1131  LoopBB->addSuccessor(LoopBB);
1132
1133  unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1134  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1135  unsigned ShiftReg = RI.createVirtualRegister(RC);
1136  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1137  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1138  unsigned SrcReg = MI->getOperand(1).getReg();
1139  unsigned DstReg = MI->getOperand(0).getReg();
1140
1141  // BB:
1142  // cmp 0, N
1143  // je RemBB
1144  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1145    .addReg(ShiftAmtSrcReg).addImm(0);
1146  BuildMI(BB, dl, TII.get(MSP430::JCC))
1147    .addMBB(RemBB)
1148    .addImm(MSP430CC::COND_E);
1149
1150  // LoopBB:
1151  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1152  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1153  // ShiftReg2 = shift ShiftReg
1154  // ShiftAmt2 = ShiftAmt - 1;
1155  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1156    .addReg(SrcReg).addMBB(BB)
1157    .addReg(ShiftReg2).addMBB(LoopBB);
1158  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1159    .addReg(ShiftAmtSrcReg).addMBB(BB)
1160    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1161  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1162    .addReg(ShiftReg);
1163  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1164    .addReg(ShiftAmtReg).addImm(1);
1165  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1166    .addMBB(LoopBB)
1167    .addImm(MSP430CC::COND_NE);
1168
1169  // RemBB:
1170  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1171  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1172    .addReg(SrcReg).addMBB(BB)
1173    .addReg(ShiftReg2).addMBB(LoopBB);
1174
1175  MI->eraseFromParent();   // The pseudo instruction is gone now.
1176  return RemBB;
1177}
1178
1179MachineBasicBlock*
1180MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1181                                                  MachineBasicBlock *BB) const {
1182  unsigned Opc = MI->getOpcode();
1183
1184  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1185      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1186      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1187    return EmitShiftInstr(MI, BB);
1188
1189  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1190  DebugLoc dl = MI->getDebugLoc();
1191
1192  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1193         "Unexpected instr type to insert");
1194
1195  // To "insert" a SELECT instruction, we actually have to insert the diamond
1196  // control-flow pattern.  The incoming instruction knows the destination vreg
1197  // to set, the condition code register to branch on, the true/false values to
1198  // select between, and a branch opcode to use.
1199  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1200  MachineFunction::iterator I = BB;
1201  ++I;
1202
1203  //  thisMBB:
1204  //  ...
1205  //   TrueVal = ...
1206  //   cmpTY ccX, r1, r2
1207  //   jCC copy1MBB
1208  //   fallthrough --> copy0MBB
1209  MachineBasicBlock *thisMBB = BB;
1210  MachineFunction *F = BB->getParent();
1211  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1212  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1213  F->insert(I, copy0MBB);
1214  F->insert(I, copy1MBB);
1215  // Update machine-CFG edges by transferring all successors of the current
1216  // block to the new block which will contain the Phi node for the select.
1217  copy1MBB->splice(copy1MBB->begin(), BB,
1218                   llvm::next(MachineBasicBlock::iterator(MI)),
1219                   BB->end());
1220  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1221  // Next, add the true and fallthrough blocks as its successors.
1222  BB->addSuccessor(copy0MBB);
1223  BB->addSuccessor(copy1MBB);
1224
1225  BuildMI(BB, dl, TII.get(MSP430::JCC))
1226    .addMBB(copy1MBB)
1227    .addImm(MI->getOperand(3).getImm());
1228
1229  //  copy0MBB:
1230  //   %FalseValue = ...
1231  //   # fallthrough to copy1MBB
1232  BB = copy0MBB;
1233
1234  // Update machine-CFG edges
1235  BB->addSuccessor(copy1MBB);
1236
1237  //  copy1MBB:
1238  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1239  //  ...
1240  BB = copy1MBB;
1241  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1242          MI->getOperand(0).getReg())
1243    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1244    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1245
1246  MI->eraseFromParent();   // The pseudo instruction is gone now.
1247  return BB;
1248}
1249