MSP430ISelLowering.cpp revision cb50e0bd60167440e2e41274f9d3c3c0e88d90ad
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the MSP430TargetLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "msp430-lower" 15 16#include "MSP430ISelLowering.h" 17#include "MSP430.h" 18#include "MSP430MachineFunctionInfo.h" 19#include "MSP430TargetMachine.h" 20#include "MSP430Subtarget.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Function.h" 23#include "llvm/Intrinsics.h" 24#include "llvm/CallingConv.h" 25#include "llvm/GlobalVariable.h" 26#include "llvm/GlobalAlias.h" 27#include "llvm/CodeGen/CallingConvLower.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/PseudoSourceValue.h" 33#include "llvm/CodeGen/SelectionDAGISel.h" 34#include "llvm/CodeGen/ValueTypes.h" 35#include "llvm/Target/TargetLoweringObjectFile.h" 36#include "llvm/Support/CommandLine.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/ErrorHandling.h" 39#include "llvm/Support/raw_ostream.h" 40#include "llvm/ADT/VectorExtras.h" 41using namespace llvm; 42 43typedef enum { 44 NoHWMult, 45 HWMultIntr, 46 HWMultNoIntr 47} HWMultUseMode; 48 49static cl::opt<HWMultUseMode> 50HWMultMode("msp430-hwmult-mode", 51 cl::desc("Hardware multiplier use mode"), 52 cl::init(HWMultNoIntr), 53 cl::values( 54 clEnumValN(NoHWMult, "no", 55 "Do not use hardware multiplier"), 56 clEnumValN(HWMultIntr, "interrupts", 57 "Assume hardware multiplier can be used inside interrupts"), 58 clEnumValN(HWMultNoIntr, "use", 59 "Assume hardware multiplier cannot be used inside interrupts"), 60 clEnumValEnd)); 61 62MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) : 63 TargetLowering(tm, new TargetLoweringObjectFileELF()), 64 Subtarget(*tm.getSubtargetImpl()), TM(tm) { 65 66 TD = getTargetData(); 67 68 // Set up the register classes. 69 addRegisterClass(MVT::i8, MSP430::GR8RegisterClass); 70 addRegisterClass(MVT::i16, MSP430::GR16RegisterClass); 71 72 // Compute derived properties from the register classes 73 computeRegisterProperties(); 74 75 // Provide all sorts of operation actions 76 77 // Division is expensive 78 setIntDivIsCheap(false); 79 80 // Even if we have only 1 bit shift here, we can perform 81 // shifts of the whole bitwidth 1 bit per step. 82 setShiftAmountType(MVT::i8); 83 84 setStackPointerRegisterToSaveRestore(MSP430::SPW); 85 setBooleanContents(ZeroOrOneBooleanContent); 86 setSchedulingPreference(SchedulingForLatency); 87 88 // We have post-incremented loads / stores. 89 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 90 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 91 92 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 93 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 94 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 95 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 96 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); 97 98 // We don't have any truncstores 99 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 100 101 setOperationAction(ISD::SRA, MVT::i8, Custom); 102 setOperationAction(ISD::SHL, MVT::i8, Custom); 103 setOperationAction(ISD::SRL, MVT::i8, Custom); 104 setOperationAction(ISD::SRA, MVT::i16, Custom); 105 setOperationAction(ISD::SHL, MVT::i16, Custom); 106 setOperationAction(ISD::SRL, MVT::i16, Custom); 107 setOperationAction(ISD::ROTL, MVT::i8, Expand); 108 setOperationAction(ISD::ROTR, MVT::i8, Expand); 109 setOperationAction(ISD::ROTL, MVT::i16, Expand); 110 setOperationAction(ISD::ROTR, MVT::i16, Expand); 111 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); 112 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom); 113 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 114 setOperationAction(ISD::BRIND, MVT::Other, Expand); 115 setOperationAction(ISD::BR_CC, MVT::i8, Custom); 116 setOperationAction(ISD::BR_CC, MVT::i16, Custom); 117 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 118 setOperationAction(ISD::SETCC, MVT::i8, Custom); 119 setOperationAction(ISD::SETCC, MVT::i16, Custom); 120 setOperationAction(ISD::SELECT, MVT::i8, Expand); 121 setOperationAction(ISD::SELECT, MVT::i16, Expand); 122 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); 123 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 124 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); 125 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); 126 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); 127 128 setOperationAction(ISD::CTTZ, MVT::i8, Expand); 129 setOperationAction(ISD::CTTZ, MVT::i16, Expand); 130 setOperationAction(ISD::CTLZ, MVT::i8, Expand); 131 setOperationAction(ISD::CTLZ, MVT::i16, Expand); 132 setOperationAction(ISD::CTPOP, MVT::i8, Expand); 133 setOperationAction(ISD::CTPOP, MVT::i16, Expand); 134 135 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand); 136 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); 137 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand); 138 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); 139 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand); 140 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); 141 142 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 143 144 // FIXME: Implement efficiently multiplication by a constant 145 setOperationAction(ISD::MUL, MVT::i8, Expand); 146 setOperationAction(ISD::MULHS, MVT::i8, Expand); 147 setOperationAction(ISD::MULHU, MVT::i8, Expand); 148 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand); 149 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand); 150 setOperationAction(ISD::MUL, MVT::i16, Expand); 151 setOperationAction(ISD::MULHS, MVT::i16, Expand); 152 setOperationAction(ISD::MULHU, MVT::i16, Expand); 153 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); 154 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); 155 156 setOperationAction(ISD::UDIV, MVT::i8, Expand); 157 setOperationAction(ISD::UDIVREM, MVT::i8, Expand); 158 setOperationAction(ISD::UREM, MVT::i8, Expand); 159 setOperationAction(ISD::SDIV, MVT::i8, Expand); 160 setOperationAction(ISD::SDIVREM, MVT::i8, Expand); 161 setOperationAction(ISD::SREM, MVT::i8, Expand); 162 setOperationAction(ISD::UDIV, MVT::i16, Expand); 163 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); 164 setOperationAction(ISD::UREM, MVT::i16, Expand); 165 setOperationAction(ISD::SDIV, MVT::i16, Expand); 166 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); 167 setOperationAction(ISD::SREM, MVT::i16, Expand); 168 169 // Libcalls names. 170 if (HWMultMode == HWMultIntr) { 171 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw"); 172 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw"); 173 } else if (HWMultMode == HWMultNoIntr) { 174 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw_noint"); 175 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint"); 176 } 177} 178 179SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 180 switch (Op.getOpcode()) { 181 case ISD::SHL: // FALLTHROUGH 182 case ISD::SRL: 183 case ISD::SRA: return LowerShifts(Op, DAG); 184 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 185 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 186 case ISD::SETCC: return LowerSETCC(Op, DAG); 187 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 188 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 189 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); 190 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 191 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 192 default: 193 llvm_unreachable("unimplemented operand"); 194 return SDValue(); 195 } 196} 197 198/// getFunctionAlignment - Return the Log2 alignment of this function. 199unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const { 200 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2; 201} 202 203//===----------------------------------------------------------------------===// 204// MSP430 Inline Assembly Support 205//===----------------------------------------------------------------------===// 206 207/// getConstraintType - Given a constraint letter, return the type of 208/// constraint it is for this target. 209TargetLowering::ConstraintType 210MSP430TargetLowering::getConstraintType(const std::string &Constraint) const { 211 if (Constraint.size() == 1) { 212 switch (Constraint[0]) { 213 case 'r': 214 return C_RegisterClass; 215 default: 216 break; 217 } 218 } 219 return TargetLowering::getConstraintType(Constraint); 220} 221 222std::pair<unsigned, const TargetRegisterClass*> 223MSP430TargetLowering:: 224getRegForInlineAsmConstraint(const std::string &Constraint, 225 EVT VT) const { 226 if (Constraint.size() == 1) { 227 // GCC Constraint Letters 228 switch (Constraint[0]) { 229 default: break; 230 case 'r': // GENERAL_REGS 231 if (VT == MVT::i8) 232 return std::make_pair(0U, MSP430::GR8RegisterClass); 233 234 return std::make_pair(0U, MSP430::GR16RegisterClass); 235 } 236 } 237 238 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 239} 240 241//===----------------------------------------------------------------------===// 242// Calling Convention Implementation 243//===----------------------------------------------------------------------===// 244 245#include "MSP430GenCallingConv.inc" 246 247SDValue 248MSP430TargetLowering::LowerFormalArguments(SDValue Chain, 249 CallingConv::ID CallConv, 250 bool isVarArg, 251 const SmallVectorImpl<ISD::InputArg> 252 &Ins, 253 DebugLoc dl, 254 SelectionDAG &DAG, 255 SmallVectorImpl<SDValue> &InVals) { 256 257 switch (CallConv) { 258 default: 259 llvm_unreachable("Unsupported calling convention"); 260 case CallingConv::C: 261 case CallingConv::Fast: 262 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); 263 case CallingConv::MSP430_INTR: 264 if (Ins.empty()) 265 return Chain; 266 else { 267 llvm_report_error("ISRs cannot have arguments"); 268 return SDValue(); 269 } 270 } 271} 272 273SDValue 274MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 275 CallingConv::ID CallConv, bool isVarArg, 276 bool isTailCall, 277 const SmallVectorImpl<ISD::OutputArg> &Outs, 278 const SmallVectorImpl<ISD::InputArg> &Ins, 279 DebugLoc dl, SelectionDAG &DAG, 280 SmallVectorImpl<SDValue> &InVals) { 281 282 switch (CallConv) { 283 default: 284 llvm_unreachable("Unsupported calling convention"); 285 case CallingConv::Fast: 286 case CallingConv::C: 287 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 288 Outs, Ins, dl, DAG, InVals); 289 case CallingConv::MSP430_INTR: 290 llvm_report_error("ISRs cannot be called directly"); 291 return SDValue(); 292 } 293} 294 295/// LowerCCCArguments - transform physical registers into virtual registers and 296/// generate load operations for arguments places on the stack. 297// FIXME: struct return stuff 298// FIXME: varargs 299SDValue 300MSP430TargetLowering::LowerCCCArguments(SDValue Chain, 301 CallingConv::ID CallConv, 302 bool isVarArg, 303 const SmallVectorImpl<ISD::InputArg> 304 &Ins, 305 DebugLoc dl, 306 SelectionDAG &DAG, 307 SmallVectorImpl<SDValue> &InVals) { 308 MachineFunction &MF = DAG.getMachineFunction(); 309 MachineFrameInfo *MFI = MF.getFrameInfo(); 310 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 311 312 // Assign locations to all of the incoming arguments. 313 SmallVector<CCValAssign, 16> ArgLocs; 314 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 315 ArgLocs, *DAG.getContext()); 316 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430); 317 318 assert(!isVarArg && "Varargs not supported yet"); 319 320 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 321 CCValAssign &VA = ArgLocs[i]; 322 if (VA.isRegLoc()) { 323 // Arguments passed in registers 324 EVT RegVT = VA.getLocVT(); 325 switch (RegVT.getSimpleVT().SimpleTy) { 326 default: 327 { 328#ifndef NDEBUG 329 errs() << "LowerFormalArguments Unhandled argument type: " 330 << RegVT.getSimpleVT().SimpleTy << "\n"; 331#endif 332 llvm_unreachable(0); 333 } 334 case MVT::i16: 335 unsigned VReg = 336 RegInfo.createVirtualRegister(MSP430::GR16RegisterClass); 337 RegInfo.addLiveIn(VA.getLocReg(), VReg); 338 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); 339 340 // If this is an 8-bit value, it is really passed promoted to 16 341 // bits. Insert an assert[sz]ext to capture this, then truncate to the 342 // right size. 343 if (VA.getLocInfo() == CCValAssign::SExt) 344 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 345 DAG.getValueType(VA.getValVT())); 346 else if (VA.getLocInfo() == CCValAssign::ZExt) 347 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 348 DAG.getValueType(VA.getValVT())); 349 350 if (VA.getLocInfo() != CCValAssign::Full) 351 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 352 353 InVals.push_back(ArgValue); 354 } 355 } else { 356 // Sanity check 357 assert(VA.isMemLoc()); 358 // Load the argument to a virtual register 359 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 360 if (ObjSize > 2) { 361 errs() << "LowerFormalArguments Unhandled argument type: " 362 << VA.getLocVT().getSimpleVT().SimpleTy 363 << "\n"; 364 } 365 // Create the frame index object for this incoming parameter... 366 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true, false); 367 368 // Create the SelectionDAG nodes corresponding to a load 369 //from this parameter 370 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16); 371 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 372 PseudoSourceValue::getFixedStack(FI), 0)); 373 } 374 } 375 376 return Chain; 377} 378 379SDValue 380MSP430TargetLowering::LowerReturn(SDValue Chain, 381 CallingConv::ID CallConv, bool isVarArg, 382 const SmallVectorImpl<ISD::OutputArg> &Outs, 383 DebugLoc dl, SelectionDAG &DAG) { 384 385 // CCValAssign - represent the assignment of the return value to a location 386 SmallVector<CCValAssign, 16> RVLocs; 387 388 // ISRs cannot return any value. 389 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) { 390 llvm_report_error("ISRs cannot return any value"); 391 return SDValue(); 392 } 393 394 // CCState - Info about the registers and stack slot. 395 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 396 RVLocs, *DAG.getContext()); 397 398 // Analize return values. 399 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430); 400 401 // If this is the first return lowered for this function, add the regs to the 402 // liveout set for the function. 403 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 404 for (unsigned i = 0; i != RVLocs.size(); ++i) 405 if (RVLocs[i].isRegLoc()) 406 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 407 } 408 409 SDValue Flag; 410 411 // Copy the result values into the output registers. 412 for (unsigned i = 0; i != RVLocs.size(); ++i) { 413 CCValAssign &VA = RVLocs[i]; 414 assert(VA.isRegLoc() && "Can only return in registers!"); 415 416 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 417 Outs[i].Val, Flag); 418 419 // Guarantee that all emitted copies are stuck together, 420 // avoiding something bad. 421 Flag = Chain.getValue(1); 422 } 423 424 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ? 425 MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG); 426 427 if (Flag.getNode()) 428 return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag); 429 430 // Return Void 431 return DAG.getNode(Opc, dl, MVT::Other, Chain); 432} 433 434/// LowerCCCCallTo - functions arguments are copied from virtual regs to 435/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 436/// TODO: sret. 437SDValue 438MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 439 CallingConv::ID CallConv, bool isVarArg, 440 bool isTailCall, 441 const SmallVectorImpl<ISD::OutputArg> 442 &Outs, 443 const SmallVectorImpl<ISD::InputArg> &Ins, 444 DebugLoc dl, SelectionDAG &DAG, 445 SmallVectorImpl<SDValue> &InVals) { 446 // Analyze operands of the call, assigning locations to each operand. 447 SmallVector<CCValAssign, 16> ArgLocs; 448 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 449 ArgLocs, *DAG.getContext()); 450 451 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430); 452 453 // Get a count of how many bytes are to be pushed on the stack. 454 unsigned NumBytes = CCInfo.getNextStackOffset(); 455 456 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes, 457 getPointerTy(), true)); 458 459 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 460 SmallVector<SDValue, 12> MemOpChains; 461 SDValue StackPtr; 462 463 // Walk the register/memloc assignments, inserting copies/loads. 464 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 465 CCValAssign &VA = ArgLocs[i]; 466 467 SDValue Arg = Outs[i].Val; 468 469 // Promote the value if needed. 470 switch (VA.getLocInfo()) { 471 default: llvm_unreachable("Unknown loc info!"); 472 case CCValAssign::Full: break; 473 case CCValAssign::SExt: 474 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 475 break; 476 case CCValAssign::ZExt: 477 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 478 break; 479 case CCValAssign::AExt: 480 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 481 break; 482 } 483 484 // Arguments that can be passed on register must be kept at RegsToPass 485 // vector 486 if (VA.isRegLoc()) { 487 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 488 } else { 489 assert(VA.isMemLoc()); 490 491 if (StackPtr.getNode() == 0) 492 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy()); 493 494 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), 495 StackPtr, 496 DAG.getIntPtrConstant(VA.getLocMemOffset())); 497 498 499 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 500 PseudoSourceValue::getStack(), 501 VA.getLocMemOffset())); 502 } 503 } 504 505 // Transform all store nodes into one single node because all store nodes are 506 // independent of each other. 507 if (!MemOpChains.empty()) 508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 509 &MemOpChains[0], MemOpChains.size()); 510 511 // Build a sequence of copy-to-reg nodes chained together with token chain and 512 // flag operands which copy the outgoing args into registers. The InFlag in 513 // necessary since all emited instructions must be stuck together. 514 SDValue InFlag; 515 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 516 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 517 RegsToPass[i].second, InFlag); 518 InFlag = Chain.getValue(1); 519 } 520 521 // If the callee is a GlobalAddress node (quite common, every direct call is) 522 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 523 // Likewise ExternalSymbol -> TargetExternalSymbol. 524 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 525 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16); 526 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 527 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16); 528 529 // Returns a chain & a flag for retval copy to use. 530 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 531 SmallVector<SDValue, 8> Ops; 532 Ops.push_back(Chain); 533 Ops.push_back(Callee); 534 535 // Add argument registers to the end of the list so that they are 536 // known live into the call. 537 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 538 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 539 RegsToPass[i].second.getValueType())); 540 541 if (InFlag.getNode()) 542 Ops.push_back(InFlag); 543 544 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 545 InFlag = Chain.getValue(1); 546 547 // Create the CALLSEQ_END node. 548 Chain = DAG.getCALLSEQ_END(Chain, 549 DAG.getConstant(NumBytes, getPointerTy(), true), 550 DAG.getConstant(0, getPointerTy(), true), 551 InFlag); 552 InFlag = Chain.getValue(1); 553 554 // Handle result values, copying them out of physregs into vregs that we 555 // return. 556 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, 557 DAG, InVals); 558} 559 560/// LowerCallResult - Lower the result values of a call into the 561/// appropriate copies out of appropriate physical registers. 562/// 563SDValue 564MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 565 CallingConv::ID CallConv, bool isVarArg, 566 const SmallVectorImpl<ISD::InputArg> &Ins, 567 DebugLoc dl, SelectionDAG &DAG, 568 SmallVectorImpl<SDValue> &InVals) { 569 570 // Assign locations to each value returned by this call. 571 SmallVector<CCValAssign, 16> RVLocs; 572 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 573 RVLocs, *DAG.getContext()); 574 575 CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430); 576 577 // Copy all of the result registers out of their specified physreg. 578 for (unsigned i = 0; i != RVLocs.size(); ++i) { 579 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 580 RVLocs[i].getValVT(), InFlag).getValue(1); 581 InFlag = Chain.getValue(2); 582 InVals.push_back(Chain.getValue(0)); 583 } 584 585 return Chain; 586} 587 588SDValue MSP430TargetLowering::LowerShifts(SDValue Op, 589 SelectionDAG &DAG) { 590 unsigned Opc = Op.getOpcode(); 591 SDNode* N = Op.getNode(); 592 EVT VT = Op.getValueType(); 593 DebugLoc dl = N->getDebugLoc(); 594 595 // Expand non-constant shifts to loops: 596 if (!isa<ConstantSDNode>(N->getOperand(1))) 597 switch (Opc) { 598 default: 599 assert(0 && "Invalid shift opcode!"); 600 case ISD::SHL: 601 return DAG.getNode(MSP430ISD::SHL, dl, 602 VT, N->getOperand(0), N->getOperand(1)); 603 case ISD::SRA: 604 return DAG.getNode(MSP430ISD::SRA, dl, 605 VT, N->getOperand(0), N->getOperand(1)); 606 case ISD::SRL: 607 return DAG.getNode(MSP430ISD::SRL, dl, 608 VT, N->getOperand(0), N->getOperand(1)); 609 } 610 611 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 612 613 // Expand the stuff into sequence of shifts. 614 // FIXME: for some shift amounts this might be done better! 615 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N 616 SDValue Victim = N->getOperand(0); 617 618 if (Opc == ISD::SRL && ShiftAmount) { 619 // Emit a special goodness here: 620 // srl A, 1 => clrc; rrc A 621 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim); 622 ShiftAmount -= 1; 623 } 624 625 while (ShiftAmount--) 626 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), 627 dl, VT, Victim); 628 629 return Victim; 630} 631 632SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 633 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 634 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 635 636 // Create the TargetGlobalAddress node, folding in the constant offset. 637 SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 638 return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(), 639 getPointerTy(), Result); 640} 641 642SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op, 643 SelectionDAG &DAG) { 644 DebugLoc dl = Op.getDebugLoc(); 645 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 646 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 647 648 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);; 649} 650 651static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, 652 ISD::CondCode CC, 653 DebugLoc dl, SelectionDAG &DAG) { 654 // FIXME: Handle bittests someday 655 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet"); 656 657 // FIXME: Handle jump negative someday 658 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID; 659 switch (CC) { 660 default: llvm_unreachable("Invalid integer condition!"); 661 case ISD::SETEQ: 662 TCC = MSP430CC::COND_E; // aka COND_Z 663 // Minor optimization: if LHS is a constant, swap operands, then the 664 // constant can be folded into comparison. 665 if (LHS.getOpcode() == ISD::Constant) 666 std::swap(LHS, RHS); 667 break; 668 case ISD::SETNE: 669 TCC = MSP430CC::COND_NE; // aka COND_NZ 670 // Minor optimization: if LHS is a constant, swap operands, then the 671 // constant can be folded into comparison. 672 if (LHS.getOpcode() == ISD::Constant) 673 std::swap(LHS, RHS); 674 break; 675 case ISD::SETULE: 676 std::swap(LHS, RHS); // FALLTHROUGH 677 case ISD::SETUGE: 678 // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to 679 // fold constant into instruction. 680 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 681 LHS = RHS; 682 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0)); 683 TCC = MSP430CC::COND_LO; 684 break; 685 } 686 TCC = MSP430CC::COND_HS; // aka COND_C 687 break; 688 case ISD::SETUGT: 689 std::swap(LHS, RHS); // FALLTHROUGH 690 case ISD::SETULT: 691 // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to 692 // fold constant into instruction. 693 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 694 LHS = RHS; 695 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0)); 696 TCC = MSP430CC::COND_HS; 697 break; 698 } 699 TCC = MSP430CC::COND_LO; // aka COND_NC 700 break; 701 case ISD::SETLE: 702 std::swap(LHS, RHS); // FALLTHROUGH 703 case ISD::SETGE: 704 // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to 705 // fold constant into instruction. 706 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 707 LHS = RHS; 708 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0)); 709 TCC = MSP430CC::COND_L; 710 break; 711 } 712 TCC = MSP430CC::COND_GE; 713 break; 714 case ISD::SETGT: 715 std::swap(LHS, RHS); // FALLTHROUGH 716 case ISD::SETLT: 717 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to 718 // fold constant into instruction. 719 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { 720 LHS = RHS; 721 RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0)); 722 TCC = MSP430CC::COND_GE; 723 break; 724 } 725 TCC = MSP430CC::COND_L; 726 break; 727 } 728 729 TargetCC = DAG.getConstant(TCC, MVT::i8); 730 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS); 731} 732 733 734SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 735 SDValue Chain = Op.getOperand(0); 736 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 737 SDValue LHS = Op.getOperand(2); 738 SDValue RHS = Op.getOperand(3); 739 SDValue Dest = Op.getOperand(4); 740 DebugLoc dl = Op.getDebugLoc(); 741 742 SDValue TargetCC; 743 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 744 745 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(), 746 Chain, Dest, TargetCC, Flag); 747} 748 749 750SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { 751 SDValue LHS = Op.getOperand(0); 752 SDValue RHS = Op.getOperand(1); 753 DebugLoc dl = Op.getDebugLoc(); 754 755 // If we are doing an AND and testing against zero, then the CMP 756 // will not be generated. The AND (or BIT) will generate the condition codes, 757 // but they are different from CMP. 758 // FIXME: since we're doing a post-processing, use a pseudoinstr here, so 759 // lowering & isel wouldn't diverge. 760 bool andCC = false; 761 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 762 if (RHSC->isNullValue() && LHS.hasOneUse() && 763 (LHS.getOpcode() == ISD::AND || 764 (LHS.getOpcode() == ISD::TRUNCATE && 765 LHS.getOperand(0).getOpcode() == ISD::AND))) { 766 andCC = true; 767 } 768 } 769 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 770 SDValue TargetCC; 771 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 772 773 // Get the condition codes directly from the status register, if its easy. 774 // Otherwise a branch will be generated. Note that the AND and BIT 775 // instructions generate different flags than CMP, the carry bit can be used 776 // for NE/EQ. 777 bool Invert = false; 778 bool Shift = false; 779 bool Convert = true; 780 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) { 781 default: 782 Convert = false; 783 break; 784 case MSP430CC::COND_HS: 785 // Res = SRW & 1, no processing is required 786 break; 787 case MSP430CC::COND_LO: 788 // Res = ~(SRW & 1) 789 Invert = true; 790 break; 791 case MSP430CC::COND_NE: 792 if (andCC) { 793 // C = ~Z, thus Res = SRW & 1, no processing is required 794 } else { 795 // Res = (SRW >> 1) & 1 796 Shift = true; 797 } 798 break; 799 case MSP430CC::COND_E: 800 if (andCC) { 801 // C = ~Z, thus Res = ~(SRW & 1) 802 } else { 803 // Res = ~((SRW >> 1) & 1) 804 Shift = true; 805 } 806 Invert = true; 807 break; 808 } 809 EVT VT = Op.getValueType(); 810 SDValue One = DAG.getConstant(1, VT); 811 if (Convert) { 812 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW, 813 MVT::i16, Flag); 814 if (Shift) 815 // FIXME: somewhere this is turned into a SRL, lower it MSP specific? 816 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); 817 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One); 818 if (Invert) 819 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One); 820 return SR; 821 } else { 822 SDValue Zero = DAG.getConstant(0, VT); 823 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 824 SmallVector<SDValue, 4> Ops; 825 Ops.push_back(One); 826 Ops.push_back(Zero); 827 Ops.push_back(TargetCC); 828 Ops.push_back(Flag); 829 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size()); 830 } 831} 832 833SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 834 SDValue LHS = Op.getOperand(0); 835 SDValue RHS = Op.getOperand(1); 836 SDValue TrueV = Op.getOperand(2); 837 SDValue FalseV = Op.getOperand(3); 838 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 839 DebugLoc dl = Op.getDebugLoc(); 840 841 SDValue TargetCC; 842 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 843 844 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 845 SmallVector<SDValue, 4> Ops; 846 Ops.push_back(TrueV); 847 Ops.push_back(FalseV); 848 Ops.push_back(TargetCC); 849 Ops.push_back(Flag); 850 851 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size()); 852} 853 854SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op, 855 SelectionDAG &DAG) { 856 SDValue Val = Op.getOperand(0); 857 EVT VT = Op.getValueType(); 858 DebugLoc dl = Op.getDebugLoc(); 859 860 assert(VT == MVT::i16 && "Only support i16 for now!"); 861 862 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, 863 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), 864 DAG.getValueType(Val.getValueType())); 865} 866 867SDValue MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { 868 MachineFunction &MF = DAG.getMachineFunction(); 869 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); 870 int ReturnAddrIndex = FuncInfo->getRAIndex(); 871 872 if (ReturnAddrIndex == 0) { 873 // Set up a frame object for the return address. 874 uint64_t SlotSize = TD->getPointerSize(); 875 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 876 true, false); 877 FuncInfo->setRAIndex(ReturnAddrIndex); 878 } 879 880 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 881} 882 883SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 884 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 885 DebugLoc dl = Op.getDebugLoc(); 886 887 if (Depth > 0) { 888 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 889 SDValue Offset = 890 DAG.getConstant(TD->getPointerSize(), MVT::i16); 891 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 892 DAG.getNode(ISD::ADD, dl, getPointerTy(), 893 FrameAddr, Offset), 894 NULL, 0); 895 } 896 897 // Just load the return address. 898 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 899 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 900 RetAddrFI, NULL, 0); 901} 902 903SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 904 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 905 MFI->setFrameAddressIsTaken(true); 906 EVT VT = Op.getValueType(); 907 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 908 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 909 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 910 MSP430::FPW, VT); 911 while (Depth--) 912 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0); 913 return FrameAddr; 914} 915 916/// getPostIndexedAddressParts - returns true by value, base pointer and 917/// offset pointer and addressing mode by reference if this node can be 918/// combined with a load / store to form a post-indexed load / store. 919bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 920 SDValue &Base, 921 SDValue &Offset, 922 ISD::MemIndexedMode &AM, 923 SelectionDAG &DAG) const { 924 925 LoadSDNode *LD = cast<LoadSDNode>(N); 926 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 927 return false; 928 929 EVT VT = LD->getMemoryVT(); 930 if (VT != MVT::i8 && VT != MVT::i16) 931 return false; 932 933 if (Op->getOpcode() != ISD::ADD) 934 return false; 935 936 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 937 uint64_t RHSC = RHS->getZExtValue(); 938 if ((VT == MVT::i16 && RHSC != 2) || 939 (VT == MVT::i8 && RHSC != 1)) 940 return false; 941 942 Base = Op->getOperand(0); 943 Offset = DAG.getConstant(RHSC, VT); 944 AM = ISD::POST_INC; 945 return true; 946 } 947 948 return false; 949} 950 951 952const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const { 953 switch (Opcode) { 954 default: return NULL; 955 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG"; 956 case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG"; 957 case MSP430ISD::RRA: return "MSP430ISD::RRA"; 958 case MSP430ISD::RLA: return "MSP430ISD::RLA"; 959 case MSP430ISD::RRC: return "MSP430ISD::RRC"; 960 case MSP430ISD::CALL: return "MSP430ISD::CALL"; 961 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper"; 962 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC"; 963 case MSP430ISD::CMP: return "MSP430ISD::CMP"; 964 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; 965 case MSP430ISD::SHL: return "MSP430ISD::SHL"; 966 case MSP430ISD::SRA: return "MSP430ISD::SRA"; 967 } 968} 969 970//===----------------------------------------------------------------------===// 971// Other Lowering Code 972//===----------------------------------------------------------------------===// 973 974MachineBasicBlock* 975MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI, 976 MachineBasicBlock *BB, 977 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 978 MachineFunction *F = BB->getParent(); 979 MachineRegisterInfo &RI = F->getRegInfo(); 980 DebugLoc dl = MI->getDebugLoc(); 981 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 982 983 unsigned Opc; 984 const TargetRegisterClass * RC; 985 switch (MI->getOpcode()) { 986 default: 987 assert(0 && "Invalid shift opcode!"); 988 case MSP430::Shl8: 989 Opc = MSP430::SHL8r1; 990 RC = MSP430::GR8RegisterClass; 991 break; 992 case MSP430::Shl16: 993 Opc = MSP430::SHL16r1; 994 RC = MSP430::GR16RegisterClass; 995 break; 996 case MSP430::Sra8: 997 Opc = MSP430::SAR8r1; 998 RC = MSP430::GR8RegisterClass; 999 break; 1000 case MSP430::Sra16: 1001 Opc = MSP430::SAR16r1; 1002 RC = MSP430::GR16RegisterClass; 1003 break; 1004 case MSP430::Srl8: 1005 Opc = MSP430::SAR8r1c; 1006 RC = MSP430::GR8RegisterClass; 1007 break; 1008 case MSP430::Srl16: 1009 Opc = MSP430::SAR16r1c; 1010 RC = MSP430::GR16RegisterClass; 1011 break; 1012 } 1013 1014 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1015 MachineFunction::iterator I = BB; 1016 ++I; 1017 1018 // Create loop block 1019 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); 1020 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); 1021 1022 F->insert(I, LoopBB); 1023 F->insert(I, RemBB); 1024 1025 // Update machine-CFG edges by transferring all successors of the current 1026 // block to the block containing instructions after shift. 1027 RemBB->transferSuccessors(BB); 1028 1029 // Inform sdisel of the edge changes. 1030 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), 1031 SE = BB->succ_end(); SI != SE; ++SI) 1032 EM->insert(std::make_pair(*SI, RemBB)); 1033 1034 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB 1035 BB->addSuccessor(LoopBB); 1036 BB->addSuccessor(RemBB); 1037 LoopBB->addSuccessor(RemBB); 1038 LoopBB->addSuccessor(LoopBB); 1039 1040 unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass); 1041 unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass); 1042 unsigned ShiftReg = RI.createVirtualRegister(RC); 1043 unsigned ShiftReg2 = RI.createVirtualRegister(RC); 1044 unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg(); 1045 unsigned SrcReg = MI->getOperand(1).getReg(); 1046 unsigned DstReg = MI->getOperand(0).getReg(); 1047 1048 // BB: 1049 // cmp 0, N 1050 // je RemBB 1051 BuildMI(BB, dl, TII.get(MSP430::CMP8ri)) 1052 .addReg(ShiftAmtSrcReg).addImm(0); 1053 BuildMI(BB, dl, TII.get(MSP430::JCC)) 1054 .addMBB(RemBB) 1055 .addImm(MSP430CC::COND_E); 1056 1057 // LoopBB: 1058 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB] 1059 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB] 1060 // ShiftReg2 = shift ShiftReg 1061 // ShiftAmt2 = ShiftAmt - 1; 1062 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) 1063 .addReg(SrcReg).addMBB(BB) 1064 .addReg(ShiftReg2).addMBB(LoopBB); 1065 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg) 1066 .addReg(ShiftAmtSrcReg).addMBB(BB) 1067 .addReg(ShiftAmtReg2).addMBB(LoopBB); 1068 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2) 1069 .addReg(ShiftReg); 1070 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2) 1071 .addReg(ShiftAmtReg).addImm(1); 1072 BuildMI(LoopBB, dl, TII.get(MSP430::JCC)) 1073 .addMBB(LoopBB) 1074 .addImm(MSP430CC::COND_NE); 1075 1076 // RemBB: 1077 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB] 1078 BuildMI(RemBB, dl, TII.get(MSP430::PHI), DstReg) 1079 .addReg(SrcReg).addMBB(BB) 1080 .addReg(ShiftReg2).addMBB(LoopBB); 1081 1082 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 1083 return RemBB; 1084} 1085 1086MachineBasicBlock* 1087MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1088 MachineBasicBlock *BB, 1089 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 1090 unsigned Opc = MI->getOpcode(); 1091 1092 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 || 1093 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 || 1094 Opc == MSP430::Srl8 || Opc == MSP430::Srl16) 1095 return EmitShiftInstr(MI, BB, EM); 1096 1097 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 1098 DebugLoc dl = MI->getDebugLoc(); 1099 1100 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) && 1101 "Unexpected instr type to insert"); 1102 1103 // To "insert" a SELECT instruction, we actually have to insert the diamond 1104 // control-flow pattern. The incoming instruction knows the destination vreg 1105 // to set, the condition code register to branch on, the true/false values to 1106 // select between, and a branch opcode to use. 1107 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1108 MachineFunction::iterator I = BB; 1109 ++I; 1110 1111 // thisMBB: 1112 // ... 1113 // TrueVal = ... 1114 // cmpTY ccX, r1, r2 1115 // jCC copy1MBB 1116 // fallthrough --> copy0MBB 1117 MachineBasicBlock *thisMBB = BB; 1118 MachineFunction *F = BB->getParent(); 1119 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1120 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 1121 BuildMI(BB, dl, TII.get(MSP430::JCC)) 1122 .addMBB(copy1MBB) 1123 .addImm(MI->getOperand(3).getImm()); 1124 F->insert(I, copy0MBB); 1125 F->insert(I, copy1MBB); 1126 // Inform sdisel of the edge changes. 1127 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), 1128 SE = BB->succ_end(); SI != SE; ++SI) 1129 EM->insert(std::make_pair(*SI, copy1MBB)); 1130 // Update machine-CFG edges by transferring all successors of the current 1131 // block to the new block which will contain the Phi node for the select. 1132 copy1MBB->transferSuccessors(BB); 1133 // Next, add the true and fallthrough blocks as its successors. 1134 BB->addSuccessor(copy0MBB); 1135 BB->addSuccessor(copy1MBB); 1136 1137 // copy0MBB: 1138 // %FalseValue = ... 1139 // # fallthrough to copy1MBB 1140 BB = copy0MBB; 1141 1142 // Update machine-CFG edges 1143 BB->addSuccessor(copy1MBB); 1144 1145 // copy1MBB: 1146 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1147 // ... 1148 BB = copy1MBB; 1149 BuildMI(BB, dl, TII.get(MSP430::PHI), 1150 MI->getOperand(0).getReg()) 1151 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1152 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1153 1154 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 1155 return BB; 1156} 1157