R600RegisterInfo.cpp revision 07b59ba69713f9aabb7597193f0df4b02c29d8f9 
1//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief R600 implementation of the TargetRegisterInfo class.
12//
13//===----------------------------------------------------------------------===//
14
15#include "R600RegisterInfo.h"
16#include "AMDGPUTargetMachine.h"
17#include "R600Defines.h"
18#include "R600InstrInfo.h"
19#include "R600MachineFunctionInfo.h"
20
21using namespace llvm;
22
23R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
24    const TargetInstrInfo &tii)
25: AMDGPURegisterInfo(tm, tii),
26  TM(tm),
27  TII(tii)
28  { }
29
30BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
31  BitVector Reserved(getNumRegs());
32
33  Reserved.set(AMDGPU::ZERO);
34  Reserved.set(AMDGPU::HALF);
35  Reserved.set(AMDGPU::ONE);
36  Reserved.set(AMDGPU::ONE_INT);
37  Reserved.set(AMDGPU::NEG_HALF);
38  Reserved.set(AMDGPU::NEG_ONE);
39  Reserved.set(AMDGPU::PV_X);
40  Reserved.set(AMDGPU::ALU_LITERAL_X);
41  Reserved.set(AMDGPU::ALU_CONST);
42  Reserved.set(AMDGPU::PREDICATE_BIT);
43  Reserved.set(AMDGPU::PRED_SEL_OFF);
44  Reserved.set(AMDGPU::PRED_SEL_ZERO);
45  Reserved.set(AMDGPU::PRED_SEL_ONE);
46
47  for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
48                        E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
49    Reserved.set(*I);
50  }
51
52  const R600InstrInfo *RII = static_cast<const R600InstrInfo*>(&TII);
53  std::vector<unsigned> IndirectRegs = RII->getIndirectReservedRegs(MF);
54  for (std::vector<unsigned>::iterator I = IndirectRegs.begin(),
55                                       E = IndirectRegs.end();
56                                       I != E; ++I) {
57    Reserved.set(*I);
58  }
59  return Reserved;
60}
61
62const TargetRegisterClass *
63R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
64  switch (rc->getID()) {
65  case AMDGPU::GPRF32RegClassID:
66  case AMDGPU::GPRI32RegClassID:
67    return &AMDGPU::R600_Reg32RegClass;
68  default: return rc;
69  }
70}
71
72unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
73  return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
74}
75
76const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
77                                                                   MVT VT) const {
78  switch(VT.SimpleTy) {
79  default:
80  case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
81  }
82}
83
84unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const {
85  switch (Channel) {
86    default: assert(!"Invalid channel index"); return 0;
87    case 0: return AMDGPU::sub0;
88    case 1: return AMDGPU::sub1;
89    case 2: return AMDGPU::sub2;
90    case 3: return AMDGPU::sub3;
91  }
92}
93
94