X86RegisterInfo.h revision 1dcce2148d855af67f845319414a94db5601be3e
1//===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86REGISTERINFO_H 15#define X86REGISTERINFO_H 16 17#include "llvm/ADT/DenseMap.h" 18#include "llvm/ADT/SmallVector.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "X86GenRegisterInfo.h.inc" 21 22namespace llvm { 23 class Type; 24 class TargetInstrInfo; 25 class X86TargetMachine; 26 27/// N86 namespace - Native X86 register numbers 28/// 29namespace N86 { 30 enum { 31 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 32 }; 33} 34 35namespace X86 { 36 /// SubregIndex - The index of various sized subregister classes. Note that 37 /// these indices must be kept in sync with the class indices in the 38 /// X86RegisterInfo.td file. 39 enum SubregIndex { 40 SUBREG_8BIT = 1, SUBREG_16BIT = 2, SUBREG_32BIT = 3 41 }; 42} 43 44/// DWARFFlavour - Flavour of dwarf regnumbers 45/// 46namespace DWARFFlavour { 47 enum { 48 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 49 }; 50} 51 52class X86RegisterInfo : public X86GenRegisterInfo { 53public: 54 X86TargetMachine &TM; 55 const TargetInstrInfo &TII; 56 57private: 58 /// Is64Bit - Is the target 64-bits. 59 /// 60 bool Is64Bit; 61 62 /// IsWin64 - Is the target on of win64 flavours 63 /// 64 bool IsWin64; 65 66 /// SlotSize - Stack slot size in bytes. 67 /// 68 unsigned SlotSize; 69 70 /// StackAlign - Default stack alignment. 71 /// 72 unsigned StackAlign; 73 74 /// StackPtr - X86 physical register used as stack ptr. 75 /// 76 unsigned StackPtr; 77 78 /// FramePtr - X86 physical register used as frame ptr. 79 /// 80 unsigned FramePtr; 81 82public: 83 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii); 84 85 /// getX86RegNum - Returns the native X86 register number for the given LLVM 86 /// register identifier. 87 unsigned getX86RegNum(unsigned RegNo) const; 88 89 unsigned getStackAlignment() const { return StackAlign; } 90 91 /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum 92 /// (created by TableGen) for target dependencies. 93 int getDwarfRegNum(unsigned RegNum, bool isEH) const; 94 95 /// Code Generation virtual methods... 96 /// 97 const TargetRegisterClass * 98 getCrossCopyRegClass(const TargetRegisterClass *RC) const; 99 100 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 101 unsigned DestReg, const MachineInstr *Orig) const; 102 103 /// getCalleeSavedRegs - Return a null-terminated list of all of the 104 /// callee-save registers on this target. 105 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; 106 107 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred 108 /// register classes to spill each callee-saved register with. The order and 109 /// length of this list match the getCalleeSavedRegs() list. 110 const TargetRegisterClass* const* 111 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const; 112 113 /// getReservedRegs - Returns a bitset indexed by physical register number 114 /// indicating if a register is a special register that has particular uses and 115 /// should be considered unavailable at all times, e.g. SP, RA. This is used by 116 /// register scavenger to determine what registers are free. 117 BitVector getReservedRegs(const MachineFunction &MF) const; 118 119 bool hasFP(const MachineFunction &MF) const; 120 121 bool hasReservedCallFrame(MachineFunction &MF) const; 122 123 void eliminateCallFramePseudoInstr(MachineFunction &MF, 124 MachineBasicBlock &MBB, 125 MachineBasicBlock::iterator MI) const; 126 127 void eliminateFrameIndex(MachineBasicBlock::iterator MI, 128 int SPAdj, RegScavenger *RS = NULL) const; 129 130 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const; 131 132 void emitPrologue(MachineFunction &MF) const; 133 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; 134 135 // Debug information queries. 136 unsigned getRARegister() const; 137 unsigned getFrameRegister(MachineFunction &MF) const; 138 int getFrameIndexOffset(MachineFunction &MF, int FI) const; 139 void getInitialFrameState(std::vector<MachineMove> &Moves) const; 140 141 // Exception handling queries. 142 unsigned getEHExceptionRegister() const; 143 unsigned getEHHandlerRegister() const; 144}; 145 146// getX86SubSuperRegister - X86 utility function. It returns the sub or super 147// register of a specific X86 register. 148// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX 149unsigned getX86SubSuperRegister(unsigned, MVT::ValueType, bool High=false); 150 151} // End llvm namespace 152 153#endif 154