X86RegisterInfo.h revision 3458e9e4dfc8689179a74e954aad78d3a4b564ff
1//===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86REGISTERINFO_H 15#define X86REGISTERINFO_H 16 17#include "llvm/Target/TargetRegisterInfo.h" 18#include "X86GenRegisterInfo.h.inc" 19 20namespace llvm { 21 class Type; 22 class TargetInstrInfo; 23 class X86TargetMachine; 24 25/// N86 namespace - Native X86 register numbers 26/// 27namespace N86 { 28 enum { 29 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 30 }; 31} 32 33/// DWARFFlavour - Flavour of dwarf regnumbers 34/// 35namespace DWARFFlavour { 36 enum { 37 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 38 }; 39} 40 41class X86RegisterInfo : public X86GenRegisterInfo { 42public: 43 X86TargetMachine &TM; 44 const TargetInstrInfo &TII; 45 46private: 47 /// Is64Bit - Is the target 64-bits. 48 /// 49 bool Is64Bit; 50 51 /// IsWin64 - Is the target on of win64 flavours 52 /// 53 bool IsWin64; 54 55 /// SlotSize - Stack slot size in bytes. 56 /// 57 unsigned SlotSize; 58 59 /// StackAlign - Default stack alignment. 60 /// 61 unsigned StackAlign; 62 63 /// StackPtr - X86 physical register used as stack ptr. 64 /// 65 unsigned StackPtr; 66 67 /// FramePtr - X86 physical register used as frame ptr. 68 /// 69 unsigned FramePtr; 70 71public: 72 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii); 73 74 /// getX86RegNum - Returns the native X86 register number for the given LLVM 75 /// register identifier. 76 static unsigned getX86RegNum(unsigned RegNo); 77 78 unsigned getStackAlignment() const { return StackAlign; } 79 80 /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum 81 /// (created by TableGen) for target dependencies. 82 int getDwarfRegNum(unsigned RegNum, bool isEH) const; 83 84 /// Code Generation virtual methods... 85 /// 86 87 /// getMatchingSuperRegClass - Return a subclass of the specified register 88 /// class A so that each register in it has a sub-register of the 89 /// specified sub-register index which is in the specified register class B. 90 virtual const TargetRegisterClass * 91 getMatchingSuperRegClass(const TargetRegisterClass *A, 92 const TargetRegisterClass *B, unsigned Idx) const; 93 94 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 95 /// values. 96 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const; 97 98 /// getCrossCopyRegClass - Returns a legal register class to copy a register 99 /// in the specified class to or from. Returns NULL if it is possible to copy 100 /// between a two registers of the specified class. 101 const TargetRegisterClass * 102 getCrossCopyRegClass(const TargetRegisterClass *RC) const; 103 104 /// getCalleeSavedRegs - Return a null-terminated list of all of the 105 /// callee-save registers on this target. 106 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; 107 108 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred 109 /// register classes to spill each callee-saved register with. The order and 110 /// length of this list match the getCalleeSavedRegs() list. 111 const TargetRegisterClass* const* 112 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const; 113 114 /// getReservedRegs - Returns a bitset indexed by physical register number 115 /// indicating if a register is a special register that has particular uses and 116 /// should be considered unavailable at all times, e.g. SP, RA. This is used by 117 /// register scavenger to determine what registers are free. 118 BitVector getReservedRegs(const MachineFunction &MF) const; 119 120 bool hasFP(const MachineFunction &MF) const; 121 122 bool canRealignStack(const MachineFunction &MF) const; 123 124 bool needsStackRealignment(const MachineFunction &MF) const; 125 126 bool hasReservedCallFrame(MachineFunction &MF) const; 127 128 bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg, 129 int &FrameIdx) const; 130 131 void eliminateCallFramePseudoInstr(MachineFunction &MF, 132 MachineBasicBlock &MBB, 133 MachineBasicBlock::iterator MI) const; 134 135 unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI, 136 int SPAdj, FrameIndexValue *Value = NULL, 137 RegScavenger *RS = NULL) const; 138 139 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 140 RegScavenger *RS = NULL) const; 141 142 void emitCalleeSavedFrameMoves(MachineFunction &MF, MCSymbol *Label, 143 unsigned FramePtr) const; 144 void emitPrologue(MachineFunction &MF) const; 145 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; 146 147 // Debug information queries. 148 unsigned getRARegister() const; 149 unsigned getFrameRegister(const MachineFunction &MF) const; 150 int getFrameIndexOffset(const MachineFunction &MF, int FI) const; 151 void getInitialFrameState(std::vector<MachineMove> &Moves) const; 152 153 // Exception handling queries. 154 unsigned getEHExceptionRegister() const; 155 unsigned getEHHandlerRegister() const; 156}; 157 158// getX86SubSuperRegister - X86 utility function. It returns the sub or super 159// register of a specific X86 register. 160// e.g. getX86SubSuperRegister(X86::EAX, EVT::i16) return X86:AX 161unsigned getX86SubSuperRegister(unsigned, EVT, bool High=false); 162 163} // End llvm namespace 164 165#endif 166