X86RegisterInfo.h revision 58184e6878fdab651bc7c9a59dab2687ca82ede2
1//===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the MRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86REGISTERINFO_H 15#define X86REGISTERINFO_H 16 17#include "llvm/ADT/DenseMap.h" 18#include "llvm/ADT/SmallVector.h" 19#include "llvm/Target/MRegisterInfo.h" 20#include "X86GenRegisterInfo.h.inc" 21 22namespace llvm { 23 class Type; 24 class TargetInstrInfo; 25 class X86TargetMachine; 26 27/// N86 namespace - Native X86 register numbers 28/// 29namespace N86 { 30 enum { 31 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 32 }; 33} 34 35class X86RegisterInfo : public X86GenRegisterInfo { 36public: 37 X86TargetMachine &TM; 38 const TargetInstrInfo &TII; 39 40private: 41 /// Is64Bit - Is the target 64-bits. 42 /// 43 bool Is64Bit; 44 45 /// SlotSize - Stack slot size in bytes. 46 /// 47 unsigned SlotSize; 48 49 /// StackPtr - X86 physical register used as stack ptr. 50 /// 51 unsigned StackPtr; 52 53 /// FramePtr - X86 physical register used as frame ptr. 54 /// 55 unsigned FramePtr; 56 57 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 58 /// RegOp2MemOpTable2 - Load / store folding opcode maps. 59 /// 60 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr; 61 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0; 62 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1; 63 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2; 64 65 /// MemOp2RegOpTable - Load / store unfolding opcode map. 66 /// 67 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; 68 69public: 70 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii); 71 72 /// getX86RegNum - Returns the native X86 register number for the given LLVM 73 /// register identifier. 74 unsigned getX86RegNum(unsigned RegNo); 75 76 /// Code Generation virtual methods... 77 /// 78 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 79 MachineBasicBlock::iterator MI, 80 const std::vector<CalleeSavedInfo> &CSI) const; 81 82 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 83 MachineBasicBlock::iterator MI, 84 const std::vector<CalleeSavedInfo> &CSI) const; 85 86 void storeRegToStackSlot(MachineBasicBlock &MBB, 87 MachineBasicBlock::iterator MI, 88 unsigned SrcReg, int FrameIndex, 89 const TargetRegisterClass *RC) const; 90 91 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 92 SmallVectorImpl<MachineOperand> Addr, 93 const TargetRegisterClass *RC, 94 SmallVectorImpl<MachineInstr*> &NewMIs) const; 95 96 void loadRegFromStackSlot(MachineBasicBlock &MBB, 97 MachineBasicBlock::iterator MI, 98 unsigned DestReg, int FrameIndex, 99 const TargetRegisterClass *RC) const; 100 101 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 102 SmallVectorImpl<MachineOperand> Addr, 103 const TargetRegisterClass *RC, 104 SmallVectorImpl<MachineInstr*> &NewMIs) const; 105 106 void copyRegToReg(MachineBasicBlock &MBB, 107 MachineBasicBlock::iterator MI, 108 unsigned DestReg, unsigned SrcReg, 109 const TargetRegisterClass *DestRC, 110 const TargetRegisterClass *SrcRC) const; 111 112 const TargetRegisterClass * 113 getCrossCopyRegClass(const TargetRegisterClass *RC) const; 114 115 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 116 unsigned DestReg, const MachineInstr *Orig) const; 117 118 /// foldMemoryOperand - If this target supports it, fold a load or store of 119 /// the specified stack slot into the specified machine instruction for the 120 /// specified operand. If this is possible, the target should perform the 121 /// folding and return true, otherwise it should return false. If it folds 122 /// the instruction, it is likely that the MachineInstruction the iterator 123 /// references has been changed. 124 MachineInstr* foldMemoryOperand(MachineInstr* MI, 125 unsigned OpNum, 126 int FrameIndex) const; 127 128 /// foldMemoryOperand - Same as the previous version except it allows folding 129 /// of any load and store from / to any address, not just from a specific 130 /// stack slot. 131 MachineInstr* foldMemoryOperand(MachineInstr* MI, 132 unsigned OpNum, 133 MachineInstr* LoadMI) const; 134 135 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 136 /// a store or a load and a store into two or more instruction. If this is 137 /// possible, returns true as well as the new instructions by reference. 138 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 139 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 140 SmallVectorImpl<MachineInstr*> &NewMIs) const; 141 142 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 143 SmallVectorImpl<SDNode*> &NewNodes) const; 144 145 /// getCalleeSavedRegs - Return a null-terminated list of all of the 146 /// callee-save registers on this target. 147 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; 148 149 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred 150 /// register classes to spill each callee-saved register with. The order and 151 /// length of this list match the getCalleeSavedRegs() list. 152 const TargetRegisterClass* const* 153 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const; 154 155 /// getReservedRegs - Returns a bitset indexed by physical register number 156 /// indicating if a register is a special register that has particular uses and 157 /// should be considered unavailable at all times, e.g. SP, RA. This is used by 158 /// register scavenger to determine what registers are free. 159 BitVector getReservedRegs(const MachineFunction &MF) const; 160 161 bool hasFP(const MachineFunction &MF) const; 162 163 bool hasReservedCallFrame(MachineFunction &MF) const; 164 165 void eliminateCallFramePseudoInstr(MachineFunction &MF, 166 MachineBasicBlock &MBB, 167 MachineBasicBlock::iterator MI) const; 168 169 void eliminateFrameIndex(MachineBasicBlock::iterator MI, 170 int SPAdj, RegScavenger *RS = NULL) const; 171 172 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const; 173 174 void emitPrologue(MachineFunction &MF) const; 175 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; 176 177 // Debug information queries. 178 unsigned getRARegister() const; 179 unsigned getFrameRegister(MachineFunction &MF) const; 180 void getInitialFrameState(std::vector<MachineMove> &Moves) const; 181 182 // Exception handling queries. 183 unsigned getEHExceptionRegister() const; 184 unsigned getEHHandlerRegister() const; 185 186private: 187 MachineInstr* foldMemoryOperand(MachineInstr* MI, 188 unsigned OpNum, 189 SmallVector<MachineOperand,4> &MOs) const; 190}; 191 192// getX86SubSuperRegister - X86 utility function. It returns the sub or super 193// register of a specific X86 register. 194// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX 195unsigned getX86SubSuperRegister(unsigned, MVT::ValueType, bool High=false); 196 197} // End llvm namespace 198 199#endif 200