X86RegisterInfo.h revision b51dce3013b4370691469f415f54f1b7b7b0fdf1
1//===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86REGISTERINFO_H 15#define X86REGISTERINFO_H 16 17#include "llvm/ADT/DenseMap.h" 18#include "llvm/ADT/SmallVector.h" 19#include "llvm/Target/TargetRegisterInfo.h" 20#include "X86GenRegisterInfo.h.inc" 21 22namespace llvm { 23 class Type; 24 class TargetInstrInfo; 25 class X86TargetMachine; 26 27/// N86 namespace - Native X86 register numbers 28/// 29namespace N86 { 30 enum { 31 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 32 }; 33} 34 35namespace X86 { 36 /// SubregIndex - The index of various sized subregister classes. Note that 37 /// these indices must be kept in sync with the class indices in the 38 /// X86RegisterInfo.td file. 39 enum SubregIndex { 40 SUBREG_8BIT = 1, SUBREG_16BIT = 2, SUBREG_32BIT = 3 41 }; 42} 43 44/// DWARFFlavour - Flavour of dwarf regnumbers 45/// 46namespace DWARFFlavour { 47 enum { 48 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 49 }; 50} 51 52class X86RegisterInfo : public X86GenRegisterInfo { 53public: 54 X86TargetMachine &TM; 55 const TargetInstrInfo &TII; 56 57private: 58 /// Is64Bit - Is the target 64-bits. 59 /// 60 bool Is64Bit; 61 62 /// IsWin64 - Is the target on of win64 flavours 63 /// 64 bool IsWin64; 65 66 /// SlotSize - Stack slot size in bytes. 67 /// 68 unsigned SlotSize; 69 70 /// StackAlign - Default stack alignment. 71 /// 72 unsigned StackAlign; 73 74 /// StackPtr - X86 physical register used as stack ptr. 75 /// 76 unsigned StackPtr; 77 78 /// FramePtr - X86 physical register used as frame ptr. 79 /// 80 unsigned FramePtr; 81 82public: 83 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii); 84 85 /// getX86RegNum - Returns the native X86 register number for the given LLVM 86 /// register identifier. 87 static unsigned getX86RegNum(unsigned RegNo); 88 89 unsigned getStackAlignment() const { return StackAlign; } 90 91 /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum 92 /// (created by TableGen) for target dependencies. 93 int getDwarfRegNum(unsigned RegNum, bool isEH) const; 94 95 /// Code Generation virtual methods... 96 /// 97 const TargetRegisterClass * 98 getCrossCopyRegClass(const TargetRegisterClass *RC) const; 99 100 /// getCalleeSavedRegs - Return a null-terminated list of all of the 101 /// callee-save registers on this target. 102 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; 103 104 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred 105 /// register classes to spill each callee-saved register with. The order and 106 /// length of this list match the getCalleeSavedRegs() list. 107 const TargetRegisterClass* const* 108 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const; 109 110 /// getReservedRegs - Returns a bitset indexed by physical register number 111 /// indicating if a register is a special register that has particular uses and 112 /// should be considered unavailable at all times, e.g. SP, RA. This is used by 113 /// register scavenger to determine what registers are free. 114 BitVector getReservedRegs(const MachineFunction &MF) const; 115 116 bool hasFP(const MachineFunction &MF) const; 117 118 bool needsStackRealignment(const MachineFunction &MF) const; 119 120 bool hasReservedCallFrame(MachineFunction &MF) const; 121 122 void eliminateCallFramePseudoInstr(MachineFunction &MF, 123 MachineBasicBlock &MBB, 124 MachineBasicBlock::iterator MI) const; 125 126 void eliminateFrameIndex(MachineBasicBlock::iterator MI, 127 int SPAdj, RegScavenger *RS = NULL) const; 128 129 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const; 130 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 131 RegScavenger *RS = NULL) const; 132 133 void emitPrologue(MachineFunction &MF) const; 134 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; 135 136 void emitFrameMoves(MachineFunction &MF, 137 unsigned FrameLabelId, unsigned ReadyLabelId) const; 138 139 // Debug information queries. 140 unsigned getRARegister() const; 141 unsigned getFrameRegister(MachineFunction &MF) const; 142 int getFrameIndexOffset(MachineFunction &MF, int FI) const; 143 void getInitialFrameState(std::vector<MachineMove> &Moves) const; 144 145 // Exception handling queries. 146 unsigned getEHExceptionRegister() const; 147 unsigned getEHHandlerRegister() const; 148}; 149 150// getX86SubSuperRegister - X86 utility function. It returns the sub or super 151// register of a specific X86 register. 152// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX 153unsigned getX86SubSuperRegister(unsigned, MVT::ValueType, bool High=false); 154 155} // End llvm namespace 156 157#endif 158