X86RegisterInfo.h revision e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3
1//===- X86RegisterInfo.h - X86 Register Information Impl --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86REGISTERINFO_H 15#define X86REGISTERINFO_H 16 17#include "llvm/Target/TargetRegisterInfo.h" 18#include "X86GenRegisterInfo.h.inc" 19 20namespace llvm { 21 class Type; 22 class TargetInstrInfo; 23 class X86TargetMachine; 24 25/// N86 namespace - Native X86 register numbers 26/// 27namespace N86 { 28 enum { 29 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 30 }; 31} 32 33namespace X86 { 34 /// SubregIndex - The index of various sized subregister classes. Note that 35 /// these indices must be kept in sync with the class indices in the 36 /// X86RegisterInfo.td file. 37 enum SubregIndex { 38 SUBREG_8BIT = 1, SUBREG_8BIT_HI = 2, SUBREG_16BIT = 3, SUBREG_32BIT = 4 39 }; 40} 41 42/// DWARFFlavour - Flavour of dwarf regnumbers 43/// 44namespace DWARFFlavour { 45 enum { 46 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 47 }; 48} 49 50class X86RegisterInfo : public X86GenRegisterInfo { 51public: 52 X86TargetMachine &TM; 53 const TargetInstrInfo &TII; 54 55private: 56 /// Is64Bit - Is the target 64-bits. 57 /// 58 bool Is64Bit; 59 60 /// IsWin64 - Is the target on of win64 flavours 61 /// 62 bool IsWin64; 63 64 /// SlotSize - Stack slot size in bytes. 65 /// 66 unsigned SlotSize; 67 68 /// StackAlign - Default stack alignment. 69 /// 70 unsigned StackAlign; 71 72 /// StackPtr - X86 physical register used as stack ptr. 73 /// 74 unsigned StackPtr; 75 76 /// FramePtr - X86 physical register used as frame ptr. 77 /// 78 unsigned FramePtr; 79 80public: 81 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii); 82 83 /// getX86RegNum - Returns the native X86 register number for the given LLVM 84 /// register identifier. 85 static unsigned getX86RegNum(unsigned RegNo); 86 87 unsigned getStackAlignment() const { return StackAlign; } 88 89 /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum 90 /// (created by TableGen) for target dependencies. 91 int getDwarfRegNum(unsigned RegNum, bool isEH) const; 92 93 /// Code Generation virtual methods... 94 /// 95 96 /// getMatchingSuperRegClass - Return a subclass of the specified register 97 /// class A so that each register in it has a sub-register of the 98 /// specified sub-register index which is in the specified register class B. 99 virtual const TargetRegisterClass * 100 getMatchingSuperRegClass(const TargetRegisterClass *A, 101 const TargetRegisterClass *B, unsigned Idx) const; 102 103 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 104 /// values. 105 const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const; 106 107 /// getCrossCopyRegClass - Returns a legal register class to copy a register 108 /// in the specified class to or from. Returns NULL if it is possible to copy 109 /// between a two registers of the specified class. 110 const TargetRegisterClass * 111 getCrossCopyRegClass(const TargetRegisterClass *RC) const; 112 113 /// getCalleeSavedRegs - Return a null-terminated list of all of the 114 /// callee-save registers on this target. 115 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; 116 117 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred 118 /// register classes to spill each callee-saved register with. The order and 119 /// length of this list match the getCalleeSavedRegs() list. 120 const TargetRegisterClass* const* 121 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const; 122 123 /// getReservedRegs - Returns a bitset indexed by physical register number 124 /// indicating if a register is a special register that has particular uses and 125 /// should be considered unavailable at all times, e.g. SP, RA. This is used by 126 /// register scavenger to determine what registers are free. 127 BitVector getReservedRegs(const MachineFunction &MF) const; 128 129 bool hasFP(const MachineFunction &MF) const; 130 131 bool canRealignStack(const MachineFunction &MF) const; 132 133 bool needsStackRealignment(const MachineFunction &MF) const; 134 135 bool hasReservedCallFrame(MachineFunction &MF) const; 136 137 bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg, 138 int &FrameIdx) const; 139 140 void eliminateCallFramePseudoInstr(MachineFunction &MF, 141 MachineBasicBlock &MBB, 142 MachineBasicBlock::iterator MI) const; 143 144 unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI, 145 int SPAdj, int *Value = NULL, 146 RegScavenger *RS = NULL) const; 147 148 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 149 RegScavenger *RS = NULL) const; 150 151 void emitCalleeSavedFrameMoves(MachineFunction &MF, unsigned LabelId, 152 unsigned FramePtr) const; 153 void emitPrologue(MachineFunction &MF) const; 154 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; 155 156 // Debug information queries. 157 unsigned getRARegister() const; 158 unsigned getFrameRegister(const MachineFunction &MF) const; 159 int getFrameIndexOffset(MachineFunction &MF, int FI) const; 160 void getInitialFrameState(std::vector<MachineMove> &Moves) const; 161 162 // Exception handling queries. 163 unsigned getEHExceptionRegister() const; 164 unsigned getEHHandlerRegister() const; 165}; 166 167// getX86SubSuperRegister - X86 utility function. It returns the sub or super 168// register of a specific X86 register. 169// e.g. getX86SubSuperRegister(X86::EAX, EVT::i16) return X86:AX 170unsigned getX86SubSuperRegister(unsigned, EVT, bool High=false); 171 172} // End llvm namespace 173 174#endif 175