X86TargetTransformInfo.cpp revision d3c965d6251e6d939f7797f8704d4e3a82f7e274
1//===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9/// \file 10/// This file implements a TargetTransformInfo analysis pass specific to the 11/// X86 target machine. It uses the target's detailed information to provide 12/// more precise answers to certain TTI queries, while letting the target 13/// independent and default TTI implementations handle the rest. 14/// 15//===----------------------------------------------------------------------===// 16 17#define DEBUG_TYPE "x86tti" 18#include "X86.h" 19#include "X86TargetMachine.h" 20#include "llvm/Analysis/TargetTransformInfo.h" 21#include "llvm/Support/Debug.h" 22#include "llvm/Target/TargetLowering.h" 23using namespace llvm; 24 25// Declare the pass initialization routine locally as target-specific passes 26// don't havve a target-wide initialization entry point, and so we rely on the 27// pass constructor initialization. 28namespace llvm { 29void initializeX86TTIPass(PassRegistry &); 30} 31 32namespace { 33 34class X86TTI : public ImmutablePass, public TargetTransformInfo { 35 const X86TargetMachine *TM; 36 const X86Subtarget *ST; 37 const X86TargetLowering *TLI; 38 39 /// Estimate the overhead of scalarizing an instruction. Insert and Extract 40 /// are set if the result needs to be inserted and/or extracted from vectors. 41 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const; 42 43public: 44 X86TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) { 45 llvm_unreachable("This pass cannot be directly constructed"); 46 } 47 48 X86TTI(const X86TargetMachine *TM) 49 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()), 50 TLI(TM->getTargetLowering()) { 51 initializeX86TTIPass(*PassRegistry::getPassRegistry()); 52 } 53 54 virtual void initializePass() { 55 pushTTIStack(this); 56 } 57 58 virtual void finalizePass() { 59 popTTIStack(); 60 } 61 62 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 63 TargetTransformInfo::getAnalysisUsage(AU); 64 } 65 66 /// Pass identification. 67 static char ID; 68 69 /// Provide necessary pointer adjustments for the two base classes. 70 virtual void *getAdjustedAnalysisPointer(const void *ID) { 71 if (ID == &TargetTransformInfo::ID) 72 return (TargetTransformInfo*)this; 73 return this; 74 } 75 76 /// \name Scalar TTI Implementations 77 /// @{ 78 virtual PopcntSupportKind getPopcntSupport(unsigned TyWidth) const; 79 80 /// @} 81 82 /// \name Vector TTI Implementations 83 /// @{ 84 85 virtual unsigned getNumberOfRegisters(bool Vector) const; 86 virtual unsigned getRegisterBitWidth(bool Vector) const; 87 virtual unsigned getMaximumUnrollFactor() const; 88 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const; 89 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp, 90 int Index, Type *SubTp) const; 91 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst, 92 Type *Src) const; 93 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 94 Type *CondTy) const; 95 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val, 96 unsigned Index) const; 97 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src, 98 unsigned Alignment, 99 unsigned AddressSpace) const; 100 101 /// @} 102}; 103 104} // end anonymous namespace 105 106INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti", 107 "X86 Target Transform Info", true, true, false) 108char X86TTI::ID = 0; 109 110ImmutablePass * 111llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) { 112 return new X86TTI(TM); 113} 114 115 116//===----------------------------------------------------------------------===// 117// 118// X86 cost model. 119// 120//===----------------------------------------------------------------------===// 121 122X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const { 123 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 124 // TODO: Currently the __builtin_popcount() implementation using SSE3 125 // instructions is inefficient. Once the problem is fixed, we should 126 // call ST->hasSSE3() instead of ST->hasSSE4(). 127 return ST->hasSSE41() ? PSK_FastHardware : PSK_Software; 128} 129 130unsigned X86TTI::getNumberOfRegisters(bool Vector) const { 131 if (Vector && !ST->hasSSE1()) 132 return 0; 133 134 if (ST->is64Bit()) 135 return 16; 136 return 8; 137} 138 139unsigned X86TTI::getRegisterBitWidth(bool Vector) const { 140 if (Vector) { 141 if (ST->hasAVX()) return 256; 142 if (ST->hasSSE1()) return 128; 143 return 0; 144 } 145 146 if (ST->is64Bit()) 147 return 64; 148 return 32; 149 150} 151 152unsigned X86TTI::getMaximumUnrollFactor() const { 153 if (ST->isAtom()) 154 return 1; 155 156 // Sandybridge and Haswell have multiple execution ports and pipelined 157 // vector units. 158 if (ST->hasAVX()) 159 return 4; 160 161 return 2; 162} 163 164unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty) const { 165 // Legalize the type. 166 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty); 167 168 int ISD = TLI->InstructionOpcodeToISD(Opcode); 169 assert(ISD && "Invalid opcode"); 170 171 // We don't have to scalarize unsupported ops. We can issue two half-sized 172 // operations and we only need to extract the upper YMM half. 173 // Two ops + 1 extract + 1 insert = 4. 174 static const CostTableEntry AVX1CostTable[] = { 175 { ISD::MUL, { MVT::v8i32 }, 4 }, 176 { ISD::SUB, { MVT::v8i32 }, 4 }, 177 { ISD::ADD, { MVT::v8i32 }, 4 }, 178 { ISD::MUL, { MVT::v4i64 }, 4 }, 179 { ISD::SUB, { MVT::v4i64 }, 4 }, 180 { ISD::ADD, { MVT::v4i64 }, 4 }, 181 }; 182 UnaryCostTable costTable (AVX1CostTable, array_lengthof(AVX1CostTable)); 183 184 // Look for AVX1 lowering tricks. 185 if (ST->hasAVX()) { 186 unsigned cost = costTable.findCost(ISD, LT.second); 187 if (cost != BinaryCostTable::COST_NOT_FOUND) 188 return LT.first * cost; 189 } 190 // Fallback to the default implementation. 191 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty); 192} 193 194unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index, 195 Type *SubTp) const { 196 // We only estimate the cost of reverse shuffles. 197 if (Kind != SK_Reverse) 198 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp); 199 200 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp); 201 unsigned Cost = 1; 202 if (LT.second.getSizeInBits() > 128) 203 Cost = 3; // Extract + insert + copy. 204 205 // Multiple by the number of parts. 206 return Cost * LT.first; 207} 208 209unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const { 210 int ISD = TLI->InstructionOpcodeToISD(Opcode); 211 assert(ISD && "Invalid opcode"); 212 213 EVT SrcTy = TLI->getValueType(Src); 214 EVT DstTy = TLI->getValueType(Dst); 215 216 if (!SrcTy.isSimple() || !DstTy.isSimple()) 217 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src); 218 219 static const CostTableEntry AVXConversionTbl[] = { 220 { ISD::SIGN_EXTEND, { MVT::v8i32, MVT::v8i16 }, 1 }, 221 { ISD::ZERO_EXTEND, { MVT::v8i32, MVT::v8i16 }, 1 }, 222 { ISD::SIGN_EXTEND, { MVT::v4i64, MVT::v4i32 }, 1 }, 223 { ISD::ZERO_EXTEND, { MVT::v4i64, MVT::v4i32 }, 1 }, 224 { ISD::TRUNCATE, { MVT::v4i32, MVT::v4i64 }, 1 }, 225 { ISD::TRUNCATE, { MVT::v8i16, MVT::v8i32 }, 1 }, 226 { ISD::SINT_TO_FP, { MVT::v8f32, MVT::v8i8 }, 1 }, 227 { ISD::SINT_TO_FP, { MVT::v4f32, MVT::v4i8 }, 1 }, 228 { ISD::UINT_TO_FP, { MVT::v8f32, MVT::v8i8 }, 1 }, 229 { ISD::UINT_TO_FP, { MVT::v4f32, MVT::v4i8 }, 1 }, 230 { ISD::FP_TO_SINT, { MVT::v8i8, MVT::v8f32 }, 1 }, 231 { ISD::FP_TO_SINT, { MVT::v4i8, MVT::v4f32 }, 1 }, 232 { ISD::ZERO_EXTEND, { MVT::v8i32, MVT::v8i1 }, 6 }, 233 { ISD::SIGN_EXTEND, { MVT::v8i32, MVT::v8i1 }, 9 }, 234 { ISD::TRUNCATE, { MVT::v8i32, MVT::v8i64 }, 3 } 235 }; 236 BinaryCostTable costTable (AVXConversionTbl, array_lengthof(AVXConversionTbl)); 237 238 if (ST->hasAVX()) { 239 unsigned cost = costTable.findCost(ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT()); 240 if (cost != BinaryCostTable::COST_NOT_FOUND) 241 return cost; 242 } 243 244 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src); 245} 246 247unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 248 Type *CondTy) const { 249 // Legalize the type. 250 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy); 251 252 MVT MTy = LT.second; 253 254 int ISD = TLI->InstructionOpcodeToISD(Opcode); 255 assert(ISD && "Invalid opcode"); 256 257 static const CostTableEntry SSE42CostTbl[] = { 258 { ISD::SETCC, { MVT::v2f64 }, 1 }, 259 { ISD::SETCC, { MVT::v4f32 }, 1 }, 260 { ISD::SETCC, { MVT::v2i64 }, 1 }, 261 { ISD::SETCC, { MVT::v4i32 }, 1 }, 262 { ISD::SETCC, { MVT::v8i16 }, 1 }, 263 { ISD::SETCC, { MVT::v16i8 }, 1 }, 264 }; 265 UnaryCostTable costTableSSE4 (SSE42CostTbl, array_lengthof(SSE42CostTbl)); 266 267 static const CostTableEntry AVX1CostTbl[] = { 268 { ISD::SETCC, { MVT::v4f64 }, 1 }, 269 { ISD::SETCC, { MVT::v8f32 }, 1 }, 270 // AVX1 does not support 8-wide integer compare. 271 { ISD::SETCC, { MVT::v4i64 }, 4 }, 272 { ISD::SETCC, { MVT::v8i32 }, 4 }, 273 { ISD::SETCC, { MVT::v16i16 }, 4 }, 274 { ISD::SETCC, { MVT::v32i8 }, 4 }, 275 }; 276 UnaryCostTable costTableAVX1 (AVX1CostTbl, array_lengthof(AVX1CostTbl)); 277 278 static const CostTableEntry AVX2CostTbl[] = { 279 { ISD::SETCC, { MVT::v4i64 }, 1 }, 280 { ISD::SETCC, { MVT::v8i32 }, 1 }, 281 { ISD::SETCC, { MVT::v16i16 }, 1 }, 282 { ISD::SETCC, { MVT::v32i8 }, 1 }, 283 }; 284 UnaryCostTable costTableAVX2 (AVX2CostTbl, array_lengthof(AVX2CostTbl)); 285 286 if (ST->hasAVX2()) { 287 unsigned cost = costTableAVX2.findCost(ISD, MTy); 288 if (cost != BinaryCostTable::COST_NOT_FOUND) 289 return LT.first * cost; 290 } 291 292 if (ST->hasAVX()) { 293 unsigned cost = costTableAVX1.findCost(ISD, MTy); 294 if (cost != BinaryCostTable::COST_NOT_FOUND) 295 return LT.first * cost; 296 } 297 298 if (ST->hasSSE42()) { 299 unsigned cost = costTableSSE4.findCost(ISD, MTy); 300 if (cost != BinaryCostTable::COST_NOT_FOUND) 301 return LT.first * cost; 302 } 303 304 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy); 305} 306 307unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val, 308 unsigned Index) const { 309 assert(Val->isVectorTy() && "This must be a vector type"); 310 311 if (Index != -1U) { 312 // Legalize the type. 313 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val); 314 315 // This type is legalized to a scalar type. 316 if (!LT.second.isVector()) 317 return 0; 318 319 // The type may be split. Normalize the index to the new type. 320 unsigned Width = LT.second.getVectorNumElements(); 321 Index = Index % Width; 322 323 // Floating point scalars are already located in index #0. 324 if (Val->getScalarType()->isFloatingPointTy() && Index == 0) 325 return 0; 326 } 327 328 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index); 329} 330 331unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 332 unsigned AddressSpace) const { 333 // Legalize the type. 334 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src); 335 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 336 "Invalid Opcode"); 337 338 // Each load/store unit costs 1. 339 unsigned Cost = LT.first * 1; 340 341 // On Sandybridge 256bit load/stores are double pumped 342 // (but not on Haswell). 343 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2()) 344 Cost*=2; 345 346 return Cost; 347} 348