1/*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2011 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24#include "r300_chipset.h"
25
26#include "util/u_debug.h"
27
28#include <stdio.h>
29
30/* r300_chipset: A file all to itself for deducing the various properties of
31 * Radeons. */
32
33/* Parse a PCI ID and fill an r300_capabilities struct with information. */
34void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps)
35{
36    switch (pci_id) {
37#define CHIPSET(pci_id, name, chipfamily) \
38        case pci_id: \
39            caps->family = CHIP_FAMILY_##chipfamily; \
40            break;
41#include "pci_ids/r300_pci_ids.h"
42#undef CHIPSET
43
44    default:
45        fprintf(stderr, "r300: Warning: Unknown chipset 0x%x\nAborting...",
46                pci_id);
47        abort();
48    }
49
50    /* Defaults. */
51    caps->high_second_pipe = FALSE;
52    caps->num_vert_fpus = 0;
53    caps->hiz_ram = 0;
54    caps->zmask_ram = 0;
55
56
57    switch (caps->family) {
58    case CHIP_FAMILY_R300:
59    case CHIP_FAMILY_R350:
60        caps->high_second_pipe = TRUE;
61        caps->num_vert_fpus = 4;
62        caps->hiz_ram = R300_HIZ_LIMIT;
63        caps->zmask_ram = PIPE_ZMASK_SIZE;
64        break;
65
66    case CHIP_FAMILY_RV350:
67    case CHIP_FAMILY_RV370:
68        caps->high_second_pipe = TRUE;
69        caps->num_vert_fpus = 2;
70        caps->zmask_ram = RV3xx_ZMASK_SIZE;
71        break;
72
73    case CHIP_FAMILY_RV380:
74        caps->high_second_pipe = TRUE;
75        caps->num_vert_fpus = 2;
76        caps->hiz_ram = R300_HIZ_LIMIT;
77        caps->zmask_ram = RV3xx_ZMASK_SIZE;
78        break;
79
80    case CHIP_FAMILY_RS400:
81    case CHIP_FAMILY_RS600:
82    case CHIP_FAMILY_RS690:
83    case CHIP_FAMILY_RS740:
84        break;
85
86    case CHIP_FAMILY_RC410:
87    case CHIP_FAMILY_RS480:
88        caps->zmask_ram = RV3xx_ZMASK_SIZE;
89        break;
90
91    case CHIP_FAMILY_R420:
92    case CHIP_FAMILY_R423:
93    case CHIP_FAMILY_R430:
94    case CHIP_FAMILY_R480:
95    case CHIP_FAMILY_R481:
96    case CHIP_FAMILY_RV410:
97        caps->num_vert_fpus = 6;
98        caps->hiz_ram = R300_HIZ_LIMIT;
99        caps->zmask_ram = PIPE_ZMASK_SIZE;
100        break;
101
102    case CHIP_FAMILY_R520:
103        caps->num_vert_fpus = 8;
104        caps->hiz_ram = R300_HIZ_LIMIT;
105        caps->zmask_ram = PIPE_ZMASK_SIZE;
106        break;
107
108    case CHIP_FAMILY_RV515:
109        caps->num_vert_fpus = 2;
110        caps->hiz_ram = R300_HIZ_LIMIT;
111        caps->zmask_ram = PIPE_ZMASK_SIZE;
112        break;
113
114    case CHIP_FAMILY_RV530:
115        caps->num_vert_fpus = 5;
116        caps->hiz_ram = RV530_HIZ_LIMIT;
117        caps->zmask_ram = PIPE_ZMASK_SIZE;
118        break;
119
120    case CHIP_FAMILY_R580:
121    case CHIP_FAMILY_RV560:
122    case CHIP_FAMILY_RV570:
123        caps->num_vert_fpus = 8;
124        caps->hiz_ram = RV530_HIZ_LIMIT;
125        caps->zmask_ram = PIPE_ZMASK_SIZE;
126        break;
127    }
128
129    caps->num_tex_units = 16;
130    caps->is_r400 = caps->family >= CHIP_FAMILY_R420 && caps->family < CHIP_FAMILY_RV515;
131    caps->is_r500 = caps->family >= CHIP_FAMILY_RV515;
132    caps->is_rv350 = caps->family >= CHIP_FAMILY_RV350;
133    caps->z_compress = caps->is_rv350 ? R300_ZCOMP_8X8 : R300_ZCOMP_4X4;
134    caps->dxtc_swizzle = caps->is_r400 || caps->is_r500;
135    caps->has_us_format = caps->family == CHIP_FAMILY_R520;
136    caps->has_tcl = caps->num_vert_fpus > 0;
137
138    if (caps->has_tcl) {
139        caps->has_tcl = debug_get_bool_option("RADEON_NO_TCL", FALSE) ? FALSE : TRUE;
140    }
141}
142