1fa63f976522bd4faf19249e8c9ac4d3edda498d9Tom Stellard//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===// 2a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 3a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// The LLVM Compiler Infrastructure 4a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 5a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// This file is distributed under the University of Illinois Open Source 6a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// License. See LICENSE.TXT for details. 7a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 8a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard//===----------------------------------------------------------------------===// 9a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 10fa63f976522bd4faf19249e8c9ac4d3edda498d9Tom Stellard// The file contains the R600 implementation of the TargetRegisterInfo class. 11a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 12a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard//===----------------------------------------------------------------------===// 13a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 14a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "R600RegisterInfo.h" 15a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "AMDGPUTargetMachine.h" 168a4c25dd7e9002ab7a2821753bcae1ff6af2ca1cTom Stellard#include "R600MachineFunctionInfo.h" 17a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 18a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardusing namespace llvm; 19a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 20a75c6163e605f35b14f26930dd9227e4f337ec9eTom StellardR600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm, 21a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard const TargetInstrInfo &tii) 22a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard: AMDGPURegisterInfo(tm, tii), 23a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard TM(tm), 24a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard TII(tii) 25a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard { } 26a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 27a75c6163e605f35b14f26930dd9227e4f337ec9eTom StellardBitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const 28a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 29a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard BitVector Reserved(getNumRegs()); 308a4c25dd7e9002ab7a2821753bcae1ff6af2ca1cTom Stellard const R600MachineFunctionInfo * MFI = MF.getInfo<R600MachineFunctionInfo>(); 318a4c25dd7e9002ab7a2821753bcae1ff6af2ca1cTom Stellard 3276b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard Reserved.set(AMDGPU::ZERO); 3376b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard Reserved.set(AMDGPU::HALF); 3476b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard Reserved.set(AMDGPU::ONE); 3576b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard Reserved.set(AMDGPU::ONE_INT); 3676b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard Reserved.set(AMDGPU::NEG_HALF); 3776b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard Reserved.set(AMDGPU::NEG_ONE); 3876b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard Reserved.set(AMDGPU::PV_X); 3976b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard Reserved.set(AMDGPU::ALU_LITERAL_X); 408263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune Reserved.set(AMDGPU::PREDICATE_BIT); 418263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune Reserved.set(AMDGPU::PRED_SEL_OFF); 428263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune Reserved.set(AMDGPU::PRED_SEL_ZERO); 438263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune Reserved.set(AMDGPU::PRED_SEL_ONE); 44a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 4576b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard for (TargetRegisterClass::iterator I = AMDGPU::R600_CReg32RegClass.begin(), 4676b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard E = AMDGPU::R600_CReg32RegClass.end(); I != E; ++I) { 47a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard Reserved.set(*I); 48a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard } 49a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 508a4c25dd7e9002ab7a2821753bcae1ff6af2ca1cTom Stellard for (std::vector<unsigned>::const_iterator I = MFI->ReservedRegs.begin(), 518a4c25dd7e9002ab7a2821753bcae1ff6af2ca1cTom Stellard E = MFI->ReservedRegs.end(); I != E; ++I) { 528a4c25dd7e9002ab7a2821753bcae1ff6af2ca1cTom Stellard Reserved.set(*I); 53a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard } 548a4c25dd7e9002ab7a2821753bcae1ff6af2ca1cTom Stellard 55a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard return Reserved; 56a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 57a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 58a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardconst TargetRegisterClass * 59a75c6163e605f35b14f26930dd9227e4f337ec9eTom StellardR600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const 60a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 61a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard switch (rc->getID()) { 6276b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::GPRF32RegClassID: 6376b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::GPRI32RegClassID: 6476b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard return &AMDGPU::R600_Reg32RegClass; 65a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard default: return rc; 66a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard } 67a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 68a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 69a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardunsigned R600RegisterInfo::getHWRegIndex(unsigned reg) const 70a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 71a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard switch(reg) { 7276b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::ZERO: return 248; 7376b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::ONE: 7476b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::NEG_ONE: return 249; 7576b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::ONE_INT: return 250; 7676b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::HALF: 7776b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::NEG_HALF: return 252; 7876b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::ALU_LITERAL_X: return 253; 798263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune case AMDGPU::PREDICATE_BIT: 808263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune case AMDGPU::PRED_SEL_OFF: 818263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune case AMDGPU::PRED_SEL_ZERO: 828263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune case AMDGPU::PRED_SEL_ONE: 838263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune return 0; 84a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard default: return getHWRegIndexGen(reg); 85a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard } 86a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 87a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 88a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardunsigned R600RegisterInfo::getHWRegChan(unsigned reg) const 89a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 90a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard switch(reg) { 9176b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::ZERO: 9276b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::ONE: 9376b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::ONE_INT: 9476b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::NEG_ONE: 9576b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::HALF: 9676b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::NEG_HALF: 9776b44034b9b234d3db4012342f0fae677d4f10f6Tom Stellard case AMDGPU::ALU_LITERAL_X: 988263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune case AMDGPU::PREDICATE_BIT: 998263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune case AMDGPU::PRED_SEL_OFF: 1008263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune case AMDGPU::PRED_SEL_ZERO: 1018263408a91b6b3beb5af5de6bdc7e5d13197a268Vincent Lejeune case AMDGPU::PRED_SEL_ONE: 102a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard return 0; 103a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard default: return getHWRegChanGen(reg); 104a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard } 105a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 106a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 107d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellardconst TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( 108d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard MVT VT) const 109d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard{ 110d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard switch(VT.SimpleTy) { 111d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard default: 112228a6641ccddaf24a993f827af1e97379785985aTom Stellard case MVT::i32: return &AMDGPU::R600_TReg32RegClass; 113d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard } 114d6c2d3722d795381d3cdf11fe00f63780ad0725aTom Stellard} 11505882985757e655f5298af483c881008d45e6249Tom Stellard 11605882985757e655f5298af483c881008d45e6249Tom Stellardunsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const 11705882985757e655f5298af483c881008d45e6249Tom Stellard{ 11805882985757e655f5298af483c881008d45e6249Tom Stellard switch (Channel) { 11905882985757e655f5298af483c881008d45e6249Tom Stellard default: assert(!"Invalid channel index"); return 0; 12005882985757e655f5298af483c881008d45e6249Tom Stellard case 0: return AMDGPU::sel_x; 12105882985757e655f5298af483c881008d45e6249Tom Stellard case 1: return AMDGPU::sel_y; 12205882985757e655f5298af483c881008d45e6249Tom Stellard case 2: return AMDGPU::sel_z; 12305882985757e655f5298af483c881008d45e6249Tom Stellard case 3: return AMDGPU::sel_w; 12405882985757e655f5298af483c881008d45e6249Tom Stellard } 12505882985757e655f5298af483c881008d45e6249Tom Stellard} 12605882985757e655f5298af483c881008d45e6249Tom Stellard 127a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "R600HwRegInfo.include" 128