brw_tex_layout.c revision 477b74e85be8e468c63af9f2f3fe788e486764ce 
1/*
2 Copyright (C) Intel Corp.  2006.  All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28  * Authors:
29  *   Keith Whitwell <keith@tungstengraphics.com>
30  */
31
32/* Code to layout images in a mipmap tree for i965.
33 */
34
35#include "intel_mipmap_tree.h"
36#include "intel_tex_layout.h"
37#include "intel_context.h"
38#include "main/macros.h"
39
40#define FILE_DEBUG_FLAG DEBUG_MIPTREE
41
42GLboolean brw_miptree_layout(struct intel_context *intel,
43			     struct intel_mipmap_tree *mt,
44			     uint32_t tiling)
45{
46   /* XXX: these vary depending on image format: */
47   /* GLint align_w = 4; */
48
49   switch (mt->target) {
50   case GL_TEXTURE_CUBE_MAP:
51      if (intel->gen >= 5) {
52          GLuint align_w;
53          GLuint align_h;
54          GLuint level;
55          GLuint qpitch = 0;
56	  int h0, h1, q;
57
58	  intel_get_texture_alignment_unit(mt->format, &align_w, &align_h);
59
60	  /* On Ironlake, cube maps are finally represented as just a series
61	   * of MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated
62	   * by a pitch of qpitch rows, where qpitch is defined by the equation
63	   * given in Volume 1 of the BSpec.
64	   */
65	  h0 = ALIGN(mt->height0, align_h);
66	  h1 = ALIGN(minify(mt->height0), align_h);
67	  qpitch = (h0 + h1 + (intel->gen >= 7 ? 12 : 11) * align_h);
68          if (mt->compressed)
69	     qpitch /= 4;
70
71	  i945_miptree_layout_2d(intel, mt, tiling, 6);
72
73          for (level = mt->first_level; level <= mt->last_level; level++) {
74	     for (q = 0; q < 6; q++) {
75		intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
76	     }
77          }
78	  mt->total_height = qpitch * 6;
79
80          break;
81      }
82
83   case GL_TEXTURE_3D: {
84      GLuint width  = mt->width0;
85      GLuint height = mt->height0;
86      GLuint depth = mt->depth0;
87      GLuint pack_x_pitch, pack_x_nr;
88      GLuint pack_y_pitch;
89      GLuint level;
90      GLuint align_h = 2;
91      GLuint align_w = 4;
92
93      mt->total_height = 0;
94      intel_get_texture_alignment_unit(mt->format, &align_w, &align_h);
95
96      if (mt->compressed) {
97          mt->total_width = ALIGN(width, align_w);
98          pack_y_pitch = (height + 3) / 4;
99      } else {
100	 mt->total_width = mt->width0;
101	 pack_y_pitch = ALIGN(mt->height0, align_h);
102      }
103
104      pack_x_pitch = width;
105      pack_x_nr = 1;
106
107      for (level = mt->first_level ; level <= mt->last_level ; level++) {
108	 GLuint nr_images = mt->target == GL_TEXTURE_3D ? depth : 6;
109	 GLint x = 0;
110	 GLint y = 0;
111	 GLint q, j;
112
113	 intel_miptree_set_level_info(mt, level, nr_images,
114				      0, mt->total_height,
115				      width, height, depth);
116
117	 for (q = 0; q < nr_images;) {
118	    for (j = 0; j < pack_x_nr && q < nr_images; j++, q++) {
119	       intel_miptree_set_image_offset(mt, level, q, x, y);
120	       x += pack_x_pitch;
121	    }
122
123	    x = 0;
124	    y += pack_y_pitch;
125	 }
126
127
128	 mt->total_height += y;
129	 width  = minify(width);
130	 height = minify(height);
131	 depth  = minify(depth);
132
133	 if (mt->compressed) {
134	    pack_y_pitch = (height + 3) / 4;
135
136	    if (pack_x_pitch > ALIGN(width, align_w)) {
137	       pack_x_pitch = ALIGN(width, align_w);
138	       pack_x_nr <<= 1;
139	    }
140	 } else {
141	    if (pack_x_pitch > 4) {
142	       pack_x_pitch >>= 1;
143	       pack_x_nr <<= 1;
144	       assert(pack_x_pitch * pack_x_nr <= mt->total_width);
145	    }
146
147	    if (pack_y_pitch > 2) {
148	       pack_y_pitch >>= 1;
149	       pack_y_pitch = ALIGN(pack_y_pitch, align_h);
150	    }
151	 }
152
153      }
154      /* The 965's sampler lays cachelines out according to how accesses
155       * in the texture surfaces run, so they may be "vertical" through
156       * memory.  As a result, the docs say in Surface Padding Requirements:
157       * Sampling Engine Surfaces that two extra rows of padding are required.
158       */
159      if (mt->target == GL_TEXTURE_CUBE_MAP)
160	 mt->total_height += 2;
161      break;
162   }
163
164   default:
165      i945_miptree_layout_2d(intel, mt, tiling, 1);
166      break;
167   }
168   DBG("%s: %dx%dx%d\n", __FUNCTION__,
169       mt->total_width, mt->total_height, mt->cpp);
170
171   return GL_TRUE;
172}
173
174