brw_tex_layout.c revision d7cdbc3c5415d2dd5eee58834b13714a89eacf2b 
1/*
2 Copyright (C) Intel Corp.  2006.  All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28  * Authors:
29  *   Keith Whitwell <keith@tungstengraphics.com>
30  */
31
32/* Code to layout images in a mipmap tree for i965.
33 */
34
35#include "intel_mipmap_tree.h"
36#include "intel_tex_layout.h"
37#include "intel_context.h"
38#include "main/macros.h"
39
40#define FILE_DEBUG_FLAG DEBUG_MIPTREE
41
42void
43brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
44{
45   /* XXX: these vary depending on image format: */
46   /* GLint align_w = 4; */
47
48   switch (mt->target) {
49   case GL_TEXTURE_CUBE_MAP:
50      if (intel->gen >= 5) {
51          GLuint align_w;
52          GLuint align_h;
53          GLuint level;
54          GLuint qpitch = 0;
55	  int h0, h1, q;
56
57	  intel_get_texture_alignment_unit(mt->format, &align_w, &align_h);
58
59	  /* On Ironlake, cube maps are finally represented as just a series
60	   * of MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated
61	   * by a pitch of qpitch rows, where qpitch is defined by the equation
62	   * given in Volume 1 of the BSpec.
63	   */
64	  h0 = ALIGN(mt->height0, align_h);
65	  h1 = ALIGN(minify(mt->height0), align_h);
66	  qpitch = (h0 + h1 + (intel->gen >= 7 ? 12 : 11) * align_h);
67          if (mt->compressed)
68	     qpitch /= 4;
69
70	  i945_miptree_layout_2d(mt, 6);
71
72          for (level = mt->first_level; level <= mt->last_level; level++) {
73	     for (q = 0; q < 6; q++) {
74		intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
75	     }
76          }
77	  mt->total_height = qpitch * 6;
78
79          break;
80      }
81
82   case GL_TEXTURE_3D: {
83      GLuint width  = mt->width0;
84      GLuint height = mt->height0;
85      GLuint depth = mt->depth0;
86      GLuint pack_x_pitch, pack_x_nr;
87      GLuint pack_y_pitch;
88      GLuint level;
89      GLuint align_h = 2;
90      GLuint align_w = 4;
91
92      mt->total_height = 0;
93      intel_get_texture_alignment_unit(mt->format, &align_w, &align_h);
94
95      if (mt->compressed) {
96          mt->total_width = ALIGN(width, align_w);
97          pack_y_pitch = (height + 3) / 4;
98      } else {
99	 mt->total_width = mt->width0;
100	 pack_y_pitch = ALIGN(mt->height0, align_h);
101      }
102
103      pack_x_pitch = width;
104      pack_x_nr = 1;
105
106      for (level = mt->first_level ; level <= mt->last_level ; level++) {
107	 GLuint nr_images = mt->target == GL_TEXTURE_3D ? depth : 6;
108	 GLint x = 0;
109	 GLint y = 0;
110	 GLint q, j;
111
112	 intel_miptree_set_level_info(mt, level, nr_images,
113				      0, mt->total_height,
114				      width, height, depth);
115
116	 for (q = 0; q < nr_images;) {
117	    for (j = 0; j < pack_x_nr && q < nr_images; j++, q++) {
118	       intel_miptree_set_image_offset(mt, level, q, x, y);
119	       x += pack_x_pitch;
120	    }
121
122	    x = 0;
123	    y += pack_y_pitch;
124	 }
125
126
127	 mt->total_height += y;
128	 width  = minify(width);
129	 height = minify(height);
130	 depth  = minify(depth);
131
132	 if (mt->compressed) {
133	    pack_y_pitch = (height + 3) / 4;
134
135	    if (pack_x_pitch > ALIGN(width, align_w)) {
136	       pack_x_pitch = ALIGN(width, align_w);
137	       pack_x_nr <<= 1;
138	    }
139	 } else {
140	    if (pack_x_pitch > 4) {
141	       pack_x_pitch >>= 1;
142	       pack_x_nr <<= 1;
143	       assert(pack_x_pitch * pack_x_nr <= mt->total_width);
144	    }
145
146	    if (pack_y_pitch > 2) {
147	       pack_y_pitch >>= 1;
148	       pack_y_pitch = ALIGN(pack_y_pitch, align_h);
149	    }
150	 }
151
152      }
153      /* The 965's sampler lays cachelines out according to how accesses
154       * in the texture surfaces run, so they may be "vertical" through
155       * memory.  As a result, the docs say in Surface Padding Requirements:
156       * Sampling Engine Surfaces that two extra rows of padding are required.
157       */
158      if (mt->target == GL_TEXTURE_CUBE_MAP)
159	 mt->total_height += 2;
160      break;
161   }
162
163   default:
164      i945_miptree_layout_2d(mt, 1);
165      break;
166   }
167   DBG("%s: %dx%dx%d\n", __FUNCTION__,
168       mt->total_width, mt->total_height, mt->cpp);
169}
170
171