radeon_mipmap_tree.c revision b5e256c76dea2182c82af2a4f66224735701d55a
1/* 2 * Copyright (C) 2009 Maciej Cencora. 3 * Copyright (C) 2008 Nicolai Haehnle. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sublicense, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 22 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 23 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 24 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29#include "radeon_mipmap_tree.h" 30 31#include <errno.h> 32#include <unistd.h> 33 34#include "main/simple_list.h" 35#include "main/texcompress.h" 36#include "main/teximage.h" 37#include "main/texobj.h" 38#include "radeon_texture.h" 39 40static unsigned get_aligned_compressed_row_stride( 41 gl_format format, 42 unsigned width, 43 unsigned minStride) 44{ 45 const unsigned blockSize = _mesa_get_format_bytes(format); 46 unsigned blockWidth, blockHeight, numXBlocks; 47 48 _mesa_get_format_block_size(format, &blockWidth, &blockHeight); 49 numXBlocks = (width + blockWidth - 1) / blockWidth; 50 51 while (numXBlocks * blockSize < minStride) 52 { 53 ++numXBlocks; 54 } 55 56 return numXBlocks * blockSize; 57} 58 59static unsigned get_compressed_image_size( 60 gl_format format, 61 unsigned rowStride, 62 unsigned height) 63{ 64 unsigned blockWidth, blockHeight; 65 66 _mesa_get_format_block_size(format, &blockWidth, &blockHeight); 67 68 return rowStride * ((height + blockHeight - 1) / blockHeight); 69} 70 71static int find_next_power_of_two(GLuint value) 72{ 73 int i, tmp; 74 75 i = 0; 76 tmp = value - 1; 77 while (tmp) { 78 tmp >>= 1; 79 i++; 80 } 81 return (1 << i); 82} 83 84/** 85 * Compute sizes and fill in offset and blit information for the given 86 * image (determined by \p face and \p level). 87 * 88 * \param curOffset points to the offset at which the image is to be stored 89 * and is updated by this function according to the size of the image. 90 */ 91static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt, 92 GLuint face, GLuint level, GLuint* curOffset) 93{ 94 radeon_mipmap_level *lvl = &mt->levels[level]; 95 uint32_t row_align; 96 GLuint height; 97 98 height = find_next_power_of_two(lvl->height); 99 100 /* Find image size in bytes */ 101 if (_mesa_is_format_compressed(mt->mesaFormat)) { 102 lvl->rowstride = get_aligned_compressed_row_stride(mt->mesaFormat, lvl->width, rmesa->texture_compressed_row_align); 103 lvl->size = get_compressed_image_size(mt->mesaFormat, lvl->rowstride, height); 104 } else if (mt->target == GL_TEXTURE_RECTANGLE_NV) { 105 row_align = rmesa->texture_rect_row_align - 1; 106 lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align; 107 lvl->size = lvl->rowstride * height; 108 } else if (mt->tilebits & RADEON_TXO_MICRO_TILE) { 109 /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned, 110 * though the actual offset may be different (if texture is less than 111 * 32 bytes width) to the untiled case */ 112 lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) * 2 + 31) & ~31; 113 lvl->size = lvl->rowstride * ((height + 1) / 2) * lvl->depth; 114 } else { 115 row_align = rmesa->texture_row_align - 1; 116 lvl->rowstride = (_mesa_format_row_stride(mt->mesaFormat, lvl->width) + row_align) & ~row_align; 117 lvl->size = lvl->rowstride * height * lvl->depth; 118 } 119 assert(lvl->size > 0); 120 121 /* All images are aligned to a 32-byte offset */ 122 *curOffset = (*curOffset + 0x1f) & ~0x1f; 123 lvl->faces[face].offset = *curOffset; 124 *curOffset += lvl->size; 125 126 if (RADEON_DEBUG & RADEON_TEXTURE) 127 fprintf(stderr, 128 "level %d, face %d: rs:%d %dx%d at %d\n", 129 level, face, lvl->rowstride, lvl->width, height, lvl->faces[face].offset); 130} 131 132static GLuint minify(GLuint size, GLuint levels) 133{ 134 size = size >> levels; 135 if (size < 1) 136 size = 1; 137 return size; 138} 139 140 141static void calculate_miptree_layout_r100(radeonContextPtr rmesa, radeon_mipmap_tree *mt) 142{ 143 GLuint curOffset, i, face, level; 144 145 assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels); 146 147 curOffset = 0; 148 for(face = 0; face < mt->faces; face++) { 149 150 for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) { 151 mt->levels[level].valid = 1; 152 mt->levels[level].width = minify(mt->width0, i); 153 mt->levels[level].height = minify(mt->height0, i); 154 mt->levels[level].depth = minify(mt->depth0, i); 155 compute_tex_image_offset(rmesa, mt, face, level, &curOffset); 156 } 157 } 158 159 /* Note the required size in memory */ 160 mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; 161} 162 163static void calculate_miptree_layout_r300(radeonContextPtr rmesa, radeon_mipmap_tree *mt) 164{ 165 GLuint curOffset, i, level; 166 167 assert(mt->numLevels <= rmesa->glCtx->Const.MaxTextureLevels); 168 169 curOffset = 0; 170 for(i = 0, level = mt->baseLevel; i < mt->numLevels; i++, level++) { 171 GLuint face; 172 173 mt->levels[level].valid = 1; 174 mt->levels[level].width = minify(mt->width0, i); 175 mt->levels[level].height = minify(mt->height0, i); 176 mt->levels[level].depth = minify(mt->depth0, i); 177 178 for(face = 0; face < mt->faces; face++) 179 compute_tex_image_offset(rmesa, mt, face, level, &curOffset); 180 } 181 182 /* Note the required size in memory */ 183 mt->totalsize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK; 184} 185 186/** 187 * Create a new mipmap tree, calculate its layout and allocate memory. 188 */ 189static radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, 190 GLenum target, gl_format mesaFormat, GLuint baseLevel, GLuint numLevels, 191 GLuint width0, GLuint height0, GLuint depth0, GLuint tilebits) 192{ 193 radeon_mipmap_tree *mt = CALLOC_STRUCT(_radeon_mipmap_tree); 194 195 mt->mesaFormat = mesaFormat; 196 mt->refcount = 1; 197 mt->target = target; 198 mt->faces = (target == GL_TEXTURE_CUBE_MAP) ? 6 : 1; 199 mt->baseLevel = baseLevel; 200 mt->numLevels = numLevels; 201 mt->width0 = width0; 202 mt->height0 = height0; 203 mt->depth0 = depth0; 204 mt->tilebits = tilebits; 205 206 if (rmesa->radeonScreen->chip_family >= CHIP_FAMILY_R300) 207 calculate_miptree_layout_r300(rmesa, mt); 208 else 209 calculate_miptree_layout_r100(rmesa, mt); 210 211 mt->bo = radeon_bo_open(rmesa->radeonScreen->bom, 212 0, mt->totalsize, 1024, 213 RADEON_GEM_DOMAIN_VRAM, 214 0); 215 216 return mt; 217} 218 219void radeon_miptree_reference(radeon_mipmap_tree *mt, radeon_mipmap_tree **ptr) 220{ 221 assert(!*ptr); 222 223 mt->refcount++; 224 assert(mt->refcount > 0); 225 226 *ptr = mt; 227} 228 229void radeon_miptree_unreference(radeon_mipmap_tree **ptr) 230{ 231 radeon_mipmap_tree *mt = *ptr; 232 if (!mt) 233 return; 234 235 assert(mt->refcount > 0); 236 237 mt->refcount--; 238 if (!mt->refcount) { 239 radeon_bo_unref(mt->bo); 240 free(mt); 241 } 242 243 *ptr = 0; 244} 245 246/** 247 * Calculate min and max LOD for the given texture object. 248 * @param[in] tObj texture object whose LOD values to calculate 249 * @param[out] pminLod minimal LOD 250 * @param[out] pmaxLod maximal LOD 251 */ 252static void calculate_min_max_lod(struct gl_texture_object *tObj, 253 unsigned *pminLod, unsigned *pmaxLod) 254{ 255 int minLod, maxLod; 256 /* Yes, this looks overly complicated, but it's all needed. 257 */ 258 switch (tObj->Target) { 259 case GL_TEXTURE_1D: 260 case GL_TEXTURE_2D: 261 case GL_TEXTURE_3D: 262 case GL_TEXTURE_CUBE_MAP: 263 if (tObj->MinFilter == GL_NEAREST || tObj->MinFilter == GL_LINEAR) { 264 /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL. 265 */ 266 minLod = maxLod = tObj->BaseLevel; 267 } else { 268 minLod = tObj->BaseLevel + (GLint)(tObj->MinLod); 269 minLod = MAX2(minLod, tObj->BaseLevel); 270 minLod = MIN2(minLod, tObj->MaxLevel); 271 maxLod = tObj->BaseLevel + (GLint)(tObj->MaxLod + 0.5); 272 maxLod = MIN2(maxLod, tObj->MaxLevel); 273 maxLod = MIN2(maxLod, tObj->Image[0][minLod]->MaxLog2 + minLod); 274 maxLod = MAX2(maxLod, minLod); /* need at least one level */ 275 } 276 break; 277 case GL_TEXTURE_RECTANGLE_NV: 278 case GL_TEXTURE_4D_SGIS: 279 minLod = maxLod = 0; 280 break; 281 default: 282 return; 283 } 284 285 /* save these values */ 286 *pminLod = minLod; 287 *pmaxLod = maxLod; 288} 289 290/** 291 * Checks whether the given miptree can hold the given texture image at the 292 * given face and level. 293 */ 294GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt, 295 struct gl_texture_image *texImage, GLuint face, GLuint level) 296{ 297 radeon_mipmap_level *lvl; 298 299 if (face >= mt->faces) 300 return GL_FALSE; 301 302 if (texImage->TexFormat != mt->mesaFormat) 303 return GL_FALSE; 304 305 lvl = &mt->levels[level]; 306 if (!lvl->valid || 307 lvl->width != texImage->Width || 308 lvl->height != texImage->Height || 309 lvl->depth != texImage->Depth) 310 return GL_FALSE; 311 312 return GL_TRUE; 313} 314 315/** 316 * Checks whether the given miptree has the right format to store the given texture object. 317 */ 318static GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_texture_object *texObj) 319{ 320 struct gl_texture_image *firstImage; 321 unsigned numLevels; 322 radeon_mipmap_level *mtBaseLevel; 323 324 if (texObj->BaseLevel < mt->baseLevel) 325 return GL_FALSE; 326 327 mtBaseLevel = &mt->levels[texObj->BaseLevel - mt->baseLevel]; 328 firstImage = texObj->Image[0][texObj->BaseLevel]; 329 numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, firstImage->MaxLog2 + 1); 330 331 if (RADEON_DEBUG & RADEON_TEXTURE) { 332 fprintf(stderr, "Checking if miptree %p matches texObj %p\n", mt, texObj); 333 fprintf(stderr, "target %d vs %d\n", mt->target, texObj->Target); 334 fprintf(stderr, "format %d vs %d\n", mt->mesaFormat, firstImage->TexFormat); 335 fprintf(stderr, "numLevels %d vs %d\n", mt->numLevels, numLevels); 336 fprintf(stderr, "width0 %d vs %d\n", mtBaseLevel->width, firstImage->Width); 337 fprintf(stderr, "height0 %d vs %d\n", mtBaseLevel->height, firstImage->Height); 338 fprintf(stderr, "depth0 %d vs %d\n", mtBaseLevel->depth, firstImage->Depth); 339 if (mt->target == texObj->Target && 340 mt->mesaFormat == firstImage->TexFormat && 341 mt->numLevels >= numLevels && 342 mtBaseLevel->width == firstImage->Width && 343 mtBaseLevel->height == firstImage->Height && 344 mtBaseLevel->depth == firstImage->Depth) { 345 fprintf(stderr, "MATCHED\n"); 346 } else { 347 fprintf(stderr, "NOT MATCHED\n"); 348 } 349 } 350 351 return (mt->target == texObj->Target && 352 mt->mesaFormat == firstImage->TexFormat && 353 mt->numLevels >= numLevels && 354 mtBaseLevel->width == firstImage->Width && 355 mtBaseLevel->height == firstImage->Height && 356 mtBaseLevel->depth == firstImage->Depth); 357} 358 359/** 360 * Try to allocate a mipmap tree for the given texture object. 361 * @param[in] rmesa radeon context 362 * @param[in] t radeon texture object 363 */ 364void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t) 365{ 366 struct gl_texture_object *texObj = &t->base; 367 struct gl_texture_image *texImg = texObj->Image[0][texObj->BaseLevel]; 368 GLuint numLevels; 369 370 assert(!t->mt); 371 372 if (!texImg) 373 return; 374 375 numLevels = MIN2(texObj->MaxLevel - texObj->BaseLevel + 1, texImg->MaxLog2 + 1); 376 377 t->mt = radeon_miptree_create(rmesa, t->base.Target, 378 texImg->TexFormat, texObj->BaseLevel, 379 numLevels, texImg->Width, texImg->Height, 380 texImg->Depth, t->tile_bits); 381} 382 383/* Although we use the image_offset[] array to store relative offsets 384 * to cube faces, Mesa doesn't know anything about this and expects 385 * each cube face to be treated as a separate image. 386 * 387 * These functions present that view to mesa: 388 */ 389void 390radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets) 391{ 392 if (mt->target != GL_TEXTURE_3D || mt->faces == 1) { 393 offsets[0] = 0; 394 } else { 395 int i; 396 for (i = 0; i < 6; i++) { 397 offsets[i] = mt->levels[level].faces[i].offset; 398 } 399 } 400} 401 402GLuint 403radeon_miptree_image_offset(radeon_mipmap_tree *mt, 404 GLuint face, GLuint level) 405{ 406 if (mt->target == GL_TEXTURE_CUBE_MAP_ARB) 407 return (mt->levels[level].faces[face].offset); 408 else 409 return mt->levels[level].faces[0].offset; 410} 411 412/** 413 * Ensure that the given image is stored in the given miptree from now on. 414 */ 415static void migrate_image_to_miptree(radeon_mipmap_tree *mt, 416 radeon_texture_image *image, 417 int face, int level) 418{ 419 radeon_mipmap_level *dstlvl = &mt->levels[level]; 420 unsigned char *dest; 421 422 assert(image->mt != mt); 423 assert(dstlvl->valid); 424 assert(dstlvl->width == image->base.Width); 425 assert(dstlvl->height == image->base.Height); 426 assert(dstlvl->depth == image->base.Depth); 427 428 radeon_bo_map(mt->bo, GL_TRUE); 429 dest = mt->bo->ptr + dstlvl->faces[face].offset; 430 431 if (image->mt) { 432 /* Format etc. should match, so we really just need a memcpy(). 433 * In fact, that memcpy() could be done by the hardware in many 434 * cases, provided that we have a proper memory manager. 435 */ 436 assert(mt->mesaFormat == image->base.TexFormat); 437 438 radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel]; 439 440 /* TODO: bring back these assertions once the FBOs are fixed */ 441#if 0 442 assert(image->mtlevel == level); 443 assert(srclvl->size == dstlvl->size); 444 assert(srclvl->rowstride == dstlvl->rowstride); 445#endif 446 447 radeon_bo_map(image->mt->bo, GL_FALSE); 448 449 memcpy(dest, 450 image->mt->bo->ptr + srclvl->faces[face].offset, 451 dstlvl->size); 452 radeon_bo_unmap(image->mt->bo); 453 454 radeon_miptree_unreference(&image->mt); 455 } else { 456 const uint32_t srcrowstride = _mesa_format_row_stride(image->base.TexFormat, image->base.Width); 457 uint32_t rows = image->base.Height * image->base.Depth; 458 459 if (_mesa_is_format_compressed(image->base.TexFormat)) { 460 uint32_t blockWidth, blockHeight; 461 _mesa_get_format_block_size(image->base.TexFormat, &blockWidth, &blockHeight); 462 rows = (rows + blockHeight - 1) / blockHeight; 463 } 464 465 copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride, 466 rows, srcrowstride); 467 468 _mesa_free_texmemory(image->base.Data); 469 image->base.Data = 0; 470 } 471 472 radeon_bo_unmap(mt->bo); 473 474 radeon_miptree_reference(mt, &image->mt); 475 image->mtface = face; 476 image->mtlevel = level; 477} 478 479/** 480 * Filter matching miptrees, and select one with the most of data. 481 * @param[in] texObj radeon texture object 482 * @param[in] firstLevel first texture level to check 483 * @param[in] lastLevel last texture level to check 484 */ 485static radeon_mipmap_tree * get_biggest_matching_miptree(radeonTexObj *texObj, 486 unsigned firstLevel, 487 unsigned lastLevel) 488{ 489 const unsigned numLevels = lastLevel - firstLevel + 1; 490 unsigned *mtSizes = calloc(numLevels, sizeof(unsigned)); 491 radeon_mipmap_tree **mts = calloc(numLevels, sizeof(radeon_mipmap_tree *)); 492 unsigned mtCount = 0; 493 unsigned maxMtIndex = 0; 494 radeon_mipmap_tree *tmp; 495 496 for (unsigned level = firstLevel; level <= lastLevel; ++level) { 497 radeon_texture_image *img = get_radeon_texture_image(texObj->base.Image[0][level]); 498 unsigned found = 0; 499 // TODO: why this hack?? 500 if (!img) 501 break; 502 503 if (!img->mt) 504 continue; 505 506 for (int i = 0; i < mtCount; ++i) { 507 if (mts[i] == img->mt) { 508 found = 1; 509 mtSizes[i] += img->mt->levels[img->mtlevel].size; 510 break; 511 } 512 } 513 514 if (!found && radeon_miptree_matches_texture(img->mt, &texObj->base)) { 515 mtSizes[mtCount] = img->mt->levels[img->mtlevel].size; 516 mts[mtCount] = img->mt; 517 mtCount++; 518 } 519 } 520 521 if (mtCount == 0) { 522 return NULL; 523 } 524 525 for (int i = 1; i < mtCount; ++i) { 526 if (mtSizes[i] > mtSizes[maxMtIndex]) { 527 maxMtIndex = i; 528 } 529 } 530 531 tmp = mts[maxMtIndex]; 532 free(mtSizes); 533 free(mts); 534 535 return tmp; 536} 537 538/** 539 * Validate texture mipmap tree. 540 * If individual images are stored in different mipmap trees 541 * use the mipmap tree that has the most of the correct data. 542 */ 543int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj) 544{ 545 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 546 radeonTexObj *t = radeon_tex_obj(texObj); 547 548 if (t->validated || t->image_override) { 549 return GL_TRUE; 550 } 551 552 if (texObj->Image[0][texObj->BaseLevel]->Border > 0) 553 return GL_FALSE; 554 555 _mesa_test_texobj_completeness(rmesa->glCtx, texObj); 556 if (!texObj->_Complete) { 557 return GL_FALSE; 558 } 559 560 calculate_min_max_lod(&t->base, &t->minLod, &t->maxLod); 561 562 if (RADEON_DEBUG & RADEON_TEXTURE) 563 fprintf(stderr, "%s: Validating texture %p now, minLod = %d, maxLod = %d\n", 564 __FUNCTION__, texObj ,t->minLod, t->maxLod); 565 566 radeon_mipmap_tree *dst_miptree; 567 dst_miptree = get_biggest_matching_miptree(t, t->minLod, t->maxLod); 568 569 if (!dst_miptree) { 570 radeon_miptree_unreference(&t->mt); 571 radeon_try_alloc_miptree(rmesa, t); 572 dst_miptree = t->mt; 573 if (RADEON_DEBUG & RADEON_TEXTURE) { 574 fprintf(stderr, "%s: No matching miptree found, allocated new one %p\n", __FUNCTION__, t->mt); 575 } 576 } else if (RADEON_DEBUG & RADEON_TEXTURE) { 577 fprintf(stderr, "%s: Using miptree %p\n", __FUNCTION__, t->mt); 578 } 579 580 const unsigned faces = texObj->Target == GL_TEXTURE_CUBE_MAP ? 6 : 1; 581 unsigned face, level; 582 radeon_texture_image *img; 583 /* Validate only the levels that will actually be used during rendering */ 584 for (face = 0; face < faces; ++face) { 585 for (level = t->minLod; level <= t->maxLod; ++level) { 586 img = get_radeon_texture_image(texObj->Image[face][level]); 587 588 if (RADEON_DEBUG & RADEON_TEXTURE) { 589 fprintf(stderr, "Checking image level %d, face %d, mt %p ... ", level, face, img->mt); 590 } 591 592 if (img->mt != dst_miptree) { 593 if (RADEON_DEBUG & RADEON_TEXTURE) { 594 fprintf(stderr, "MIGRATING\n"); 595 } 596 struct radeon_bo *src_bo = (img->mt) ? img->mt->bo : img->bo; 597 if (src_bo && radeon_bo_is_referenced_by_cs(src_bo, rmesa->cmdbuf.cs)) { 598 radeon_firevertices(rmesa); 599 } 600 migrate_image_to_miptree(dst_miptree, img, face, level); 601 } else if (RADEON_DEBUG & RADEON_TEXTURE) { 602 fprintf(stderr, "OK\n"); 603 } 604 } 605 } 606 607 t->validated = GL_TRUE; 608 609 return GL_TRUE; 610} 611 612uint32_t get_base_teximage_offset(radeonTexObj *texObj) 613{ 614 if (!texObj->mt) { 615 return 0; 616 } else { 617 return radeon_miptree_image_offset(texObj->mt, 0, texObj->minLod); 618 } 619}