common_x86.c revision 0a79baf1bff93718e50a3ba4bad6390ea1cfb01c
1/* $Id: common_x86.c,v 1.17 2002/04/09 14:58:03 keithw Exp $ */ 2 3/* 4 * Mesa 3-D graphics library 5 * Version: 3.5 6 * 7 * Copyright (C) 1999-2001 Brian Paul All Rights Reserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included 17 * in all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 23 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 24 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 */ 26 27/* 28 * Check CPU capabilities & initialize optimized funtions for this particular 29 * processor. 30 * 31 * Written by Holger Waechtler <holger@akaflieg.extern.tu-berlin.de> 32 * Changed by Andre Werthmann <wertmann@cs.uni-potsdam.de> for using the 33 * new Katmai functions. 34 */ 35 36#include <stdlib.h> 37#include <stdio.h> 38#if defined(USE_SSE_ASM) && defined(__linux__) 39#include <signal.h> 40#endif 41 42#include "context.h" 43#include "common_x86_asm.h" 44 45 46int _mesa_x86_cpu_features = 0; 47 48/* No reason for this to be public. 49 */ 50extern int _mesa_identify_x86_cpu_features( void ); 51 52 53static void message( const char *msg ) 54{ 55 GLboolean debug; 56#ifdef DEBUG 57 debug = GL_TRUE; 58#else 59 if ( getenv( "MESA_DEBUG" ) ) { 60 debug = GL_TRUE; 61 } else { 62 debug = GL_FALSE; 63 } 64#endif 65 if ( debug ) { 66 fprintf( stderr, "%s", msg ); 67 } 68} 69 70#if defined(USE_SSE_ASM) 71/* 72 * We must verify that the Streaming SIMD Extensions are truly supported 73 * on this processor before we go ahead and hook out the optimized code. 74 * Unfortunately, the CPUID bit isn't enough, as the OS must set the 75 * OSFXSR bit in CR4 if it supports the extended FPU save and restore 76 * required to use SSE. Unfortunately, we can't just go ahead and read 77 * this register, as only the kernel can do that. Similarly, we must 78 * verify that the OSXMMEXCPT bit in CR4 has been set by the OS, 79 * signifying that it supports unmasked SIMD FPU exceptions. If we take 80 * an unmasked exception and the OS doesn't correctly support them, the 81 * best we'll get is a SIGILL and the worst we'll get is an infinite 82 * loop in the signal delivery from the kernel as we can't interact with 83 * the SIMD FPU state to clear the exception bits. Either way, this is 84 * not good. 85 */ 86 87extern void _mesa_test_os_sse_support( void ); 88extern void _mesa_test_os_sse_exception_support( void ); 89 90#if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) 91static void sigill_handler( int signal, struct sigcontext sc ) 92{ 93 message( "SIGILL, " ); 94 95 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" 96 * instructions are 3 bytes long. We must increment the instruction 97 * pointer manually to avoid repeated execution of the offending 98 * instruction. 99 * 100 * If the SIGILL is caused by a divide-by-zero when unmasked 101 * exceptions aren't supported, the SIMD FPU status and control 102 * word will be restored at the end of the test, so we don't need 103 * to worry about doing it here. Besides, we may not be able to... 104 */ 105 sc.eip += 3; 106 107 _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM); 108} 109 110static void sigfpe_handler( int signal, struct sigcontext sc ) 111{ 112 message( "SIGFPE, " ); 113 114 if ( sc.fpstate->magic != 0xffff ) { 115 /* Our signal context has the extended FPU state, so reset the 116 * divide-by-zero exception mask and clear the divide-by-zero 117 * exception bit. 118 */ 119 sc.fpstate->mxcsr |= 0x00000200; 120 sc.fpstate->mxcsr &= 0xfffffffb; 121 } else { 122 /* If we ever get here, we're completely hosed. 123 */ 124 message( "\n\n" ); 125 _mesa_problem( NULL, "SSE enabling test failed badly!" ); 126 } 127} 128#endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ 129 130/* If we're running on a processor that can do SSE, let's see if we 131 * are allowed to or not. This will catch 2.4.0 or later kernels that 132 * haven't been configured for a Pentium III but are running on one, 133 * and RedHat patched 2.2 kernels that have broken exception handling 134 * support for user space apps that do SSE. 135 * 136 * GH: Isn't this just awful? 137 */ 138static void check_os_sse_support( void ) 139{ 140#if defined(__linux__) 141#if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) 142 struct sigaction saved_sigill; 143 struct sigaction saved_sigfpe; 144 145 /* Save the original signal handlers. 146 */ 147 sigaction( SIGILL, NULL, &saved_sigill ); 148 sigaction( SIGFPE, NULL, &saved_sigfpe ); 149 150 signal( SIGILL, (void (*)(int))sigill_handler ); 151 signal( SIGFPE, (void (*)(int))sigfpe_handler ); 152 153 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it 154 * supports the extended FPU save and restore required for SSE. If 155 * we execute an SSE instruction on a PIII and get a SIGILL, the OS 156 * doesn't support Streaming SIMD Exceptions, even if the processor 157 * does. 158 */ 159 if ( cpu_has_xmm ) { 160 message( "Testing OS support for SSE... " ); 161 162 _mesa_test_os_sse_support(); 163 164 if ( cpu_has_xmm ) { 165 message( "yes.\n" ); 166 } else { 167 message( "no!\n" ); 168 } 169 } 170 171 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if 172 * it supports unmasked SIMD FPU exceptions. If we unmask the 173 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS 174 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE 175 * as expected, we're okay but we need to clean up after it. 176 * 177 * Are we being too stringent in our requirement that the OS support 178 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by 179 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 180 * doesn't even support them. We at least know the user-space SSE 181 * support is good in kernels that do support unmasked exceptions, 182 * and therefore to be safe I'm going to leave this test in here. 183 */ 184 if ( cpu_has_xmm ) { 185 message( "Testing OS support for SSE unmasked exceptions... " ); 186 187 _mesa_test_os_sse_exception_support(); 188 189 if ( cpu_has_xmm ) { 190 message( "yes.\n" ); 191 } else { 192 message( "no!\n" ); 193 } 194 } 195 196 /* Restore the original signal handlers. 197 */ 198 sigaction( SIGILL, &saved_sigill, NULL ); 199 sigaction( SIGFPE, &saved_sigfpe, NULL ); 200 201 /* If we've gotten to here and the XMM CPUID bit is still set, we're 202 * safe to go ahead and hook out the SSE code throughout Mesa. 203 */ 204 if ( cpu_has_xmm ) { 205 message( "Tests of OS support for SSE passed.\n" ); 206 } else { 207 message( "Tests of OS support for SSE failed!\n" ); 208 } 209#else 210 /* We can't use POSIX signal handling to test the availability of 211 * SSE, so we disable it by default. 212 */ 213 message( "Cannot test OS support for SSE, disabling to be safe.\n" ); 214 _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM); 215#endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ 216#else 217 /* Do nothing on non-Linux platforms for now. 218 */ 219 message( "Not testing OS support for SSE, leaving enabled.\n" ); 220#endif /* __linux__ */ 221} 222 223#endif /* USE_SSE_ASM */ 224 225 226void _mesa_init_all_x86_transform_asm( void ) 227{ 228#ifdef USE_X86_ASM 229 _mesa_x86_cpu_features = _mesa_identify_x86_cpu_features(); 230 231 if ( getenv( "MESA_NO_ASM" ) ) { 232 _mesa_x86_cpu_features = 0; 233 } 234 235 if ( _mesa_x86_cpu_features ) { 236 _mesa_init_x86_transform_asm(); 237 } 238 239#ifdef USE_MMX_ASM 240 if ( cpu_has_mmx ) { 241 if ( getenv( "MESA_NO_MMX" ) == 0 ) { 242 message( "MMX cpu detected.\n" ); 243 } else { 244 _mesa_x86_cpu_features &= ~(X86_FEATURE_MMX); 245 } 246 } 247#endif 248 249#ifdef USE_3DNOW_ASM 250 if ( cpu_has_3dnow ) { 251 if ( getenv( "MESA_NO_3DNOW" ) == 0 ) { 252 message( "3DNow! cpu detected.\n" ); 253 _mesa_init_3dnow_transform_asm(); 254 } else { 255 _mesa_x86_cpu_features &= ~(X86_FEATURE_3DNOW); 256 } 257 } 258#endif 259 260#ifdef USE_SSE_ASM 261 if ( cpu_has_xmm && getenv( "MESA_FORCE_SSE" ) == 0 ) { 262 check_os_sse_support(); 263 } 264 if ( cpu_has_xmm ) { 265 if ( getenv( "MESA_NO_SSE" ) == 0 ) { 266 message( "SSE cpu detected.\n" ); 267 _mesa_init_sse_transform_asm(); 268 } else { 269 _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM); 270 } 271 } 272#endif 273#endif 274} 275 276