common_x86.c revision 81f67fc4e9621f08f46c8219f5ab5dc5c329b146
1/* 2 * Mesa 3-D graphics library 3 * Version: 6.0.1 4 * 5 * Copyright (C) 1999-2004 Brian Paul All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included 15 * in all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 21 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25/** 26 * \file common_x86.c 27 * 28 * Check CPU capabilities & initialize optimized funtions for this particular 29 * processor. 30 * 31 * Changed by Andre Werthmann for using the new SSE functions. 32 * 33 * \author Holger Waechtler <holger@akaflieg.extern.tu-berlin.de> 34 * \author Andre Werthmann <wertmann@cs.uni-potsdam.de> 35 */ 36 37/* XXX these includes should probably go into imports.h or glheader.h */ 38#if defined(USE_SSE_ASM) && defined(__linux__) 39#include <signal.h> 40#endif 41#if defined(USE_SSE_ASM) && defined(__FreeBSD__) 42#include <sys/types.h> 43#include <sys/sysctl.h> 44#endif 45 46#include "common_x86_asm.h" 47#include "imports.h" 48 49 50int _mesa_x86_cpu_features = 0; 51 52/* No reason for this to be public. 53 */ 54extern GLuint _ASMAPI _mesa_x86_has_cpuid(void); 55extern void _ASMAPI _mesa_x86_cpuid(GLuint op, GLuint *reg_eax, GLuint *reg_ebx, GLuint *reg_ecx, GLuint *reg_edx); 56extern GLuint _ASMAPI _mesa_x86_cpuid_eax(GLuint op); 57extern GLuint _ASMAPI _mesa_x86_cpuid_ebx(GLuint op); 58extern GLuint _ASMAPI _mesa_x86_cpuid_ecx(GLuint op); 59extern GLuint _ASMAPI _mesa_x86_cpuid_edx(GLuint op); 60 61static void message( const char *msg ) 62{ 63 GLboolean debug; 64#ifdef DEBUG 65 debug = GL_TRUE; 66#else 67 if ( _mesa_getenv( "MESA_DEBUG" ) ) { 68 debug = GL_TRUE; 69 } else { 70 debug = GL_FALSE; 71 } 72#endif 73 if ( debug ) { 74 fprintf( stderr, "%s", msg ); 75 } 76} 77 78#if defined(USE_SSE_ASM) 79/* 80 * We must verify that the Streaming SIMD Extensions are truly supported 81 * on this processor before we go ahead and hook out the optimized code. 82 * Unfortunately, the CPUID bit isn't enough, as the OS must set the 83 * OSFXSR bit in CR4 if it supports the extended FPU save and restore 84 * required to use SSE. Unfortunately, we can't just go ahead and read 85 * this register, as only the kernel can do that. Similarly, we must 86 * verify that the OSXMMEXCPT bit in CR4 has been set by the OS, 87 * signifying that it supports unmasked SIMD FPU exceptions. If we take 88 * an unmasked exception and the OS doesn't correctly support them, the 89 * best we'll get is a SIGILL and the worst we'll get is an infinite 90 * loop in the signal delivery from the kernel as we can't interact with 91 * the SIMD FPU state to clear the exception bits. Either way, this is 92 * not good. 93 * 94 * However, I have been told by Alan Cox that all 2.4 (and later) Linux 95 * kernels provide full SSE support on all processors that expose SSE via 96 * the CPUID mechanism. It just so happens that this is the exact set of 97 * kernels supported DRI. Therefore, when building for DRI the funky SSE 98 * exception test is omitted. 99 */ 100 101extern void _mesa_test_os_sse_support( void ); 102extern void _mesa_test_os_sse_exception_support( void ); 103 104#if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) \ 105 && !defined(DRI_NEW_INTERFACE_ONLY) 106static void sigill_handler( int signal, struct sigcontext sc ) 107{ 108 message( "SIGILL, " ); 109 110 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" 111 * instructions are 3 bytes long. We must increment the instruction 112 * pointer manually to avoid repeated execution of the offending 113 * instruction. 114 * 115 * If the SIGILL is caused by a divide-by-zero when unmasked 116 * exceptions aren't supported, the SIMD FPU status and control 117 * word will be restored at the end of the test, so we don't need 118 * to worry about doing it here. Besides, we may not be able to... 119 */ 120 sc.eip += 3; 121 122 _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM); 123} 124 125static void sigfpe_handler( int signal, struct sigcontext sc ) 126{ 127 message( "SIGFPE, " ); 128 129 if ( sc.fpstate->magic != 0xffff ) { 130 /* Our signal context has the extended FPU state, so reset the 131 * divide-by-zero exception mask and clear the divide-by-zero 132 * exception bit. 133 */ 134 sc.fpstate->mxcsr |= 0x00000200; 135 sc.fpstate->mxcsr &= 0xfffffffb; 136 } else { 137 /* If we ever get here, we're completely hosed. 138 */ 139 message( "\n\n" ); 140 _mesa_problem( NULL, "SSE enabling test failed badly!" ); 141 } 142} 143#endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ 144 145/* If we're running on a processor that can do SSE, let's see if we 146 * are allowed to or not. This will catch 2.4.0 or later kernels that 147 * haven't been configured for a Pentium III but are running on one, 148 * and RedHat patched 2.2 kernels that have broken exception handling 149 * support for user space apps that do SSE. 150 * 151 * GH: Isn't this just awful? 152 */ 153static void check_os_sse_support( void ) 154{ 155#if defined(__linux__) && !defined(DRI_NEW_INTERFACE_ONLY) 156#if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) 157 struct sigaction saved_sigill; 158 struct sigaction saved_sigfpe; 159 160 /* Save the original signal handlers. 161 */ 162 sigaction( SIGILL, NULL, &saved_sigill ); 163 sigaction( SIGFPE, NULL, &saved_sigfpe ); 164 165 signal( SIGILL, (void (*)(int))sigill_handler ); 166 signal( SIGFPE, (void (*)(int))sigfpe_handler ); 167 168 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it 169 * supports the extended FPU save and restore required for SSE. If 170 * we execute an SSE instruction on a PIII and get a SIGILL, the OS 171 * doesn't support Streaming SIMD Exceptions, even if the processor 172 * does. 173 */ 174 if ( cpu_has_xmm ) { 175 message( "Testing OS support for SSE... " ); 176 177 _mesa_test_os_sse_support(); 178 179 if ( cpu_has_xmm ) { 180 message( "yes.\n" ); 181 } else { 182 message( "no!\n" ); 183 } 184 } 185 186 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if 187 * it supports unmasked SIMD FPU exceptions. If we unmask the 188 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS 189 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE 190 * as expected, we're okay but we need to clean up after it. 191 * 192 * Are we being too stringent in our requirement that the OS support 193 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by 194 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 195 * doesn't even support them. We at least know the user-space SSE 196 * support is good in kernels that do support unmasked exceptions, 197 * and therefore to be safe I'm going to leave this test in here. 198 */ 199 if ( cpu_has_xmm ) { 200 message( "Testing OS support for SSE unmasked exceptions... " ); 201 202 _mesa_test_os_sse_exception_support(); 203 204 if ( cpu_has_xmm ) { 205 message( "yes.\n" ); 206 } else { 207 message( "no!\n" ); 208 } 209 } 210 211 /* Restore the original signal handlers. 212 */ 213 sigaction( SIGILL, &saved_sigill, NULL ); 214 sigaction( SIGFPE, &saved_sigfpe, NULL ); 215 216 /* If we've gotten to here and the XMM CPUID bit is still set, we're 217 * safe to go ahead and hook out the SSE code throughout Mesa. 218 */ 219 if ( cpu_has_xmm ) { 220 message( "Tests of OS support for SSE passed.\n" ); 221 } else { 222 message( "Tests of OS support for SSE failed!\n" ); 223 } 224#else 225 /* We can't use POSIX signal handling to test the availability of 226 * SSE, so we disable it by default. 227 */ 228 message( "Cannot test OS support for SSE, disabling to be safe.\n" ); 229 _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM); 230#endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ 231#elif defined(__FreeBSD__) 232 { 233 int ret, len, enabled; 234 len = sizeof(enabled); 235 ret = sysctlbyname("hw.instruction_sse", &enabled, &len, NULL, 0); 236 if (ret || !enabled) 237 _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM); 238 } 239#else 240 /* Do nothing on other platforms for now. 241 */ 242 message( "Not testing OS support for SSE, leaving enabled.\n" ); 243#endif /* __linux__ */ 244} 245 246#endif /* USE_SSE_ASM */ 247 248 249void _mesa_init_all_x86_transform_asm( void ) 250{ 251 (void) message; /* silence warning */ 252#ifdef USE_X86_ASM 253 _mesa_x86_cpu_features = 0; 254 255 if (!_mesa_x86_has_cpuid()) { 256 message("CPUID not detected"); 257 } 258 else { 259 GLuint cpu_features; 260 GLuint cpu_ext_features; 261 GLuint cpu_ext_info; 262 char cpu_vendor[13]; 263 GLuint result; 264 265 /* get vendor name */ 266 _mesa_x86_cpuid(0, &result, (GLuint *)(cpu_vendor + 0), (GLuint *)(cpu_vendor + 8), (GLuint *)(cpu_vendor + 4)); 267 cpu_vendor[12] = '\0'; 268 269 message("cpu vendor: "); 270 message(cpu_vendor); 271 message("\n"); 272 273 /* get cpu features */ 274 cpu_features = _mesa_x86_cpuid_edx(1); 275 276 if (cpu_features & X86_CPU_FPU) 277 _mesa_x86_cpu_features |= X86_FEATURE_FPU; 278 if (cpu_features & X86_CPU_CMOV) 279 _mesa_x86_cpu_features |= X86_FEATURE_CMOV; 280 281#ifdef USE_MMX_ASM 282 if (cpu_features & X86_CPU_MMX) 283 _mesa_x86_cpu_features |= X86_FEATURE_MMX; 284#endif 285 286#ifdef USE_SSE_ASM 287 if (cpu_features & X86_CPU_XMM) 288 _mesa_x86_cpu_features |= X86_FEATURE_XMM; 289 if (cpu_features & X86_CPU_XMM2) 290 _mesa_x86_cpu_features |= X86_FEATURE_XMM2; 291#endif 292 293 /* query extended cpu features */ 294 if ((cpu_ext_info = _mesa_x86_cpuid_eax(0x80000000)) > 0x80000000) { 295 if (cpu_ext_info >= 0x80000001) { 296 297 cpu_ext_features = _mesa_x86_cpuid_edx(0x80000001); 298 299 if (cpu_features & X86_CPU_MMX) { 300 301#ifdef USE_3DNOW_ASM 302 if (cpu_ext_features & X86_CPUEXT_3DNOW) 303 _mesa_x86_cpu_features |= X86_FEATURE_3DNOW; 304 if (cpu_ext_features & X86_CPUEXT_3DNOW_EXT) 305 _mesa_x86_cpu_features |= X86_FEATURE_3DNOWEXT; 306#endif 307 308#ifdef USE_MMX_ASM 309 if (cpu_ext_features & X86_CPUEXT_MMX_EXT) 310 _mesa_x86_cpu_features |= X86_FEATURE_MMXEXT; 311#endif 312 } 313 } 314 315 /* query cpu name */ 316 if (cpu_ext_info >= 0x80000002) { 317 GLuint ofs; 318 char cpu_name[49]; 319 for (ofs = 0; ofs < 3; ofs++) 320 _mesa_x86_cpuid(0x80000002+ofs, (GLuint *)(cpu_name + (16*ofs)+0), (GLuint *)(cpu_name + (16*ofs)+4), (GLuint *)(cpu_name + (16*ofs)+8), (GLuint *)(cpu_name + (16*ofs)+12)); 321 cpu_name[48] = '\0'; /* the name should be NULL terminated, but just to be sure */ 322 323 message("cpu name: "); 324 message(cpu_name); 325 message("\n"); 326 } 327 } 328 329 } 330 331 if ( _mesa_getenv( "MESA_NO_ASM" ) ) { 332 _mesa_x86_cpu_features = 0; 333 } 334 335 if ( _mesa_x86_cpu_features ) { 336 _mesa_init_x86_transform_asm(); 337 } 338 339#ifdef USE_MMX_ASM 340 if ( cpu_has_mmx ) { 341 if ( _mesa_getenv( "MESA_NO_MMX" ) == 0 ) { 342 message( "MMX cpu detected.\n" ); 343 } else { 344 _mesa_x86_cpu_features &= ~(X86_FEATURE_MMX); 345 } 346 } 347#endif 348 349#ifdef USE_3DNOW_ASM 350 if ( cpu_has_3dnow ) { 351 if ( _mesa_getenv( "MESA_NO_3DNOW" ) == 0 ) { 352 message( "3DNow! cpu detected.\n" ); 353 _mesa_init_3dnow_transform_asm(); 354 } else { 355 _mesa_x86_cpu_features &= ~(X86_FEATURE_3DNOW); 356 } 357 } 358#endif 359 360#ifdef USE_SSE_ASM 361 if ( cpu_has_xmm && _mesa_getenv( "MESA_FORCE_SSE" ) == 0 ) { 362 check_os_sse_support(); 363 } 364 if ( cpu_has_xmm ) { 365 if (_mesa_getenv( "MESA_NO_SSE" ) == 0 ) { 366 message( "SSE cpu detected.\n" ); 367 _mesa_init_sse_transform_asm(); 368 } else { 369 message( "SSE cpu detected, but switched off by user.\n" ); 370 _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM); 371 } 372 } 373#endif 374#endif 375} 376 377