assembler-x64.h revision c7cc028aaeedbbfa11c11d0b7b243b3d9e837ed9
1// Copyright (c) 1994-2006 Sun Microsystems Inc. 2// All Rights Reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: 7// 8// - Redistributions of source code must retain the above copyright notice, 9// this list of conditions and the following disclaimer. 10// 11// - Redistribution in binary form must reproduce the above copyright 12// notice, this list of conditions and the following disclaimer in the 13// documentation and/or other materials provided with the distribution. 14// 15// - Neither the name of Sun Microsystems or the names of contributors may 16// be used to endorse or promote products derived from this software without 17// specific prior written permission. 18// 19// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 20// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 23// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 31// The original source code covered by the above license above has been 32// modified significantly by Google Inc. 33// Copyright 2012 the V8 project authors. All rights reserved. 34 35// A lightweight X64 Assembler. 36 37#ifndef V8_X64_ASSEMBLER_X64_H_ 38#define V8_X64_ASSEMBLER_X64_H_ 39 40#include "serialize.h" 41 42namespace v8 { 43namespace internal { 44 45// Utility functions 46 47// Test whether a 64-bit value is in a specific range. 48inline bool is_uint32(int64_t x) { 49 static const uint64_t kMaxUInt32 = V8_UINT64_C(0xffffffff); 50 return static_cast<uint64_t>(x) <= kMaxUInt32; 51} 52 53inline bool is_int32(int64_t x) { 54 static const int64_t kMinInt32 = -V8_INT64_C(0x80000000); 55 return is_uint32(x - kMinInt32); 56} 57 58inline bool uint_is_int32(uint64_t x) { 59 static const uint64_t kMaxInt32 = V8_UINT64_C(0x7fffffff); 60 return x <= kMaxInt32; 61} 62 63inline bool is_uint32(uint64_t x) { 64 static const uint64_t kMaxUInt32 = V8_UINT64_C(0xffffffff); 65 return x <= kMaxUInt32; 66} 67 68// CPU Registers. 69// 70// 1) We would prefer to use an enum, but enum values are assignment- 71// compatible with int, which has caused code-generation bugs. 72// 73// 2) We would prefer to use a class instead of a struct but we don't like 74// the register initialization to depend on the particular initialization 75// order (which appears to be different on OS X, Linux, and Windows for the 76// installed versions of C++ we tried). Using a struct permits C-style 77// "initialization". Also, the Register objects cannot be const as this 78// forces initialization stubs in MSVC, making us dependent on initialization 79// order. 80// 81// 3) By not using an enum, we are possibly preventing the compiler from 82// doing certain constant folds, which may significantly reduce the 83// code generated for some assembly instructions (because they boil down 84// to a few constants). If this is a problem, we could change the code 85// such that we use an enum in optimized mode, and the struct in debug 86// mode. This way we get the compile-time error checking in debug mode 87// and best performance in optimized code. 88// 89 90struct Register { 91 // The non-allocatable registers are: 92 // rsp - stack pointer 93 // rbp - frame pointer 94 // rsi - context register 95 // r10 - fixed scratch register 96 // r12 - smi constant register 97 // r13 - root register 98 static const int kNumRegisters = 16; 99 static const int kNumAllocatableRegisters = 10; 100 101 static int ToAllocationIndex(Register reg) { 102 return kAllocationIndexByRegisterCode[reg.code()]; 103 } 104 105 static Register FromAllocationIndex(int index) { 106 ASSERT(index >= 0 && index < kNumAllocatableRegisters); 107 Register result = { kRegisterCodeByAllocationIndex[index] }; 108 return result; 109 } 110 111 static const char* AllocationIndexToString(int index) { 112 ASSERT(index >= 0 && index < kNumAllocatableRegisters); 113 const char* const names[] = { 114 "rax", 115 "rbx", 116 "rdx", 117 "rcx", 118 "rdi", 119 "r8", 120 "r9", 121 "r11", 122 "r14", 123 "r15" 124 }; 125 return names[index]; 126 } 127 128 static Register from_code(int code) { 129 Register r = { code }; 130 return r; 131 } 132 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; } 133 bool is(Register reg) const { return code_ == reg.code_; } 134 // rax, rbx, rcx and rdx are byte registers, the rest are not. 135 bool is_byte_register() const { return code_ <= 3; } 136 int code() const { 137 ASSERT(is_valid()); 138 return code_; 139 } 140 int bit() const { 141 return 1 << code_; 142 } 143 144 // Return the high bit of the register code as a 0 or 1. Used often 145 // when constructing the REX prefix byte. 146 int high_bit() const { 147 return code_ >> 3; 148 } 149 // Return the 3 low bits of the register code. Used when encoding registers 150 // in modR/M, SIB, and opcode bytes. 151 int low_bits() const { 152 return code_ & 0x7; 153 } 154 155 // Unfortunately we can't make this private in a struct when initializing 156 // by assignment. 157 int code_; 158 159 private: 160 static const int kRegisterCodeByAllocationIndex[kNumAllocatableRegisters]; 161 static const int kAllocationIndexByRegisterCode[kNumRegisters]; 162}; 163 164const Register rax = { 0 }; 165const Register rcx = { 1 }; 166const Register rdx = { 2 }; 167const Register rbx = { 3 }; 168const Register rsp = { 4 }; 169const Register rbp = { 5 }; 170const Register rsi = { 6 }; 171const Register rdi = { 7 }; 172const Register r8 = { 8 }; 173const Register r9 = { 9 }; 174const Register r10 = { 10 }; 175const Register r11 = { 11 }; 176const Register r12 = { 12 }; 177const Register r13 = { 13 }; 178const Register r14 = { 14 }; 179const Register r15 = { 15 }; 180const Register no_reg = { -1 }; 181 182 183struct XMMRegister { 184 static const int kNumRegisters = 16; 185 static const int kNumAllocatableRegisters = 15; 186 187 static int ToAllocationIndex(XMMRegister reg) { 188 ASSERT(reg.code() != 0); 189 return reg.code() - 1; 190 } 191 192 static XMMRegister FromAllocationIndex(int index) { 193 ASSERT(0 <= index && index < kNumAllocatableRegisters); 194 XMMRegister result = { index + 1 }; 195 return result; 196 } 197 198 static const char* AllocationIndexToString(int index) { 199 ASSERT(index >= 0 && index < kNumAllocatableRegisters); 200 const char* const names[] = { 201 "xmm1", 202 "xmm2", 203 "xmm3", 204 "xmm4", 205 "xmm5", 206 "xmm6", 207 "xmm7", 208 "xmm8", 209 "xmm9", 210 "xmm10", 211 "xmm11", 212 "xmm12", 213 "xmm13", 214 "xmm14", 215 "xmm15" 216 }; 217 return names[index]; 218 } 219 220 static XMMRegister from_code(int code) { 221 ASSERT(code >= 0); 222 ASSERT(code < kNumRegisters); 223 XMMRegister r = { code }; 224 return r; 225 } 226 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; } 227 bool is(XMMRegister reg) const { return code_ == reg.code_; } 228 int code() const { 229 ASSERT(is_valid()); 230 return code_; 231 } 232 233 // Return the high bit of the register code as a 0 or 1. Used often 234 // when constructing the REX prefix byte. 235 int high_bit() const { 236 return code_ >> 3; 237 } 238 // Return the 3 low bits of the register code. Used when encoding registers 239 // in modR/M, SIB, and opcode bytes. 240 int low_bits() const { 241 return code_ & 0x7; 242 } 243 244 int code_; 245}; 246 247const XMMRegister xmm0 = { 0 }; 248const XMMRegister xmm1 = { 1 }; 249const XMMRegister xmm2 = { 2 }; 250const XMMRegister xmm3 = { 3 }; 251const XMMRegister xmm4 = { 4 }; 252const XMMRegister xmm5 = { 5 }; 253const XMMRegister xmm6 = { 6 }; 254const XMMRegister xmm7 = { 7 }; 255const XMMRegister xmm8 = { 8 }; 256const XMMRegister xmm9 = { 9 }; 257const XMMRegister xmm10 = { 10 }; 258const XMMRegister xmm11 = { 11 }; 259const XMMRegister xmm12 = { 12 }; 260const XMMRegister xmm13 = { 13 }; 261const XMMRegister xmm14 = { 14 }; 262const XMMRegister xmm15 = { 15 }; 263 264 265typedef XMMRegister DoubleRegister; 266 267 268enum Condition { 269 // any value < 0 is considered no_condition 270 no_condition = -1, 271 272 overflow = 0, 273 no_overflow = 1, 274 below = 2, 275 above_equal = 3, 276 equal = 4, 277 not_equal = 5, 278 below_equal = 6, 279 above = 7, 280 negative = 8, 281 positive = 9, 282 parity_even = 10, 283 parity_odd = 11, 284 less = 12, 285 greater_equal = 13, 286 less_equal = 14, 287 greater = 15, 288 289 // Fake conditions that are handled by the 290 // opcodes using them. 291 always = 16, 292 never = 17, 293 // aliases 294 carry = below, 295 not_carry = above_equal, 296 zero = equal, 297 not_zero = not_equal, 298 sign = negative, 299 not_sign = positive, 300 last_condition = greater 301}; 302 303 304// Returns the equivalent of !cc. 305// Negation of the default no_condition (-1) results in a non-default 306// no_condition value (-2). As long as tests for no_condition check 307// for condition < 0, this will work as expected. 308inline Condition NegateCondition(Condition cc) { 309 return static_cast<Condition>(cc ^ 1); 310} 311 312 313// Corresponds to transposing the operands of a comparison. 314inline Condition ReverseCondition(Condition cc) { 315 switch (cc) { 316 case below: 317 return above; 318 case above: 319 return below; 320 case above_equal: 321 return below_equal; 322 case below_equal: 323 return above_equal; 324 case less: 325 return greater; 326 case greater: 327 return less; 328 case greater_equal: 329 return less_equal; 330 case less_equal: 331 return greater_equal; 332 default: 333 return cc; 334 }; 335} 336 337 338// ----------------------------------------------------------------------------- 339// Machine instruction Immediates 340 341class Immediate BASE_EMBEDDED { 342 public: 343 explicit Immediate(int32_t value) : value_(value) {} 344 345 private: 346 int32_t value_; 347 348 friend class Assembler; 349}; 350 351 352// ----------------------------------------------------------------------------- 353// Machine instruction Operands 354 355enum ScaleFactor { 356 times_1 = 0, 357 times_2 = 1, 358 times_4 = 2, 359 times_8 = 3, 360 times_int_size = times_4, 361 times_pointer_size = times_8 362}; 363 364 365class Operand BASE_EMBEDDED { 366 public: 367 // [base + disp/r] 368 Operand(Register base, int32_t disp); 369 370 // [base + index*scale + disp/r] 371 Operand(Register base, 372 Register index, 373 ScaleFactor scale, 374 int32_t disp); 375 376 // [index*scale + disp/r] 377 Operand(Register index, 378 ScaleFactor scale, 379 int32_t disp); 380 381 // Offset from existing memory operand. 382 // Offset is added to existing displacement as 32-bit signed values and 383 // this must not overflow. 384 Operand(const Operand& base, int32_t offset); 385 386 // Checks whether either base or index register is the given register. 387 // Does not check the "reg" part of the Operand. 388 bool AddressUsesRegister(Register reg) const; 389 390 // Queries related to the size of the generated instruction. 391 // Whether the generated instruction will have a REX prefix. 392 bool requires_rex() const { return rex_ != 0; } 393 // Size of the ModR/M, SIB and displacement parts of the generated 394 // instruction. 395 int operand_size() const { return len_; } 396 397 private: 398 byte rex_; 399 byte buf_[6]; 400 // The number of bytes of buf_ in use. 401 byte len_; 402 403 // Set the ModR/M byte without an encoded 'reg' register. The 404 // register is encoded later as part of the emit_operand operation. 405 // set_modrm can be called before or after set_sib and set_disp*. 406 inline void set_modrm(int mod, Register rm); 407 408 // Set the SIB byte if one is needed. Sets the length to 2 rather than 1. 409 inline void set_sib(ScaleFactor scale, Register index, Register base); 410 411 // Adds operand displacement fields (offsets added to the memory address). 412 // Needs to be called after set_sib, not before it. 413 inline void set_disp8(int disp); 414 inline void set_disp32(int disp); 415 416 friend class Assembler; 417}; 418 419 420// CpuFeatures keeps track of which features are supported by the target CPU. 421// Supported features must be enabled by a Scope before use. 422// Example: 423// if (CpuFeatures::IsSupported(SSE3)) { 424// CpuFeatures::Scope fscope(SSE3); 425// // Generate SSE3 floating point code. 426// } else { 427// // Generate standard x87 or SSE2 floating point code. 428// } 429class CpuFeatures : public AllStatic { 430 public: 431 // Detect features of the target CPU. Set safe defaults if the serializer 432 // is enabled (snapshots must be portable). 433 static void Probe(); 434 435 // Check whether a feature is supported by the target CPU. 436 static bool IsSupported(CpuFeature f) { 437 ASSERT(initialized_); 438 if (f == SSE2 && !FLAG_enable_sse2) return false; 439 if (f == SSE3 && !FLAG_enable_sse3) return false; 440 if (f == CMOV && !FLAG_enable_cmov) return false; 441 if (f == RDTSC && !FLAG_enable_rdtsc) return false; 442 if (f == SAHF && !FLAG_enable_sahf) return false; 443 return (supported_ & (V8_UINT64_C(1) << f)) != 0; 444 } 445 446#ifdef DEBUG 447 // Check whether a feature is currently enabled. 448 static bool IsEnabled(CpuFeature f) { 449 ASSERT(initialized_); 450 Isolate* isolate = Isolate::UncheckedCurrent(); 451 if (isolate == NULL) { 452 // When no isolate is available, work as if we're running in 453 // release mode. 454 return IsSupported(f); 455 } 456 uint64_t enabled = isolate->enabled_cpu_features(); 457 return (enabled & (V8_UINT64_C(1) << f)) != 0; 458 } 459#endif 460 461 // Enable a specified feature within a scope. 462 class Scope BASE_EMBEDDED { 463#ifdef DEBUG 464 465 public: 466 explicit Scope(CpuFeature f) { 467 uint64_t mask = V8_UINT64_C(1) << f; 468 ASSERT(CpuFeatures::IsSupported(f)); 469 ASSERT(!Serializer::enabled() || 470 (CpuFeatures::found_by_runtime_probing_ & mask) == 0); 471 isolate_ = Isolate::UncheckedCurrent(); 472 old_enabled_ = 0; 473 if (isolate_ != NULL) { 474 old_enabled_ = isolate_->enabled_cpu_features(); 475 isolate_->set_enabled_cpu_features(old_enabled_ | mask); 476 } 477 } 478 ~Scope() { 479 ASSERT_EQ(Isolate::UncheckedCurrent(), isolate_); 480 if (isolate_ != NULL) { 481 isolate_->set_enabled_cpu_features(old_enabled_); 482 } 483 } 484 485 private: 486 Isolate* isolate_; 487 uint64_t old_enabled_; 488#else 489 490 public: 491 explicit Scope(CpuFeature f) {} 492#endif 493 }; 494 495 private: 496 // Safe defaults include SSE2 and CMOV for X64. It is always available, if 497 // anyone checks, but they shouldn't need to check. 498 // The required user mode extensions in X64 are (from AMD64 ABI Table A.1): 499 // fpu, tsc, cx8, cmov, mmx, sse, sse2, fxsr, syscall 500 static const uint64_t kDefaultCpuFeatures = (1 << SSE2 | 1 << CMOV); 501 502#ifdef DEBUG 503 static bool initialized_; 504#endif 505 static uint64_t supported_; 506 static uint64_t found_by_runtime_probing_; 507 508 DISALLOW_COPY_AND_ASSIGN(CpuFeatures); 509}; 510 511 512class Assembler : public AssemblerBase { 513 private: 514 // We check before assembling an instruction that there is sufficient 515 // space to write an instruction and its relocation information. 516 // The relocation writer's position must be kGap bytes above the end of 517 // the generated instructions. This leaves enough space for the 518 // longest possible x64 instruction, 15 bytes, and the longest possible 519 // relocation information encoding, RelocInfoWriter::kMaxLength == 16. 520 // (There is a 15 byte limit on x64 instruction length that rules out some 521 // otherwise valid instructions.) 522 // This allows for a single, fast space check per instruction. 523 static const int kGap = 32; 524 525 public: 526 // Create an assembler. Instructions and relocation information are emitted 527 // into a buffer, with the instructions starting from the beginning and the 528 // relocation information starting from the end of the buffer. See CodeDesc 529 // for a detailed comment on the layout (globals.h). 530 // 531 // If the provided buffer is NULL, the assembler allocates and grows its own 532 // buffer, and buffer_size determines the initial buffer size. The buffer is 533 // owned by the assembler and deallocated upon destruction of the assembler. 534 // 535 // If the provided buffer is not NULL, the assembler uses the provided buffer 536 // for code generation and assumes its size to be buffer_size. If the buffer 537 // is too small, a fatal error occurs. No deallocation of the buffer is done 538 // upon destruction of the assembler. 539 Assembler(Isolate* isolate, void* buffer, int buffer_size); 540 ~Assembler(); 541 542 // Overrides the default provided by FLAG_debug_code. 543 void set_emit_debug_code(bool value) { emit_debug_code_ = value; } 544 545 // GetCode emits any pending (non-emitted) code and fills the descriptor 546 // desc. GetCode() is idempotent; it returns the same result if no other 547 // Assembler functions are invoked in between GetCode() calls. 548 void GetCode(CodeDesc* desc); 549 550 // Read/Modify the code target in the relative branch/call instruction at pc. 551 // On the x64 architecture, we use relative jumps with a 32-bit displacement 552 // to jump to other Code objects in the Code space in the heap. 553 // Jumps to C functions are done indirectly through a 64-bit register holding 554 // the absolute address of the target. 555 // These functions convert between absolute Addresses of Code objects and 556 // the relative displacements stored in the code. 557 static inline Address target_address_at(Address pc); 558 static inline void set_target_address_at(Address pc, Address target); 559 560 // This sets the branch destination (which is in the instruction on x64). 561 // This is for calls and branches within generated code. 562 inline static void set_target_at(Address instruction_payload, 563 Address target) { 564 set_target_address_at(instruction_payload, target); 565 } 566 567 // This sets the branch destination (which is a load instruction on x64). 568 // This is for calls and branches to runtime code. 569 inline static void set_external_target_at(Address instruction_payload, 570 Address target) { 571 *reinterpret_cast<Address*>(instruction_payload) = target; 572 } 573 574 inline Handle<Object> code_target_object_handle_at(Address pc); 575 // Number of bytes taken up by the branch target in the code. 576 static const int kCallTargetSize = 4; // Use 32-bit displacement. 577 static const int kExternalTargetSize = 8; // Use 64-bit absolute. 578 // Distance between the address of the code target in the call instruction 579 // and the return address pushed on the stack. 580 static const int kCallTargetAddressOffset = 4; // Use 32-bit displacement. 581 // Distance between the start of the JS return sequence and where the 582 // 32-bit displacement of a near call would be, relative to the pushed 583 // return address. TODO: Use return sequence length instead. 584 // Should equal Debug::kX64JSReturnSequenceLength - kCallTargetAddressOffset; 585 static const int kPatchReturnSequenceAddressOffset = 13 - 4; 586 // Distance between start of patched debug break slot and where the 587 // 32-bit displacement of a near call would be, relative to the pushed 588 // return address. TODO: Use return sequence length instead. 589 // Should equal Debug::kX64JSReturnSequenceLength - kCallTargetAddressOffset; 590 static const int kPatchDebugBreakSlotAddressOffset = 13 - 4; 591 // TODO(X64): Rename this, removing the "Real", after changing the above. 592 static const int kRealPatchReturnSequenceAddressOffset = 2; 593 594 // Some x64 JS code is padded with int3 to make it large 595 // enough to hold an instruction when the debugger patches it. 596 static const int kJumpInstructionLength = 13; 597 static const int kCallInstructionLength = 13; 598 static const int kJSReturnSequenceLength = 13; 599 static const int kShortCallInstructionLength = 5; 600 601 // The debug break slot must be able to contain a call instruction. 602 static const int kDebugBreakSlotLength = kCallInstructionLength; 603 604 // One byte opcode for test eax,0xXXXXXXXX. 605 static const byte kTestEaxByte = 0xA9; 606 // One byte opcode for test al, 0xXX. 607 static const byte kTestAlByte = 0xA8; 608 // One byte opcode for nop. 609 static const byte kNopByte = 0x90; 610 611 // One byte prefix for a short conditional jump. 612 static const byte kJccShortPrefix = 0x70; 613 static const byte kJncShortOpcode = kJccShortPrefix | not_carry; 614 static const byte kJcShortOpcode = kJccShortPrefix | carry; 615 616 617 618 // --------------------------------------------------------------------------- 619 // Code generation 620 // 621 // Function names correspond one-to-one to x64 instruction mnemonics. 622 // Unless specified otherwise, instructions operate on 64-bit operands. 623 // 624 // If we need versions of an assembly instruction that operate on different 625 // width arguments, we add a single-letter suffix specifying the width. 626 // This is done for the following instructions: mov, cmp, inc, dec, 627 // add, sub, and test. 628 // There are no versions of these instructions without the suffix. 629 // - Instructions on 8-bit (byte) operands/registers have a trailing 'b'. 630 // - Instructions on 16-bit (word) operands/registers have a trailing 'w'. 631 // - Instructions on 32-bit (doubleword) operands/registers use 'l'. 632 // - Instructions on 64-bit (quadword) operands/registers use 'q'. 633 // 634 // Some mnemonics, such as "and", are the same as C++ keywords. 635 // Naming conflicts with C++ keywords are resolved by adding a trailing '_'. 636 637 // Insert the smallest number of nop instructions 638 // possible to align the pc offset to a multiple 639 // of m, where m must be a power of 2. 640 void Align(int m); 641 void Nop(int bytes = 1); 642 // Aligns code to something that's optimal for a jump target for the platform. 643 void CodeTargetAlign(); 644 645 // Stack 646 void pushfq(); 647 void popfq(); 648 649 void push(Immediate value); 650 // Push a 32 bit integer, and guarantee that it is actually pushed as a 651 // 32 bit value, the normal push will optimize the 8 bit case. 652 void push_imm32(int32_t imm32); 653 void push(Register src); 654 void push(const Operand& src); 655 656 void pop(Register dst); 657 void pop(const Operand& dst); 658 659 void enter(Immediate size); 660 void leave(); 661 662 // Moves 663 void movb(Register dst, const Operand& src); 664 void movb(Register dst, Immediate imm); 665 void movb(const Operand& dst, Register src); 666 667 // Move the low 16 bits of a 64-bit register value to a 16-bit 668 // memory location. 669 void movw(const Operand& dst, Register src); 670 671 void movl(Register dst, Register src); 672 void movl(Register dst, const Operand& src); 673 void movl(const Operand& dst, Register src); 674 void movl(const Operand& dst, Immediate imm); 675 // Load a 32-bit immediate value, zero-extended to 64 bits. 676 void movl(Register dst, Immediate imm32); 677 678 // Move 64 bit register value to 64-bit memory location. 679 void movq(const Operand& dst, Register src); 680 // Move 64 bit memory location to 64-bit register value. 681 void movq(Register dst, const Operand& src); 682 void movq(Register dst, Register src); 683 // Sign extends immediate 32-bit value to 64 bits. 684 void movq(Register dst, Immediate x); 685 // Move the offset of the label location relative to the current 686 // position (after the move) to the destination. 687 void movl(const Operand& dst, Label* src); 688 689 // Move sign extended immediate to memory location. 690 void movq(const Operand& dst, Immediate value); 691 // Instructions to load a 64-bit immediate into a register. 692 // All 64-bit immediates must have a relocation mode. 693 void movq(Register dst, void* ptr, RelocInfo::Mode rmode); 694 void movq(Register dst, int64_t value, RelocInfo::Mode rmode); 695 void movq(Register dst, const char* s, RelocInfo::Mode rmode); 696 // Moves the address of the external reference into the register. 697 void movq(Register dst, ExternalReference ext); 698 void movq(Register dst, Handle<Object> handle, RelocInfo::Mode rmode); 699 700 void movsxbq(Register dst, const Operand& src); 701 void movsxwq(Register dst, const Operand& src); 702 void movsxlq(Register dst, Register src); 703 void movsxlq(Register dst, const Operand& src); 704 void movzxbq(Register dst, const Operand& src); 705 void movzxbl(Register dst, const Operand& src); 706 void movzxwq(Register dst, const Operand& src); 707 void movzxwl(Register dst, const Operand& src); 708 709 // Repeated moves. 710 711 void repmovsb(); 712 void repmovsw(); 713 void repmovsl(); 714 void repmovsq(); 715 716 // Instruction to load from an immediate 64-bit pointer into RAX. 717 void load_rax(void* ptr, RelocInfo::Mode rmode); 718 void load_rax(ExternalReference ext); 719 720 // Conditional moves. 721 void cmovq(Condition cc, Register dst, Register src); 722 void cmovq(Condition cc, Register dst, const Operand& src); 723 void cmovl(Condition cc, Register dst, Register src); 724 void cmovl(Condition cc, Register dst, const Operand& src); 725 726 // Exchange two registers 727 void xchg(Register dst, Register src); 728 729 // Arithmetics 730 void addl(Register dst, Register src) { 731 arithmetic_op_32(0x03, dst, src); 732 } 733 734 void addl(Register dst, Immediate src) { 735 immediate_arithmetic_op_32(0x0, dst, src); 736 } 737 738 void addl(Register dst, const Operand& src) { 739 arithmetic_op_32(0x03, dst, src); 740 } 741 742 void addl(const Operand& dst, Immediate src) { 743 immediate_arithmetic_op_32(0x0, dst, src); 744 } 745 746 void addl(const Operand& dst, Register src) { 747 arithmetic_op_32(0x01, src, dst); 748 } 749 750 void addq(Register dst, Register src) { 751 arithmetic_op(0x03, dst, src); 752 } 753 754 void addq(Register dst, const Operand& src) { 755 arithmetic_op(0x03, dst, src); 756 } 757 758 void addq(const Operand& dst, Register src) { 759 arithmetic_op(0x01, src, dst); 760 } 761 762 void addq(Register dst, Immediate src) { 763 immediate_arithmetic_op(0x0, dst, src); 764 } 765 766 void addq(const Operand& dst, Immediate src) { 767 immediate_arithmetic_op(0x0, dst, src); 768 } 769 770 void sbbl(Register dst, Register src) { 771 arithmetic_op_32(0x1b, dst, src); 772 } 773 774 void sbbq(Register dst, Register src) { 775 arithmetic_op(0x1b, dst, src); 776 } 777 778 void cmpb(Register dst, Immediate src) { 779 immediate_arithmetic_op_8(0x7, dst, src); 780 } 781 782 void cmpb_al(Immediate src); 783 784 void cmpb(Register dst, Register src) { 785 arithmetic_op(0x3A, dst, src); 786 } 787 788 void cmpb(Register dst, const Operand& src) { 789 arithmetic_op(0x3A, dst, src); 790 } 791 792 void cmpb(const Operand& dst, Register src) { 793 arithmetic_op(0x38, src, dst); 794 } 795 796 void cmpb(const Operand& dst, Immediate src) { 797 immediate_arithmetic_op_8(0x7, dst, src); 798 } 799 800 void cmpw(const Operand& dst, Immediate src) { 801 immediate_arithmetic_op_16(0x7, dst, src); 802 } 803 804 void cmpw(Register dst, Immediate src) { 805 immediate_arithmetic_op_16(0x7, dst, src); 806 } 807 808 void cmpw(Register dst, const Operand& src) { 809 arithmetic_op_16(0x3B, dst, src); 810 } 811 812 void cmpw(Register dst, Register src) { 813 arithmetic_op_16(0x3B, dst, src); 814 } 815 816 void cmpw(const Operand& dst, Register src) { 817 arithmetic_op_16(0x39, src, dst); 818 } 819 820 void cmpl(Register dst, Register src) { 821 arithmetic_op_32(0x3B, dst, src); 822 } 823 824 void cmpl(Register dst, const Operand& src) { 825 arithmetic_op_32(0x3B, dst, src); 826 } 827 828 void cmpl(const Operand& dst, Register src) { 829 arithmetic_op_32(0x39, src, dst); 830 } 831 832 void cmpl(Register dst, Immediate src) { 833 immediate_arithmetic_op_32(0x7, dst, src); 834 } 835 836 void cmpl(const Operand& dst, Immediate src) { 837 immediate_arithmetic_op_32(0x7, dst, src); 838 } 839 840 void cmpq(Register dst, Register src) { 841 arithmetic_op(0x3B, dst, src); 842 } 843 844 void cmpq(Register dst, const Operand& src) { 845 arithmetic_op(0x3B, dst, src); 846 } 847 848 void cmpq(const Operand& dst, Register src) { 849 arithmetic_op(0x39, src, dst); 850 } 851 852 void cmpq(Register dst, Immediate src) { 853 immediate_arithmetic_op(0x7, dst, src); 854 } 855 856 void cmpq(const Operand& dst, Immediate src) { 857 immediate_arithmetic_op(0x7, dst, src); 858 } 859 860 void and_(Register dst, Register src) { 861 arithmetic_op(0x23, dst, src); 862 } 863 864 void and_(Register dst, const Operand& src) { 865 arithmetic_op(0x23, dst, src); 866 } 867 868 void and_(const Operand& dst, Register src) { 869 arithmetic_op(0x21, src, dst); 870 } 871 872 void and_(Register dst, Immediate src) { 873 immediate_arithmetic_op(0x4, dst, src); 874 } 875 876 void and_(const Operand& dst, Immediate src) { 877 immediate_arithmetic_op(0x4, dst, src); 878 } 879 880 void andl(Register dst, Immediate src) { 881 immediate_arithmetic_op_32(0x4, dst, src); 882 } 883 884 void andl(Register dst, Register src) { 885 arithmetic_op_32(0x23, dst, src); 886 } 887 888 void andl(Register dst, const Operand& src) { 889 arithmetic_op_32(0x23, dst, src); 890 } 891 892 void andb(Register dst, Immediate src) { 893 immediate_arithmetic_op_8(0x4, dst, src); 894 } 895 896 void decq(Register dst); 897 void decq(const Operand& dst); 898 void decl(Register dst); 899 void decl(const Operand& dst); 900 void decb(Register dst); 901 void decb(const Operand& dst); 902 903 // Sign-extends rax into rdx:rax. 904 void cqo(); 905 // Sign-extends eax into edx:eax. 906 void cdq(); 907 908 // Divide rdx:rax by src. Quotient in rax, remainder in rdx. 909 void idivq(Register src); 910 // Divide edx:eax by lower 32 bits of src. Quotient in eax, rem. in edx. 911 void idivl(Register src); 912 913 // Signed multiply instructions. 914 void imul(Register src); // rdx:rax = rax * src. 915 void imul(Register dst, Register src); // dst = dst * src. 916 void imul(Register dst, const Operand& src); // dst = dst * src. 917 void imul(Register dst, Register src, Immediate imm); // dst = src * imm. 918 // Signed 32-bit multiply instructions. 919 void imull(Register dst, Register src); // dst = dst * src. 920 void imull(Register dst, const Operand& src); // dst = dst * src. 921 void imull(Register dst, Register src, Immediate imm); // dst = src * imm. 922 923 void incq(Register dst); 924 void incq(const Operand& dst); 925 void incl(Register dst); 926 void incl(const Operand& dst); 927 928 void lea(Register dst, const Operand& src); 929 void leal(Register dst, const Operand& src); 930 931 // Multiply rax by src, put the result in rdx:rax. 932 void mul(Register src); 933 934 void neg(Register dst); 935 void neg(const Operand& dst); 936 void negl(Register dst); 937 938 void not_(Register dst); 939 void not_(const Operand& dst); 940 void notl(Register dst); 941 942 void or_(Register dst, Register src) { 943 arithmetic_op(0x0B, dst, src); 944 } 945 946 void orl(Register dst, Register src) { 947 arithmetic_op_32(0x0B, dst, src); 948 } 949 950 void or_(Register dst, const Operand& src) { 951 arithmetic_op(0x0B, dst, src); 952 } 953 954 void orl(Register dst, const Operand& src) { 955 arithmetic_op_32(0x0B, dst, src); 956 } 957 958 void or_(const Operand& dst, Register src) { 959 arithmetic_op(0x09, src, dst); 960 } 961 962 void or_(Register dst, Immediate src) { 963 immediate_arithmetic_op(0x1, dst, src); 964 } 965 966 void orl(Register dst, Immediate src) { 967 immediate_arithmetic_op_32(0x1, dst, src); 968 } 969 970 void or_(const Operand& dst, Immediate src) { 971 immediate_arithmetic_op(0x1, dst, src); 972 } 973 974 void orl(const Operand& dst, Immediate src) { 975 immediate_arithmetic_op_32(0x1, dst, src); 976 } 977 978 979 void rcl(Register dst, Immediate imm8) { 980 shift(dst, imm8, 0x2); 981 } 982 983 void rol(Register dst, Immediate imm8) { 984 shift(dst, imm8, 0x0); 985 } 986 987 void rcr(Register dst, Immediate imm8) { 988 shift(dst, imm8, 0x3); 989 } 990 991 void ror(Register dst, Immediate imm8) { 992 shift(dst, imm8, 0x1); 993 } 994 995 // Shifts dst:src left by cl bits, affecting only dst. 996 void shld(Register dst, Register src); 997 998 // Shifts src:dst right by cl bits, affecting only dst. 999 void shrd(Register dst, Register src); 1000 1001 // Shifts dst right, duplicating sign bit, by shift_amount bits. 1002 // Shifting by 1 is handled efficiently. 1003 void sar(Register dst, Immediate shift_amount) { 1004 shift(dst, shift_amount, 0x7); 1005 } 1006 1007 // Shifts dst right, duplicating sign bit, by shift_amount bits. 1008 // Shifting by 1 is handled efficiently. 1009 void sarl(Register dst, Immediate shift_amount) { 1010 shift_32(dst, shift_amount, 0x7); 1011 } 1012 1013 // Shifts dst right, duplicating sign bit, by cl % 64 bits. 1014 void sar_cl(Register dst) { 1015 shift(dst, 0x7); 1016 } 1017 1018 // Shifts dst right, duplicating sign bit, by cl % 64 bits. 1019 void sarl_cl(Register dst) { 1020 shift_32(dst, 0x7); 1021 } 1022 1023 void shl(Register dst, Immediate shift_amount) { 1024 shift(dst, shift_amount, 0x4); 1025 } 1026 1027 void shl_cl(Register dst) { 1028 shift(dst, 0x4); 1029 } 1030 1031 void shll_cl(Register dst) { 1032 shift_32(dst, 0x4); 1033 } 1034 1035 void shll(Register dst, Immediate shift_amount) { 1036 shift_32(dst, shift_amount, 0x4); 1037 } 1038 1039 void shr(Register dst, Immediate shift_amount) { 1040 shift(dst, shift_amount, 0x5); 1041 } 1042 1043 void shr_cl(Register dst) { 1044 shift(dst, 0x5); 1045 } 1046 1047 void shrl_cl(Register dst) { 1048 shift_32(dst, 0x5); 1049 } 1050 1051 void shrl(Register dst, Immediate shift_amount) { 1052 shift_32(dst, shift_amount, 0x5); 1053 } 1054 1055 void store_rax(void* dst, RelocInfo::Mode mode); 1056 void store_rax(ExternalReference ref); 1057 1058 void subq(Register dst, Register src) { 1059 arithmetic_op(0x2B, dst, src); 1060 } 1061 1062 void subq(Register dst, const Operand& src) { 1063 arithmetic_op(0x2B, dst, src); 1064 } 1065 1066 void subq(const Operand& dst, Register src) { 1067 arithmetic_op(0x29, src, dst); 1068 } 1069 1070 void subq(Register dst, Immediate src) { 1071 immediate_arithmetic_op(0x5, dst, src); 1072 } 1073 1074 void subq(const Operand& dst, Immediate src) { 1075 immediate_arithmetic_op(0x5, dst, src); 1076 } 1077 1078 void subl(Register dst, Register src) { 1079 arithmetic_op_32(0x2B, dst, src); 1080 } 1081 1082 void subl(Register dst, const Operand& src) { 1083 arithmetic_op_32(0x2B, dst, src); 1084 } 1085 1086 void subl(const Operand& dst, Immediate src) { 1087 immediate_arithmetic_op_32(0x5, dst, src); 1088 } 1089 1090 void subl(Register dst, Immediate src) { 1091 immediate_arithmetic_op_32(0x5, dst, src); 1092 } 1093 1094 void subb(Register dst, Immediate src) { 1095 immediate_arithmetic_op_8(0x5, dst, src); 1096 } 1097 1098 void testb(Register dst, Register src); 1099 void testb(Register reg, Immediate mask); 1100 void testb(const Operand& op, Immediate mask); 1101 void testb(const Operand& op, Register reg); 1102 void testl(Register dst, Register src); 1103 void testl(Register reg, Immediate mask); 1104 void testl(const Operand& op, Immediate mask); 1105 void testq(const Operand& op, Register reg); 1106 void testq(Register dst, Register src); 1107 void testq(Register dst, Immediate mask); 1108 1109 void xor_(Register dst, Register src) { 1110 if (dst.code() == src.code()) { 1111 arithmetic_op_32(0x33, dst, src); 1112 } else { 1113 arithmetic_op(0x33, dst, src); 1114 } 1115 } 1116 1117 void xorl(Register dst, Register src) { 1118 arithmetic_op_32(0x33, dst, src); 1119 } 1120 1121 void xorl(Register dst, const Operand& src) { 1122 arithmetic_op_32(0x33, dst, src); 1123 } 1124 1125 void xorl(Register dst, Immediate src) { 1126 immediate_arithmetic_op_32(0x6, dst, src); 1127 } 1128 1129 void xorl(const Operand& dst, Immediate src) { 1130 immediate_arithmetic_op_32(0x6, dst, src); 1131 } 1132 1133 void xor_(Register dst, const Operand& src) { 1134 arithmetic_op(0x33, dst, src); 1135 } 1136 1137 void xor_(const Operand& dst, Register src) { 1138 arithmetic_op(0x31, src, dst); 1139 } 1140 1141 void xor_(Register dst, Immediate src) { 1142 immediate_arithmetic_op(0x6, dst, src); 1143 } 1144 1145 void xor_(const Operand& dst, Immediate src) { 1146 immediate_arithmetic_op(0x6, dst, src); 1147 } 1148 1149 // Bit operations. 1150 void bt(const Operand& dst, Register src); 1151 void bts(const Operand& dst, Register src); 1152 1153 // Miscellaneous 1154 void clc(); 1155 void cld(); 1156 void cpuid(); 1157 void hlt(); 1158 void int3(); 1159 void nop(); 1160 void rdtsc(); 1161 void ret(int imm16); 1162 void setcc(Condition cc, Register reg); 1163 1164 // Label operations & relative jumps (PPUM Appendix D) 1165 // 1166 // Takes a branch opcode (cc) and a label (L) and generates 1167 // either a backward branch or a forward branch and links it 1168 // to the label fixup chain. Usage: 1169 // 1170 // Label L; // unbound label 1171 // j(cc, &L); // forward branch to unbound label 1172 // bind(&L); // bind label to the current pc 1173 // j(cc, &L); // backward branch to bound label 1174 // bind(&L); // illegal: a label may be bound only once 1175 // 1176 // Note: The same Label can be used for forward and backward branches 1177 // but it may be bound only once. 1178 1179 void bind(Label* L); // binds an unbound label L to the current code position 1180 1181 // Calls 1182 // Call near relative 32-bit displacement, relative to next instruction. 1183 void call(Label* L); 1184 void call(Handle<Code> target, 1185 RelocInfo::Mode rmode = RelocInfo::CODE_TARGET, 1186 unsigned ast_id = kNoASTId); 1187 1188 // Calls directly to the given address using a relative offset. 1189 // Should only ever be used in Code objects for calls within the 1190 // same Code object. Should not be used when generating new code (use labels), 1191 // but only when patching existing code. 1192 void call(Address target); 1193 1194 // Call near absolute indirect, address in register 1195 void call(Register adr); 1196 1197 // Call near indirect 1198 void call(const Operand& operand); 1199 1200 // Jumps 1201 // Jump short or near relative. 1202 // Use a 32-bit signed displacement. 1203 // Unconditional jump to L 1204 void jmp(Label* L, Label::Distance distance = Label::kFar); 1205 void jmp(Handle<Code> target, RelocInfo::Mode rmode); 1206 1207 // Jump near absolute indirect (r64) 1208 void jmp(Register adr); 1209 1210 // Jump near absolute indirect (m64) 1211 void jmp(const Operand& src); 1212 1213 // Conditional jumps 1214 void j(Condition cc, 1215 Label* L, 1216 Label::Distance distance = Label::kFar); 1217 void j(Condition cc, Handle<Code> target, RelocInfo::Mode rmode); 1218 1219 // Floating-point operations 1220 void fld(int i); 1221 1222 void fld1(); 1223 void fldz(); 1224 void fldpi(); 1225 void fldln2(); 1226 1227 void fld_s(const Operand& adr); 1228 void fld_d(const Operand& adr); 1229 1230 void fstp_s(const Operand& adr); 1231 void fstp_d(const Operand& adr); 1232 void fstp(int index); 1233 1234 void fild_s(const Operand& adr); 1235 void fild_d(const Operand& adr); 1236 1237 void fist_s(const Operand& adr); 1238 1239 void fistp_s(const Operand& adr); 1240 void fistp_d(const Operand& adr); 1241 1242 void fisttp_s(const Operand& adr); 1243 void fisttp_d(const Operand& adr); 1244 1245 void fabs(); 1246 void fchs(); 1247 1248 void fadd(int i); 1249 void fsub(int i); 1250 void fmul(int i); 1251 void fdiv(int i); 1252 1253 void fisub_s(const Operand& adr); 1254 1255 void faddp(int i = 1); 1256 void fsubp(int i = 1); 1257 void fsubrp(int i = 1); 1258 void fmulp(int i = 1); 1259 void fdivp(int i = 1); 1260 void fprem(); 1261 void fprem1(); 1262 1263 void fxch(int i = 1); 1264 void fincstp(); 1265 void ffree(int i = 0); 1266 1267 void ftst(); 1268 void fucomp(int i); 1269 void fucompp(); 1270 void fucomi(int i); 1271 void fucomip(); 1272 1273 void fcompp(); 1274 void fnstsw_ax(); 1275 void fwait(); 1276 void fnclex(); 1277 1278 void fsin(); 1279 void fcos(); 1280 void fptan(); 1281 void fyl2x(); 1282 void f2xm1(); 1283 void fscale(); 1284 void fninit(); 1285 1286 void frndint(); 1287 1288 void sahf(); 1289 1290 // SSE2 instructions 1291 void movd(XMMRegister dst, Register src); 1292 void movd(Register dst, XMMRegister src); 1293 void movq(XMMRegister dst, Register src); 1294 void movq(Register dst, XMMRegister src); 1295 void movq(XMMRegister dst, XMMRegister src); 1296 void extractps(Register dst, XMMRegister src, byte imm8); 1297 1298 // Don't use this unless it's important to keep the 1299 // top half of the destination register unchanged. 1300 // Used movaps when moving double values and movq for integer 1301 // values in xmm registers. 1302 void movsd(XMMRegister dst, XMMRegister src); 1303 1304 void movsd(const Operand& dst, XMMRegister src); 1305 void movsd(XMMRegister dst, const Operand& src); 1306 1307 void movdqa(const Operand& dst, XMMRegister src); 1308 void movdqa(XMMRegister dst, const Operand& src); 1309 1310 void movapd(XMMRegister dst, XMMRegister src); 1311 void movaps(XMMRegister dst, XMMRegister src); 1312 1313 void movss(XMMRegister dst, const Operand& src); 1314 void movss(const Operand& dst, XMMRegister src); 1315 1316 void cvttss2si(Register dst, const Operand& src); 1317 void cvttss2si(Register dst, XMMRegister src); 1318 void cvttsd2si(Register dst, const Operand& src); 1319 void cvttsd2si(Register dst, XMMRegister src); 1320 void cvttsd2siq(Register dst, XMMRegister src); 1321 1322 void cvtlsi2sd(XMMRegister dst, const Operand& src); 1323 void cvtlsi2sd(XMMRegister dst, Register src); 1324 void cvtqsi2sd(XMMRegister dst, const Operand& src); 1325 void cvtqsi2sd(XMMRegister dst, Register src); 1326 1327 void cvtlsi2ss(XMMRegister dst, Register src); 1328 1329 void cvtss2sd(XMMRegister dst, XMMRegister src); 1330 void cvtss2sd(XMMRegister dst, const Operand& src); 1331 void cvtsd2ss(XMMRegister dst, XMMRegister src); 1332 1333 void cvtsd2si(Register dst, XMMRegister src); 1334 void cvtsd2siq(Register dst, XMMRegister src); 1335 1336 void addsd(XMMRegister dst, XMMRegister src); 1337 void subsd(XMMRegister dst, XMMRegister src); 1338 void mulsd(XMMRegister dst, XMMRegister src); 1339 void divsd(XMMRegister dst, XMMRegister src); 1340 1341 void andpd(XMMRegister dst, XMMRegister src); 1342 void orpd(XMMRegister dst, XMMRegister src); 1343 void xorpd(XMMRegister dst, XMMRegister src); 1344 void xorps(XMMRegister dst, XMMRegister src); 1345 void sqrtsd(XMMRegister dst, XMMRegister src); 1346 1347 void ucomisd(XMMRegister dst, XMMRegister src); 1348 void ucomisd(XMMRegister dst, const Operand& src); 1349 1350 enum RoundingMode { 1351 kRoundToNearest = 0x0, 1352 kRoundDown = 0x1, 1353 kRoundUp = 0x2, 1354 kRoundToZero = 0x3 1355 }; 1356 1357 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode); 1358 1359 void movmskpd(Register dst, XMMRegister src); 1360 1361 // The first argument is the reg field, the second argument is the r/m field. 1362 void emit_sse_operand(XMMRegister dst, XMMRegister src); 1363 void emit_sse_operand(XMMRegister reg, const Operand& adr); 1364 void emit_sse_operand(XMMRegister dst, Register src); 1365 void emit_sse_operand(Register dst, XMMRegister src); 1366 1367 // Debugging 1368 void Print(); 1369 1370 // Check the code size generated from label to here. 1371 int SizeOfCodeGeneratedSince(Label* label) { 1372 return pc_offset() - label->pos(); 1373 } 1374 1375 // Mark address of the ExitJSFrame code. 1376 void RecordJSReturn(); 1377 1378 // Mark address of a debug break slot. 1379 void RecordDebugBreakSlot(); 1380 1381 // Record a comment relocation entry that can be used by a disassembler. 1382 // Use --code-comments to enable. 1383 void RecordComment(const char* msg, bool force = false); 1384 1385 // Writes a single word of data in the code stream. 1386 // Used for inline tables, e.g., jump-tables. 1387 void db(uint8_t data); 1388 void dd(uint32_t data); 1389 1390 int pc_offset() const { return static_cast<int>(pc_ - buffer_); } 1391 1392 PositionsRecorder* positions_recorder() { return &positions_recorder_; } 1393 1394 // Check if there is less than kGap bytes available in the buffer. 1395 // If this is the case, we need to grow the buffer before emitting 1396 // an instruction or relocation information. 1397 inline bool buffer_overflow() const { 1398 return pc_ >= reloc_info_writer.pos() - kGap; 1399 } 1400 1401 // Get the number of bytes available in the buffer. 1402 inline int available_space() const { 1403 return static_cast<int>(reloc_info_writer.pos() - pc_); 1404 } 1405 1406 static bool IsNop(Address addr); 1407 1408 // Avoid overflows for displacements etc. 1409 static const int kMaximalBufferSize = 512*MB; 1410 static const int kMinimalBufferSize = 4*KB; 1411 1412 byte byte_at(int pos) { return buffer_[pos]; } 1413 void set_byte_at(int pos, byte value) { buffer_[pos] = value; } 1414 1415 protected: 1416 bool emit_debug_code() const { return emit_debug_code_; } 1417 1418 private: 1419 byte* addr_at(int pos) { return buffer_ + pos; } 1420 uint32_t long_at(int pos) { 1421 return *reinterpret_cast<uint32_t*>(addr_at(pos)); 1422 } 1423 void long_at_put(int pos, uint32_t x) { 1424 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x; 1425 } 1426 1427 // code emission 1428 void GrowBuffer(); 1429 1430 void emit(byte x) { *pc_++ = x; } 1431 inline void emitl(uint32_t x); 1432 inline void emitq(uint64_t x, RelocInfo::Mode rmode); 1433 inline void emitw(uint16_t x); 1434 inline void emit_code_target(Handle<Code> target, 1435 RelocInfo::Mode rmode, 1436 unsigned ast_id = kNoASTId); 1437 void emit(Immediate x) { emitl(x.value_); } 1438 1439 // Emits a REX prefix that encodes a 64-bit operand size and 1440 // the top bit of both register codes. 1441 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. 1442 // REX.W is set. 1443 inline void emit_rex_64(XMMRegister reg, Register rm_reg); 1444 inline void emit_rex_64(Register reg, XMMRegister rm_reg); 1445 inline void emit_rex_64(Register reg, Register rm_reg); 1446 1447 // Emits a REX prefix that encodes a 64-bit operand size and 1448 // the top bit of the destination, index, and base register codes. 1449 // The high bit of reg is used for REX.R, the high bit of op's base 1450 // register is used for REX.B, and the high bit of op's index register 1451 // is used for REX.X. REX.W is set. 1452 inline void emit_rex_64(Register reg, const Operand& op); 1453 inline void emit_rex_64(XMMRegister reg, const Operand& op); 1454 1455 // Emits a REX prefix that encodes a 64-bit operand size and 1456 // the top bit of the register code. 1457 // The high bit of register is used for REX.B. 1458 // REX.W is set and REX.R and REX.X are clear. 1459 inline void emit_rex_64(Register rm_reg); 1460 1461 // Emits a REX prefix that encodes a 64-bit operand size and 1462 // the top bit of the index and base register codes. 1463 // The high bit of op's base register is used for REX.B, and the high 1464 // bit of op's index register is used for REX.X. 1465 // REX.W is set and REX.R clear. 1466 inline void emit_rex_64(const Operand& op); 1467 1468 // Emit a REX prefix that only sets REX.W to choose a 64-bit operand size. 1469 void emit_rex_64() { emit(0x48); } 1470 1471 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. 1472 // REX.W is clear. 1473 inline void emit_rex_32(Register reg, Register rm_reg); 1474 1475 // The high bit of reg is used for REX.R, the high bit of op's base 1476 // register is used for REX.B, and the high bit of op's index register 1477 // is used for REX.X. REX.W is cleared. 1478 inline void emit_rex_32(Register reg, const Operand& op); 1479 1480 // High bit of rm_reg goes to REX.B. 1481 // REX.W, REX.R and REX.X are clear. 1482 inline void emit_rex_32(Register rm_reg); 1483 1484 // High bit of base goes to REX.B and high bit of index to REX.X. 1485 // REX.W and REX.R are clear. 1486 inline void emit_rex_32(const Operand& op); 1487 1488 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B. 1489 // REX.W is cleared. If no REX bits are set, no byte is emitted. 1490 inline void emit_optional_rex_32(Register reg, Register rm_reg); 1491 1492 // The high bit of reg is used for REX.R, the high bit of op's base 1493 // register is used for REX.B, and the high bit of op's index register 1494 // is used for REX.X. REX.W is cleared. If no REX bits are set, nothing 1495 // is emitted. 1496 inline void emit_optional_rex_32(Register reg, const Operand& op); 1497 1498 // As for emit_optional_rex_32(Register, Register), except that 1499 // the registers are XMM registers. 1500 inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base); 1501 1502 // As for emit_optional_rex_32(Register, Register), except that 1503 // one of the registers is an XMM registers. 1504 inline void emit_optional_rex_32(XMMRegister reg, Register base); 1505 1506 // As for emit_optional_rex_32(Register, Register), except that 1507 // one of the registers is an XMM registers. 1508 inline void emit_optional_rex_32(Register reg, XMMRegister base); 1509 1510 // As for emit_optional_rex_32(Register, const Operand&), except that 1511 // the register is an XMM register. 1512 inline void emit_optional_rex_32(XMMRegister reg, const Operand& op); 1513 1514 // Optionally do as emit_rex_32(Register) if the register number has 1515 // the high bit set. 1516 inline void emit_optional_rex_32(Register rm_reg); 1517 1518 // Optionally do as emit_rex_32(const Operand&) if the operand register 1519 // numbers have a high bit set. 1520 inline void emit_optional_rex_32(const Operand& op); 1521 1522 1523 // Emit the ModR/M byte, and optionally the SIB byte and 1524 // 1- or 4-byte offset for a memory operand. Also encodes 1525 // the second operand of the operation, a register or operation 1526 // subcode, into the reg field of the ModR/M byte. 1527 void emit_operand(Register reg, const Operand& adr) { 1528 emit_operand(reg.low_bits(), adr); 1529 } 1530 1531 // Emit the ModR/M byte, and optionally the SIB byte and 1532 // 1- or 4-byte offset for a memory operand. Also used to encode 1533 // a three-bit opcode extension into the ModR/M byte. 1534 void emit_operand(int rm, const Operand& adr); 1535 1536 // Emit a ModR/M byte with registers coded in the reg and rm_reg fields. 1537 void emit_modrm(Register reg, Register rm_reg) { 1538 emit(0xC0 | reg.low_bits() << 3 | rm_reg.low_bits()); 1539 } 1540 1541 // Emit a ModR/M byte with an operation subcode in the reg field and 1542 // a register in the rm_reg field. 1543 void emit_modrm(int code, Register rm_reg) { 1544 ASSERT(is_uint3(code)); 1545 emit(0xC0 | code << 3 | rm_reg.low_bits()); 1546 } 1547 1548 // Emit the code-object-relative offset of the label's position 1549 inline void emit_code_relative_offset(Label* label); 1550 1551 // Emit machine code for one of the operations ADD, ADC, SUB, SBC, 1552 // AND, OR, XOR, or CMP. The encodings of these operations are all 1553 // similar, differing just in the opcode or in the reg field of the 1554 // ModR/M byte. 1555 void arithmetic_op_16(byte opcode, Register reg, Register rm_reg); 1556 void arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg); 1557 void arithmetic_op_32(byte opcode, Register reg, Register rm_reg); 1558 void arithmetic_op_32(byte opcode, Register reg, const Operand& rm_reg); 1559 void arithmetic_op(byte opcode, Register reg, Register rm_reg); 1560 void arithmetic_op(byte opcode, Register reg, const Operand& rm_reg); 1561 void immediate_arithmetic_op(byte subcode, Register dst, Immediate src); 1562 void immediate_arithmetic_op(byte subcode, const Operand& dst, Immediate src); 1563 // Operate on a byte in memory or register. 1564 void immediate_arithmetic_op_8(byte subcode, 1565 Register dst, 1566 Immediate src); 1567 void immediate_arithmetic_op_8(byte subcode, 1568 const Operand& dst, 1569 Immediate src); 1570 // Operate on a word in memory or register. 1571 void immediate_arithmetic_op_16(byte subcode, 1572 Register dst, 1573 Immediate src); 1574 void immediate_arithmetic_op_16(byte subcode, 1575 const Operand& dst, 1576 Immediate src); 1577 // Operate on a 32-bit word in memory or register. 1578 void immediate_arithmetic_op_32(byte subcode, 1579 Register dst, 1580 Immediate src); 1581 void immediate_arithmetic_op_32(byte subcode, 1582 const Operand& dst, 1583 Immediate src); 1584 1585 // Emit machine code for a shift operation. 1586 void shift(Register dst, Immediate shift_amount, int subcode); 1587 void shift_32(Register dst, Immediate shift_amount, int subcode); 1588 // Shift dst by cl % 64 bits. 1589 void shift(Register dst, int subcode); 1590 void shift_32(Register dst, int subcode); 1591 1592 void emit_farith(int b1, int b2, int i); 1593 1594 // labels 1595 // void print(Label* L); 1596 void bind_to(Label* L, int pos); 1597 1598 // record reloc info for current pc_ 1599 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 1600 1601 friend class CodePatcher; 1602 friend class EnsureSpace; 1603 friend class RegExpMacroAssemblerX64; 1604 1605 // Code buffer: 1606 // The buffer into which code and relocation info are generated. 1607 byte* buffer_; 1608 int buffer_size_; 1609 // True if the assembler owns the buffer, false if buffer is external. 1610 bool own_buffer_; 1611 1612 // code generation 1613 byte* pc_; // the program counter; moves forward 1614 RelocInfoWriter reloc_info_writer; 1615 1616 List< Handle<Code> > code_targets_; 1617 1618 PositionsRecorder positions_recorder_; 1619 1620 bool emit_debug_code_; 1621 1622 friend class PositionsRecorder; 1623}; 1624 1625 1626// Helper class that ensures that there is enough space for generating 1627// instructions and relocation information. The constructor makes 1628// sure that there is enough space and (in debug mode) the destructor 1629// checks that we did not generate too much. 1630class EnsureSpace BASE_EMBEDDED { 1631 public: 1632 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) { 1633 if (assembler_->buffer_overflow()) assembler_->GrowBuffer(); 1634#ifdef DEBUG 1635 space_before_ = assembler_->available_space(); 1636#endif 1637 } 1638 1639#ifdef DEBUG 1640 ~EnsureSpace() { 1641 int bytes_generated = space_before_ - assembler_->available_space(); 1642 ASSERT(bytes_generated < assembler_->kGap); 1643 } 1644#endif 1645 1646 private: 1647 Assembler* assembler_; 1648#ifdef DEBUG 1649 int space_before_; 1650#endif 1651}; 1652 1653} } // namespace v8::internal 1654 1655#endif // V8_X64_ASSEMBLER_X64_H_ 1656