1ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 2ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/*---------------------------------------------------------------*/ 3ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/*--- begin host_amd64_defs.h ---*/ 4ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/*---------------------------------------------------------------*/ 5ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 6ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* 7ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown This file is part of Valgrind, a dynamic binary instrumentation 8ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown framework. 9ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 10663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Copyright (C) 2004-2012 OpenWorks LLP 11ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown info@open-works.net 12ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 13ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown This program is free software; you can redistribute it and/or 14ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown modify it under the terms of the GNU General Public License as 15ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown published by the Free Software Foundation; either version 2 of the 16ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown License, or (at your option) any later version. 17ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 18ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown This program is distributed in the hope that it will be useful, but 19ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown WITHOUT ANY WARRANTY; without even the implied warranty of 20ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 21ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown General Public License for more details. 22ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 23ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown You should have received a copy of the GNU General Public License 24ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown along with this program; if not, write to the Free Software 25ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 26ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 02110-1301, USA. 27ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 28ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown The GNU General Public License is contained in the file COPYING. 29ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 30ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Neither the names of the U.S. Department of Energy nor the 31ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown University of California nor the names of its contributors may be 32ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown used to endorse or promote products derived from this software 33ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown without prior written permission. 34ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown*/ 35ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 36ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#ifndef __VEX_HOST_AMD64_DEFS_H 37ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#define __VEX_HOST_AMD64_DEFS_H 38ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 39ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 40ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Registers. --------- */ 41ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 42ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* The usual HReg abstraction. There are 16 real int regs, 6 real 43ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown float regs, and 16 real vector regs. 44ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown*/ 45ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 46ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void ppHRegAMD64 ( HReg ); 47ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 48ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RAX ( void ); 49ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RBX ( void ); 50ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RCX ( void ); 51ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RDX ( void ); 52ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RSP ( void ); 53ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RBP ( void ); 54ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RSI ( void ); 55ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_RDI ( void ); 56ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R8 ( void ); 57ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R9 ( void ); 58ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R10 ( void ); 59ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R11 ( void ); 60ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R12 ( void ); 61ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R13 ( void ); 62ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R14 ( void ); 63ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_R15 ( void ); 64ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 65ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_FAKE0 ( void ); 66ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_FAKE1 ( void ); 67ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_FAKE2 ( void ); 68ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_FAKE3 ( void ); 69ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_FAKE4 ( void ); 70ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_FAKE5 ( void ); 71ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 72ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM0 ( void ); 73ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM1 ( void ); 74ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM3 ( void ); 75ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM4 ( void ); 76ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM5 ( void ); 77ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM6 ( void ); 78ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM7 ( void ); 79ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM8 ( void ); 80ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM9 ( void ); 81ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM10 ( void ); 82ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM11 ( void ); 83ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HReg hregAMD64_XMM12 ( void ); 84ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 85ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 86ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Condition codes, AMD encoding. --------- */ 87ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 88ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 89ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 90ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_O = 0, /* overflow */ 91ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NO = 1, /* no overflow */ 92ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 93ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_B = 2, /* below */ 94ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NB = 3, /* not below */ 95ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 96ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_Z = 4, /* zero */ 97ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NZ = 5, /* not zero */ 98ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 99ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_BE = 6, /* below or equal */ 100ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NBE = 7, /* not below or equal */ 101ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 102ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_S = 8, /* negative */ 103ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NS = 9, /* not negative */ 104ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 105ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_P = 10, /* parity even */ 106ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NP = 11, /* not parity even */ 107ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 108ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_L = 12, /* jump less */ 109ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NL = 13, /* not less */ 110ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 111ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_LE = 14, /* less or equal */ 112ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_NLE = 15, /* not less or equal */ 113ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 114ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Acc_ALWAYS = 16 /* the usual hack */ 115ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 116ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64CondCode; 117ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 118ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HChar* showAMD64CondCode ( AMD64CondCode ); 119ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 120ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 121ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Memory address expressions (amodes). --------- */ 122ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 123ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 124ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 125ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aam_IR, /* Immediate + Reg */ 126ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aam_IRRS /* Immediate + Reg1 + (Reg2 << Shift) */ 127ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 128ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AModeTag; 129ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 130ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 131ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 132ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AModeTag tag; 133ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown union { 134ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 135ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UInt imm; 136ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg reg; 137ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } IR; 138ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 139ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UInt imm; 140ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg base; 141ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg index; 142ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Int shift; /* 0, 1, 2 or 3 only */ 143ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } IRRS; 144ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Aam; 145ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 146ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode; 147ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 148ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64AMode* AMD64AMode_IR ( UInt, HReg ); 149ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64AMode* AMD64AMode_IRRS ( UInt, HReg, HReg, Int ); 150ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 151ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64AMode* dopyAMD64AMode ( AMD64AMode* ); 152ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 153ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void ppAMD64AMode ( AMD64AMode* ); 154ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 155ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 156ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Operand, which can be reg, immediate or memory. --------- */ 157ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 158ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 159ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 160ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Armi_Imm, 161ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Armi_Reg, 162ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Armi_Mem 163ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 164ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMITag; 165ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 166ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 167ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 168ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMITag tag; 169ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown union { 170ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 171ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UInt imm32; 172ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Imm; 173ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 174ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg reg; 175ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Reg; 176ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 177ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* am; 178ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Mem; 179ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 180ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Armi; 181ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 182ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMI; 183ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 184ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RMI* AMD64RMI_Imm ( UInt ); 185ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RMI* AMD64RMI_Reg ( HReg ); 186ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RMI* AMD64RMI_Mem ( AMD64AMode* ); 187ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 188b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanovextern void ppAMD64RMI ( AMD64RMI* ); 189b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanovextern void ppAMD64RMI_lo32 ( AMD64RMI* ); 190ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 191ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 192ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Operand, which can be reg or immediate only. --------- */ 193ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 194ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 195ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 196ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ari_Imm, 197ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ari_Reg 198ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 199ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RITag; 200ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 201ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 202ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 203ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RITag tag; 204ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown union { 205ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 206ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UInt imm32; 207ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Imm; 208ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 209ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg reg; 210ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Reg; 211ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 212ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ari; 213ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 214ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RI; 215ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 216ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RI* AMD64RI_Imm ( UInt ); 217ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RI* AMD64RI_Reg ( HReg ); 218ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 219ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void ppAMD64RI ( AMD64RI* ); 220ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 221ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 222ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Operand, which can be reg or memory only. --------- */ 223ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 224ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 225ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 226ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Arm_Reg, 227ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Arm_Mem 228ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 229ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMTag; 230ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 231ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 232ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 233ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMTag tag; 234ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown union { 235ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 236ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg reg; 237ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Reg; 238ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 239ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* am; 240ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Mem; 241ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 242ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Arm; 243ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 244ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RM; 245ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 246ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RM* AMD64RM_Reg ( HReg ); 247ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64RM* AMD64RM_Mem ( AMD64AMode* ); 248ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 249ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void ppAMD64RM ( AMD64RM* ); 250ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 251ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 252ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- Instructions. --------- */ 253ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 254ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- */ 255ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 256ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 257ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aun_NEG, 258ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aun_NOT 259ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 260ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64UnaryOp; 261ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 262ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HChar* showAMD64UnaryOp ( AMD64UnaryOp ); 263ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 264ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 265ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- */ 266ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 267ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 268ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aalu_INVALID, 269ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aalu_MOV, 270ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aalu_CMP, 271ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aalu_ADD, Aalu_SUB, Aalu_ADC, Aalu_SBB, 272ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aalu_AND, Aalu_OR, Aalu_XOR, 273ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Aalu_MUL 274ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 275ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AluOp; 276ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 277ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HChar* showAMD64AluOp ( AMD64AluOp ); 278ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 279ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 280ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- */ 281ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 282ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 283ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ash_INVALID, 284ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ash_SHL, Ash_SHR, Ash_SAR 285ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 286ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64ShiftOp; 287ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 288ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HChar* showAMD64ShiftOp ( AMD64ShiftOp ); 289ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 290ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 291ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- */ 292ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 293ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 294ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Afp_INVALID, 295ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Binary */ 296ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Afp_SCALE, Afp_ATAN, Afp_YL2X, Afp_YL2XP1, Afp_PREM, Afp_PREM1, 297ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Unary */ 298ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Afp_SQRT, 299ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Afp_SIN, Afp_COS, Afp_TAN, 300ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Afp_ROUND, Afp_2XM1 301ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 302ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown A87FpOp; 303ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 304ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HChar* showA87FpOp ( A87FpOp ); 305ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 306ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 307ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- */ 308ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 309ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 310ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_INVALID, 311ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* mov */ 312ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MOV, 313ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Floating point binary */ 314ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_ADDF, Asse_SUBF, Asse_MULF, Asse_DIVF, 315ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MAXF, Asse_MINF, 316ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_CMPEQF, Asse_CMPLTF, Asse_CMPLEF, Asse_CMPUNF, 317ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Floating point unary */ 318ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_RCPF, Asse_RSQRTF, Asse_SQRTF, 319ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Bitwise */ 320ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_AND, Asse_OR, Asse_XOR, Asse_ANDN, 321ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_ADD8, Asse_ADD16, Asse_ADD32, Asse_ADD64, 322ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_QADD8U, Asse_QADD16U, 323ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_QADD8S, Asse_QADD16S, 324ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_SUB8, Asse_SUB16, Asse_SUB32, Asse_SUB64, 325ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_QSUB8U, Asse_QSUB16U, 326ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_QSUB8S, Asse_QSUB16S, 327ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MUL16, 328ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MULHI16U, 329ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MULHI16S, 330ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_AVG8U, Asse_AVG16U, 331ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MAX16S, 332ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MAX8U, 333ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MIN16S, 334ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_MIN8U, 335ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_CMPEQ8, Asse_CMPEQ16, Asse_CMPEQ32, 336ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_CMPGT8S, Asse_CMPGT16S, Asse_CMPGT32S, 337ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_SHL16, Asse_SHL32, Asse_SHL64, 338ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_SHR16, Asse_SHR32, Asse_SHR64, 339ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_SAR16, Asse_SAR32, 340ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_PACKSSD, Asse_PACKSSW, Asse_PACKUSW, 341ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_UNPCKHB, Asse_UNPCKHW, Asse_UNPCKHD, Asse_UNPCKHQ, 342ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Asse_UNPCKLB, Asse_UNPCKLW, Asse_UNPCKLD, Asse_UNPCKLQ 343ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 344ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64SseOp; 345ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 346ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern HChar* showAMD64SseOp ( AMD64SseOp ); 347ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 348ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 349ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* --------- */ 350ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 351ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 352ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Imm64, /* Generate 64-bit literal to register */ 353ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Alu64R, /* 64-bit mov/arith/logical, dst=REG */ 354ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Alu64M, /* 64-bit mov/arith/logical, dst=MEM */ 355ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Sh64, /* 64-bit shift/rotate, dst=REG or MEM */ 356ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Test64, /* 64-bit test (AND, set flags, discard result) */ 357ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Unary64, /* 64-bit not and neg */ 358ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Lea64, /* 64-bit compute EA into a reg */ 359b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov Ain_Alu32R, /* 32-bit add/sub/and/or/xor/cmp, dst=REG (a la Alu64R) */ 360ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_MulL, /* widening multiply */ 361ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Div, /* div and mod */ 362ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Push, /* push 64-bit value on stack */ 363ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Call, /* call to address in register */ 364663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Ain_XDirect, /* direct transfer to GA */ 365663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Ain_XIndir, /* indirect transfer to GA */ 366663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Ain_XAssisted, /* assisted transfer to GA */ 367ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_CMov64, /* conditional move */ 368ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_MovxLQ, /* reg-reg move, zx-ing/sx-ing top half */ 369ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_LoadEX, /* mov{s,z}{b,w,l}q from mem to reg */ 370ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Store, /* store 32/16/8 bit value in memory */ 371ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Set64, /* convert condition code to 64-bit value */ 372ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Bsfr64, /* 64-bit bsf/bsr */ 373ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_MFence, /* mem fence */ 374ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_ACAS, /* 8/16/32/64-bit lock;cmpxchg */ 375ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_DACAS, /* lock;cmpxchg8b/16b (doubleword ACAS, 2 x 376ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 32-bit or 2 x 64-bit only) */ 377ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_A87Free, /* free up x87 registers */ 378ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_A87PushPop, /* x87 loads/stores */ 379ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_A87FpOp, /* x87 operations */ 380ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_A87LdCW, /* load x87 control word */ 381ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_A87StSW, /* store x87 status word */ 382ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_LdMXCSR, /* load %mxcsr */ 383ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseUComIS, /* ucomisd/ucomiss, then get %rflags into int 384ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown register */ 385ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseSI2SF, /* scalar 32/64 int to 32/64 float conversion */ 386ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseSF2SI, /* scalar 32/64 float to 32/64 int conversion */ 387ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseSDSS, /* scalar float32 to/from float64 */ 388ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseLdSt, /* SSE load/store 32/64/128 bits, no alignment 389ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown constraints, upper 96/64/0 bits arbitrary */ 390ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseLdzLO, /* SSE load low 32/64 bits, zero remainder of reg */ 391ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Sse32Fx4, /* SSE binary, 32Fx4 */ 392ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Sse32FLo, /* SSE binary, 32F in lowest lane only */ 393ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Sse64Fx2, /* SSE binary, 64Fx2 */ 394ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_Sse64FLo, /* SSE binary, 64F in lowest lane only */ 395ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseReRg, /* SSE binary general reg-reg, Re, Rg */ 396ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Ain_SseCMov, /* SSE conditional move */ 397663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Ain_SseShuf, /* SSE2 shuffle (pshufd) */ 398663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu Ain_AvxLdSt, /* AVX load/store 256 bits, 399663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu no alignment constraints */ 400663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu Ain_AvxReRg, /* AVX binary general reg-reg, Re, Rg */ 401663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Ain_EvCheck, /* Event check */ 402663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Ain_ProfInc /* 64-bit profile counter increment */ 403ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 404ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64InstrTag; 405ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 406ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* Destinations are on the RIGHT (second operand) */ 407ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 408ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Browntypedef 409ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 410ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64InstrTag tag; 411ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown union { 412ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 413ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown ULong imm64; 414ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 415ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Imm64; 416ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 417ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AluOp op; 418ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMI* src; 419ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 420ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Alu64R; 421ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 422ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AluOp op; 423ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RI* src; 424ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* dst; 425ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Alu64M; 426ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 427ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64ShiftOp op; 428ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UInt src; /* shift amount, or 0 means %cl */ 429ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 430ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Sh64; 431ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 432ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UInt imm32; 433ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 434ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Test64; 435ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Not and Neg */ 436ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 437ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64UnaryOp op; 438ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 439ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Unary64; 440ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* 64-bit compute EA into a reg */ 441ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 442ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* am; 443ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 444ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Lea64; 445b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov /* 32-bit add/sub/and/or/xor/cmp, dst=REG (a la Alu64R) */ 446b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov struct { 447b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov AMD64AluOp op; 448b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov AMD64RMI* src; 449b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov HReg dst; 450b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanov } Alu32R; 451ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* 64 x 64 -> 128 bit widening multiply: RDX:RAX = RAX *s/u 452ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown r/m64 */ 453ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 454ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool syned; 455ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RM* src; 456ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } MulL; 457ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* amd64 div/idiv instruction. Modifies RDX and RAX and 458ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown reads src. */ 459ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 460ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool syned; 461ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Int sz; /* 4 or 8 only */ 462ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RM* src; 463ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Div; 464ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 465ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RMI* src; 466ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Push; 467ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Pseudo-insn. Call target (an absolute address), on given 468ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown condition (which could be Xcc_ALWAYS). */ 469ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 470ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64CondCode cond; 471ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Addr64 target; 472ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Int regparms; /* 0 .. 6 */ 473ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Call; 474663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Update the guest RIP value, then exit requesting to chain 475663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng to it. May be conditional. */ 476663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 477663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Addr64 dstGA; /* next guest address */ 478663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64AMode* amRIP; /* amode in guest state for RIP */ 479663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64CondCode cond; /* can be Acc_ALWAYS */ 480663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool toFastEP; /* chain to the slow or fast point? */ 481663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } XDirect; 482663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Boring transfer to a guest address not known at JIT time. 483663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Not chainable. May be conditional. */ 484663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 485663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dstGA; 486663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64AMode* amRIP; 487663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64CondCode cond; /* can be Acc_ALWAYS */ 488663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } XIndir; 489663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* Assisted transfer to a guest address, most general case. 490663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Not chainable. May be conditional. */ 491663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 492663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng HReg dstGA; 493663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64AMode* amRIP; 494663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64CondCode cond; /* can be Acc_ALWAYS */ 495ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown IRJumpKind jk; 496663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } XAssisted; 497ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Mov src to dst on the given condition, which may not 498ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown be the bogus Acc_ALWAYS. */ 499ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 500ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64CondCode cond; 501ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64RM* src; 502ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 503ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } CMov64; 504ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* reg-reg move, sx-ing/zx-ing top half */ 505ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 506ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool syned; 507ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 508ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 509ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } MovxLQ; 510ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Sign/Zero extending loads. Dst size is always 64 bits. */ 511ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 512ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar szSmall; /* only 1, 2 or 4 */ 513ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool syned; 514ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* src; 515ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 516ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } LoadEX; 517ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* 32/16/8 bit stores. */ 518ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 519ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar sz; /* only 1, 2 or 4 */ 520ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 521ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* dst; 522ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Store; 523ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Convert an amd64 condition code to a 64-bit value (0 or 1). */ 524ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 525ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64CondCode cond; 526ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 527ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Set64; 528ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* 64-bit bsf or bsr. */ 529ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 530ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool isFwds; 531ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 532ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 533ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Bsfr64; 534ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Mem fence. In short, an insn which flushes all preceding 535ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown loads and stores as much as possible before continuing. 536ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown On AMD64 we emit a real "mfence". */ 537ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 538ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } MFence; 539ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 540ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 541ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar sz; /* 1, 2, 4 or 8 */ 542ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } ACAS; 543ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 544ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 545ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar sz; /* 4 or 8 only */ 546ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } DACAS; 547ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 548ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* --- X87 --- */ 549ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 550ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* A very minimal set of x87 insns, that operate exactly in a 551ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown stack-like way so no need to think about x87 registers. */ 552ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 553ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Do 'ffree' on %st(7) .. %st(7-nregs) */ 554ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 555ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Int nregs; /* 1 <= nregs <= 7 */ 556ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } A87Free; 557ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 558ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Push a 32- or 64-bit FP value from memory onto the stack, 559ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown or move a value from the stack to memory and remove it 560ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown from the stack. */ 561ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 562ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 563ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool isPush; 564ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar szB; /* 4 or 8 */ 565ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } A87PushPop; 566ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 567ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Do an operation on the top-of-stack. This can be unary, in 568ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown which case it is %st0 = OP( %st0 ), or binary: %st0 = OP( 569ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown %st0, %st1 ). */ 570ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 571ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown A87FpOp op; 572ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } A87FpOp; 573ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 574ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Load the FPU control word. */ 575ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 576ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 577ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } A87LdCW; 578ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 579ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Store the FPU status word (fstsw m16) */ 580ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 581ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 582ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } A87StSW; 583ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 584ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* --- SSE --- */ 585ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 586ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Load 32 bits into %mxcsr. */ 587ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 588ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 589ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 590ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown LdMXCSR; 591ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* ucomisd/ucomiss, then get %rflags into int register */ 592ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 593ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar sz; /* 4 or 8 only */ 594ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg srcL; /* xmm */ 595ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg srcR; /* xmm */ 596ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; /* int */ 597ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseUComIS; 598ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* scalar 32/64 int to 32/64 float conversion */ 599ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 600ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar szS; /* 4 or 8 */ 601ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar szD; /* 4 or 8 */ 602ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; /* i class */ 603ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; /* v class */ 604ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseSI2SF; 605ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* scalar 32/64 float to 32/64 int conversion */ 606ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 607ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar szS; /* 4 or 8 */ 608ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar szD; /* 4 or 8 */ 609ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; /* v class */ 610ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; /* i class */ 611ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseSF2SI; 612ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* scalar float32 to/from float64 */ 613ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 614ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool from64; /* True: 64->32; False: 32->64 */ 615ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 616ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 617ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseSDSS; 618ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 619ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Bool isLoad; 620ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown UChar sz; /* 4, 8 or 16 only */ 621ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg reg; 622ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 623ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseLdSt; 624ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 625ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Int sz; /* 4 or 8 only */ 626ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg reg; 627ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* addr; 628ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseLdzLO; 629ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 630ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64SseOp op; 631ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 632ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 633ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Sse32Fx4; 634ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 635ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64SseOp op; 636ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 637ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 638ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Sse32FLo; 639ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 640ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64SseOp op; 641ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 642ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 643ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Sse64Fx2; 644ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 645ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64SseOp op; 646ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 647ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 648ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Sse64FLo; 649ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 650ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64SseOp op; 651ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 652ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 653ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseReRg; 654ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown /* Mov src to dst on the given condition, which may not 655ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown be the bogus Xcc_ALWAYS. */ 656ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 657ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64CondCode cond; 658ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 659ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 660ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseCMov; 661ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown struct { 662ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Int order; /* 0 <= order <= 0xFF */ 663ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg src; 664ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg dst; 665ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } SseShuf; 666663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu struct { 667663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu Bool isLoad; 668663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu HReg reg; 669663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu AMD64AMode* addr; 670663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu } AvxLdSt; 671663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu struct { 672663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu AMD64SseOp op; 673663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu HReg src; 674663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu HReg dst; 675663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng //uu } AvxReRg; 676663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 677663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64AMode* amCounter; 678663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64AMode* amFailAddr; 679663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } EvCheck; 680663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng struct { 681663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng /* No fields. The address of the counter to inc is 682663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng installed later, post-translation, by patching it in, 683663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng as it is not known at translation time. */ 684663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng } ProfInc; 685ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 686ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } Ain; 687ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 688ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64Instr; 689ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 690ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Imm64 ( ULong imm64, HReg dst ); 691ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Alu64R ( AMD64AluOp, AMD64RMI*, HReg ); 692ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Alu64M ( AMD64AluOp, AMD64RI*, AMD64AMode* ); 693ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Unary64 ( AMD64UnaryOp op, HReg dst ); 694ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Lea64 ( AMD64AMode* am, HReg dst ); 695b32f58018498ea2225959b0ba11c18f0c433deefEvgeniy Stepanovextern AMD64Instr* AMD64Instr_Alu32R ( AMD64AluOp, AMD64RMI*, HReg ); 696ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Sh64 ( AMD64ShiftOp, UInt, HReg ); 697ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Test64 ( UInt imm32, HReg dst ); 698ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_MulL ( Bool syned, AMD64RM* ); 699ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Div ( Bool syned, Int sz, AMD64RM* ); 700ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Push ( AMD64RMI* ); 701ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Call ( AMD64CondCode, Addr64, Int ); 702663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern AMD64Instr* AMD64Instr_XDirect ( Addr64 dstGA, AMD64AMode* amRIP, 703663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64CondCode cond, Bool toFastEP ); 704663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern AMD64Instr* AMD64Instr_XIndir ( HReg dstGA, AMD64AMode* amRIP, 705663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64CondCode cond ); 706663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern AMD64Instr* AMD64Instr_XAssisted ( HReg dstGA, AMD64AMode* amRIP, 707663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64CondCode cond, IRJumpKind jk ); 708ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_CMov64 ( AMD64CondCode, AMD64RM* src, HReg dst ); 709ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_MovxLQ ( Bool syned, HReg src, HReg dst ); 710ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_LoadEX ( UChar szSmall, Bool syned, 711ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown AMD64AMode* src, HReg dst ); 712ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Store ( UChar sz, HReg src, AMD64AMode* dst ); 713ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Set64 ( AMD64CondCode cond, HReg dst ); 714ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Bsfr64 ( Bool isFwds, HReg src, HReg dst ); 715ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_MFence ( void ); 716ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_ACAS ( AMD64AMode* addr, UChar sz ); 717ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_DACAS ( AMD64AMode* addr, UChar sz ); 718ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 719ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_A87Free ( Int nregs ); 720ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush, UChar szB ); 721ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_A87FpOp ( A87FpOp op ); 722ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_A87LdCW ( AMD64AMode* addr ); 723ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_A87StSW ( AMD64AMode* addr ); 724ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_LdMXCSR ( AMD64AMode* ); 725ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseUComIS ( Int sz, HReg srcL, HReg srcR, HReg dst ); 726ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseSI2SF ( Int szS, Int szD, HReg src, HReg dst ); 727ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseSF2SI ( Int szS, Int szD, HReg src, HReg dst ); 728ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseSDSS ( Bool from64, HReg src, HReg dst ); 729ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseLdSt ( Bool isLoad, Int sz, HReg, AMD64AMode* ); 730ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseLdzLO ( Int sz, HReg, AMD64AMode* ); 731ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Sse32Fx4 ( AMD64SseOp, HReg, HReg ); 732ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Sse32FLo ( AMD64SseOp, HReg, HReg ); 733ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp, HReg, HReg ); 734ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_Sse64FLo ( AMD64SseOp, HReg, HReg ); 735ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseReRg ( AMD64SseOp, HReg, HReg ); 736ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseCMov ( AMD64CondCode, HReg src, HReg dst ); 737ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg dst ); 738663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng//uu extern AMD64Instr* AMD64Instr_AvxLdSt ( Bool isLoad, HReg, AMD64AMode* ); 739663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng//uu extern AMD64Instr* AMD64Instr_AvxReRg ( AMD64SseOp, HReg, HReg ); 740663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern AMD64Instr* AMD64Instr_EvCheck ( AMD64AMode* amCounter, 741663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng AMD64AMode* amFailAddr ); 742663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern AMD64Instr* AMD64Instr_ProfInc ( void ); 743ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 744ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 745ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void ppAMD64Instr ( AMD64Instr*, Bool ); 746ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 747ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/* Some functions that insulate the register allocator from details 748ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown of the underlying instruction set. */ 749ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void getRegUsage_AMD64Instr ( HRegUsage*, AMD64Instr*, Bool ); 750ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr*, Bool ); 751ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern Bool isMove_AMD64Instr ( AMD64Instr*, HReg*, HReg* ); 752663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc, 753663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng UChar* buf, Int nbuf, AMD64Instr* i, 754663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool mode64, 755663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_chain_me_to_slowEP, 756663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_chain_me_to_fastEP, 757663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_xindir, 758663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_xassisted ); 759ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 760ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void genSpill_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, 761ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg rreg, Int offset, Bool ); 762ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void genReload_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, 763ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown HReg rreg, Int offset, Bool ); 764ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 765ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownextern void getAllocableRegs_AMD64 ( Int*, HReg** ); 766663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern HInstrArray* iselSB_AMD64 ( IRSB*, 767663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng VexArch, 768663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng VexArchInfo*, 769663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng VexAbiInfo*, 770663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Int offs_Host_EvC_Counter, 771663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Int offs_Host_EvC_FailAddr, 772663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool chainingAllowed, 773663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Bool addProfInc, 774663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng Addr64 max_ga ); 775663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 776663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* How big is an event check? This is kind of a kludge because it 777663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng depends on the offsets of host_EvC_FAILADDR and host_EvC_COUNTER, 778663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng and so assumes that they are both <= 128, and so can use the short 779663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng offset encoding. This is all checked with assertions, so in the 780663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng worst case we will merely assert at startup. */ 781663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern Int evCheckSzB_AMD64 ( void ); 782663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 783663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* Perform a chaining and unchaining of an XDirect jump. */ 784663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern VexInvalRange chainXDirect_AMD64 ( void* place_to_chain, 785663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_chain_me_EXPECTED, 786663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* place_to_jump_to ); 787663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 788663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern VexInvalRange unchainXDirect_AMD64 ( void* place_to_unchain, 789663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* place_to_jump_to_EXPECTED, 790663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng void* disp_cp_chain_me ); 791663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 792663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng/* Patch the counter location into an existing ProfInc point. */ 793663860b1408516d02ebfcb3a9999a134e6cfb223Ben Chengextern VexInvalRange patchProfInc_AMD64 ( void* place_to_patch, 794663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng ULong* location_of_counter ); 795663860b1408516d02ebfcb3a9999a134e6cfb223Ben Cheng 796ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 797ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#endif /* ndef __VEX_HOST_AMD64_DEFS_H */ 798ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 799ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/*---------------------------------------------------------------*/ 800ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/*--- end host_amd64_defs.h ---*/ 801ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/*---------------------------------------------------------------*/ 802