sad_halfpel_inline.h revision 29a84457aed4c45bc900998b5e11c03023264208 
1/* ------------------------------------------------------------------
2 * Copyright (C) 1998-2009 PacketVideo
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either
13 * express or implied.
14 * See the License for the specific language governing permissions
15 * and limitations under the License.
16 * -------------------------------------------------------------------
17 */
18
19#ifndef _SAD_HALFPEL_INLINE_H_
20#define _SAD_HALFPEL_INLINE_H_
21
22#ifdef __cplusplus
23extern "C"
24{
25#endif
26
27#if defined(__GNUC__) && defined(__arm__) /* ARM GNU COMPILER  */
28
29    __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
30    {
31        tmp = (tmp2 >> 1) - tmp;
32        if (tmp > 0) sad += tmp;
33        else sad -= tmp;
34
35        return sad;
36    }
37
38    __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
39    {
40        tmp = (tmp >> 2) - tmp2;
41        if (tmp > 0) sad += tmp;
42        else sad -= tmp;
43
44        return sad;
45    }
46
47#elif defined(__CC_ARM)  /* only work with arm v5 */
48
49    __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
50    {
51        __asm
52        {
53            rsbs    tmp, tmp, tmp2, asr #1 ;
54            rsbmi   tmp, tmp, #0 ;
55            add     sad, sad, tmp ;
56        }
57
58        return sad;
59    }
60
61    __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
62    {
63        __asm
64        {
65            rsbs    tmp, tmp2, tmp, asr #2 ;
66            rsbmi   tmp, tmp, #0 ;
67            add     sad, sad, tmp ;
68        }
69
70        return sad;
71    }
72
73#elif defined(__GNUC__) && defined(__arm__) /* ARM GNU COMPILER  */
74
75    __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
76    {
77__asm__ volatile("rsbs	%1, %1, %2, asr #1\n\trsbmi %1, %1, #0\n\tadd  %0, %0, %1": "=r"(sad), "=r"(tmp): "r"(tmp2));
78
79        return sad;
80    }
81
82    __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2)
83    {
84__asm__ volatile("rsbs	%1, %2, %1, asr #2\n\trsbmi %1, %1, #0\n\tadd	%0, %0, %1": "=r"(sad), "=r"(tmp): "r"(tmp2));
85
86        return sad;
87    }
88
89#endif
90
91#ifdef __cplusplus
92}
93#endif
94
95#endif //_SAD_HALFPEL_INLINE_H_
96
97