hwc.cpp revision 89bb5743fcbcf78bbc517e5bd690de3996981fd4
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16#include <errno.h> 17#include <fcntl.h> 18#include <poll.h> 19#include <pthread.h> 20#include <stdio.h> 21#include <stdlib.h> 22 23#include <sys/ioctl.h> 24#include <sys/mman.h> 25#include <sys/time.h> 26#include <sys/resource.h> 27 28#include <s3c-fb.h> 29 30#include <EGL/egl.h> 31 32#define HWC_REMOVE_DEPRECATED_VERSIONS 1 33 34#include <cutils/compiler.h> 35#include <cutils/log.h> 36#include <cutils/properties.h> 37#include <hardware/gralloc.h> 38#include <hardware/hardware.h> 39#include <hardware/hwcomposer.h> 40#include <hardware_legacy/uevent.h> 41#include <utils/String8.h> 42#include <utils/Vector.h> 43 44#include <sync/sync.h> 45 46#include "ion.h" 47#include "gralloc_priv.h" 48#include "exynos_gscaler.h" 49#include "exynos_format.h" 50#include "exynos_v4l2.h" 51#include "s5p_tvout_v4l2.h" 52 53const size_t NUM_HW_WINDOWS = 5; 54const size_t NO_FB_NEEDED = NUM_HW_WINDOWS + 1; 55const size_t MAX_PIXELS = 2560 * 1600 * 2; 56const size_t GSC_W_ALIGNMENT = 16; 57const size_t GSC_H_ALIGNMENT = 16; 58const size_t FIMD_GSC_IDX = 0; 59const size_t HDMI_GSC_IDX = 1; 60const int AVAILABLE_GSC_UNITS[] = { 0, 3 }; 61const size_t NUM_GSC_UNITS = sizeof(AVAILABLE_GSC_UNITS) / 62 sizeof(AVAILABLE_GSC_UNITS[0]); 63const size_t BURSTLEN_BYTES = 16 * 8; 64const size_t NUM_HDMI_BUFFERS = 3; 65 66struct exynos5_hwc_composer_device_1_t; 67 68struct exynos5_gsc_map_t { 69 enum { 70 GSC_NONE = 0, 71 GSC_M2M, 72 // TODO: GSC_LOCAL_PATH 73 } mode; 74 int idx; 75}; 76 77struct exynos5_hwc_post_data_t { 78 int overlay_map[NUM_HW_WINDOWS]; 79 exynos5_gsc_map_t gsc_map[NUM_HW_WINDOWS]; 80 size_t fb_window; 81}; 82 83const size_t NUM_GSC_DST_BUFS = 3; 84struct exynos5_gsc_data_t { 85 void *gsc; 86 exynos_gsc_img src_cfg; 87 exynos_gsc_img dst_cfg; 88 buffer_handle_t dst_buf[NUM_GSC_DST_BUFS]; 89 size_t current_buf; 90}; 91 92struct hdmi_layer_t { 93 int id; 94 int fd; 95 bool enabled; 96 exynos_gsc_img cfg; 97 98 bool streaming; 99 size_t current_buf; 100 size_t queued_buf; 101}; 102 103struct exynos5_hwc_composer_device_1_t { 104 hwc_composer_device_1_t base; 105 106 int fd; 107 int vsync_fd; 108 exynos5_hwc_post_data_t bufs; 109 110 const private_module_t *gralloc_module; 111 alloc_device_t *alloc_device; 112 const hwc_procs_t *procs; 113 pthread_t vsync_thread; 114 int force_gpu; 115 116 int32_t xres; 117 int32_t yres; 118 int32_t xdpi; 119 int32_t ydpi; 120 int32_t vsync_period; 121 122 int hdmi_mixer0; 123 bool hdmi_hpd; 124 bool hdmi_enabled; 125 bool hdmi_blanked; 126 int hdmi_w; 127 int hdmi_h; 128 129 hdmi_layer_t hdmi_layers[2]; 130 131 exynos5_gsc_data_t gsc[NUM_GSC_UNITS]; 132 133 struct s3c_fb_win_config last_config[NUM_HW_WINDOWS]; 134 size_t last_fb_window; 135 const void *last_handles[NUM_HW_WINDOWS]; 136 exynos5_gsc_map_t last_gsc_map[NUM_HW_WINDOWS]; 137}; 138 139static void exynos5_cleanup_gsc_m2m(exynos5_hwc_composer_device_1_t *pdev, 140 size_t gsc_idx); 141 142static void dump_handle(private_handle_t *h) 143{ 144 ALOGV("\t\tformat = %d, width = %u, height = %u, stride = %u, vstride = %u", 145 h->format, h->width, h->height, h->stride, h->vstride); 146} 147 148static void dump_layer(hwc_layer_1_t const *l) 149{ 150 ALOGV("\ttype=%d, flags=%08x, handle=%p, tr=%02x, blend=%04x, " 151 "{%d,%d,%d,%d}, {%d,%d,%d,%d}", 152 l->compositionType, l->flags, l->handle, l->transform, 153 l->blending, 154 l->sourceCrop.left, 155 l->sourceCrop.top, 156 l->sourceCrop.right, 157 l->sourceCrop.bottom, 158 l->displayFrame.left, 159 l->displayFrame.top, 160 l->displayFrame.right, 161 l->displayFrame.bottom); 162 163 if(l->handle && !(l->flags & HWC_SKIP_LAYER)) 164 dump_handle(private_handle_t::dynamicCast(l->handle)); 165} 166 167static void dump_config(s3c_fb_win_config &c) 168{ 169 ALOGV("\tstate = %u", c.state); 170 if (c.state == c.S3C_FB_WIN_STATE_BUFFER) { 171 ALOGV("\t\tfd = %d, offset = %u, stride = %u, " 172 "x = %d, y = %d, w = %u, h = %u, " 173 "format = %u, blending = %u", 174 c.fd, c.offset, c.stride, 175 c.x, c.y, c.w, c.h, 176 c.format, c.blending); 177 } 178 else if (c.state == c.S3C_FB_WIN_STATE_COLOR) { 179 ALOGV("\t\tcolor = %u", c.color); 180 } 181} 182 183static void dump_gsc_img(exynos_gsc_img &c) 184{ 185 ALOGV("\tx = %u, y = %u, w = %u, h = %u, fw = %u, fh = %u", 186 c.x, c.y, c.w, c.h, c.fw, c.fh); 187 ALOGV("\taddr = {%u, %u, %u}, rot = %u, cacheable = %u, drmMode = %u", 188 c.yaddr, c.uaddr, c.vaddr, c.rot, c.cacheable, c.drmMode); 189} 190 191inline int WIDTH(const hwc_rect &rect) { return rect.right - rect.left; } 192inline int HEIGHT(const hwc_rect &rect) { return rect.bottom - rect.top; } 193template<typename T> inline T max(T a, T b) { return (a > b) ? a : b; } 194template<typename T> inline T min(T a, T b) { return (a < b) ? a : b; } 195 196static bool is_transformed(const hwc_layer_1_t &layer) 197{ 198 return layer.transform != 0; 199} 200 201static bool is_rotated(const hwc_layer_1_t &layer) 202{ 203 return (layer.transform & HAL_TRANSFORM_ROT_90) || 204 (layer.transform & HAL_TRANSFORM_ROT_180); 205} 206 207static bool is_scaled(const hwc_layer_1_t &layer) 208{ 209 return WIDTH(layer.displayFrame) != WIDTH(layer.sourceCrop) || 210 HEIGHT(layer.displayFrame) != HEIGHT(layer.sourceCrop); 211} 212 213static inline bool gsc_dst_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 214{ 215 return c1.x != c2.x || 216 c1.y != c2.y || 217 c1.w != c2.w || 218 c1.h != c2.h || 219 c1.format != c2.format || 220 c1.rot != c2.rot || 221 c1.cacheable != c2.cacheable || 222 c1.drmMode != c2.drmMode; 223} 224 225static inline bool gsc_src_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 226{ 227 return gsc_dst_cfg_changed(c1, c2) || 228 c1.fw != c2.fw || 229 c1.fh != c2.fh; 230} 231 232static enum s3c_fb_pixel_format exynos5_format_to_s3c_format(int format) 233{ 234 switch (format) { 235 case HAL_PIXEL_FORMAT_RGBA_8888: 236 return S3C_FB_PIXEL_FORMAT_RGBA_8888; 237 case HAL_PIXEL_FORMAT_RGBX_8888: 238 return S3C_FB_PIXEL_FORMAT_RGBX_8888; 239 case HAL_PIXEL_FORMAT_RGBA_5551: 240 return S3C_FB_PIXEL_FORMAT_RGBA_5551; 241 case HAL_PIXEL_FORMAT_RGB_565: 242 return S3C_FB_PIXEL_FORMAT_RGB_565; 243 case HAL_PIXEL_FORMAT_BGRA_8888: 244 return S3C_FB_PIXEL_FORMAT_BGRA_8888; 245 default: 246 return S3C_FB_PIXEL_FORMAT_MAX; 247 } 248} 249 250static bool exynos5_format_is_supported(int format) 251{ 252 return exynos5_format_to_s3c_format(format) < S3C_FB_PIXEL_FORMAT_MAX; 253} 254 255static bool exynos5_format_is_rgb(int format) 256{ 257 switch (format) { 258 case HAL_PIXEL_FORMAT_RGBA_8888: 259 case HAL_PIXEL_FORMAT_RGBX_8888: 260 case HAL_PIXEL_FORMAT_RGB_888: 261 case HAL_PIXEL_FORMAT_RGB_565: 262 case HAL_PIXEL_FORMAT_BGRA_8888: 263 case HAL_PIXEL_FORMAT_RGBA_5551: 264 case HAL_PIXEL_FORMAT_RGBA_4444: 265 return true; 266 267 default: 268 return false; 269 } 270} 271 272static bool exynos5_format_is_supported_by_gscaler(int format) 273{ 274 switch (format) { 275 case HAL_PIXEL_FORMAT_RGBX_8888: 276 case HAL_PIXEL_FORMAT_RGB_565: 277 case HAL_PIXEL_FORMAT_EXYNOS_YV12: 278 case HAL_PIXEL_FORMAT_YCbCr_420_SP: 279 case HAL_PIXEL_FORMAT_YCbCr_420_SP_TILED: 280 return true; 281 282 default: 283 return false; 284 } 285} 286 287static bool exynos5_format_is_ycrcb(int format) 288{ 289 return format == HAL_PIXEL_FORMAT_EXYNOS_YV12; 290} 291 292static bool exynos5_format_requires_gscaler(int format) 293{ 294 return (exynos5_format_is_supported_by_gscaler(format) && 295 (format != HAL_PIXEL_FORMAT_RGBX_8888) && (format != HAL_PIXEL_FORMAT_RGB_565)); 296} 297 298static uint8_t exynos5_format_to_bpp(int format) 299{ 300 switch (format) { 301 case HAL_PIXEL_FORMAT_RGBA_8888: 302 case HAL_PIXEL_FORMAT_RGBX_8888: 303 case HAL_PIXEL_FORMAT_BGRA_8888: 304 return 32; 305 306 case HAL_PIXEL_FORMAT_RGBA_5551: 307 case HAL_PIXEL_FORMAT_RGBA_4444: 308 case HAL_PIXEL_FORMAT_RGB_565: 309 return 16; 310 311 default: 312 ALOGW("unrecognized pixel format %u", format); 313 return 0; 314 } 315} 316 317static bool is_x_aligned(const hwc_layer_1_t &layer, int format) 318{ 319 if (!exynos5_format_is_supported(format)) 320 return true; 321 322 uint8_t bpp = exynos5_format_to_bpp(format); 323 uint8_t pixel_alignment = 32 / bpp; 324 325 return (layer.displayFrame.left % pixel_alignment) == 0 && 326 (layer.displayFrame.right % pixel_alignment) == 0; 327} 328 329static bool exynos5_supports_gscaler(hwc_layer_1_t &layer, int format, 330 bool local_path) 331{ 332 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 333 334 int max_w = is_rotated(layer) ? 2048 : 4800; 335 int max_h = is_rotated(layer) ? 2048 : 3344; 336 337 bool rot90or270 = !!(layer.transform & HAL_TRANSFORM_ROT_90); 338 // n.b.: HAL_TRANSFORM_ROT_270 = HAL_TRANSFORM_ROT_90 | 339 // HAL_TRANSFORM_ROT_180 340 341 int src_w = WIDTH(layer.sourceCrop), src_h = HEIGHT(layer.sourceCrop); 342 int dest_w, dest_h; 343 if (rot90or270) { 344 dest_w = HEIGHT(layer.displayFrame); 345 dest_h = WIDTH(layer.displayFrame); 346 } else { 347 dest_w = WIDTH(layer.displayFrame); 348 dest_h = HEIGHT(layer.displayFrame); 349 } 350 int max_downscale = local_path ? 4 : 16; 351 const int max_upscale = 8; 352 353 return exynos5_format_is_supported_by_gscaler(format) && 354 handle->stride <= max_w && 355 handle->stride % GSC_W_ALIGNMENT == 0 && 356 src_w <= dest_w * max_downscale && 357 dest_w <= src_w * max_upscale && 358 handle->vstride <= max_h && 359 handle->vstride % GSC_H_ALIGNMENT == 0 && 360 src_h <= dest_h * max_downscale && 361 dest_h <= src_h * max_upscale && 362 // per 46.2 363 (!rot90or270 || layer.sourceCrop.top % 2 == 0) && 364 (!rot90or270 || layer.sourceCrop.left % 2 == 0); 365 // per 46.3.1.6 366} 367 368static bool exynos5_requires_gscaler(hwc_layer_1_t &layer, int format) 369{ 370 return exynos5_format_requires_gscaler(format) || is_scaled(layer) 371 || is_transformed(layer) || !is_x_aligned(layer, format); 372} 373 374int hdmi_get_config(struct exynos5_hwc_composer_device_1_t *dev) 375{ 376 struct v4l2_dv_preset preset; 377 struct v4l2_dv_enum_preset enum_preset; 378 int index = 0; 379 bool found = false; 380 int ret; 381 382 if (ioctl(dev->hdmi_layers[0].fd, VIDIOC_G_DV_PRESET, &preset) < 0) { 383 ALOGE("%s: g_dv_preset error, %d", __func__, errno); 384 return -1; 385 } 386 387 while (true) { 388 enum_preset.index = index++; 389 ret = ioctl(dev->hdmi_layers[0].fd, VIDIOC_ENUM_DV_PRESETS, &enum_preset); 390 391 if (ret < 0) { 392 if (errno == EINVAL) 393 break; 394 ALOGE("%s: enum_dv_presets error, %d", __func__, errno); 395 return -1; 396 } 397 398 ALOGV("%s: %d preset=%02d width=%d height=%d name=%s", 399 __func__, enum_preset.index, enum_preset.preset, 400 enum_preset.width, enum_preset.height, enum_preset.name); 401 402 if (preset.preset == enum_preset.preset) { 403 dev->hdmi_w = enum_preset.width; 404 dev->hdmi_h = enum_preset.height; 405 found = true; 406 } 407 } 408 409 return found ? 0 : -1; 410} 411 412static enum s3c_fb_blending exynos5_blending_to_s3c_blending(int32_t blending) 413{ 414 switch (blending) { 415 case HWC_BLENDING_NONE: 416 return S3C_FB_BLENDING_NONE; 417 case HWC_BLENDING_PREMULT: 418 return S3C_FB_BLENDING_PREMULT; 419 case HWC_BLENDING_COVERAGE: 420 return S3C_FB_BLENDING_COVERAGE; 421 422 default: 423 return S3C_FB_BLENDING_MAX; 424 } 425} 426 427static bool exynos5_blending_is_supported(int32_t blending) 428{ 429 return exynos5_blending_to_s3c_blending(blending) < S3C_FB_BLENDING_MAX; 430} 431 432 433static int hdmi_enable_layer(struct exynos5_hwc_composer_device_1_t *dev, 434 hdmi_layer_t &hl) 435{ 436 if (hl.enabled) 437 return 0; 438 439 struct v4l2_requestbuffers reqbuf; 440 memset(&reqbuf, 0, sizeof(reqbuf)); 441 reqbuf.count = NUM_HDMI_BUFFERS; 442 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 443 reqbuf.memory = V4L2_MEMORY_DMABUF; 444 if (exynos_v4l2_reqbufs(hl.fd, &reqbuf) < 0) { 445 ALOGE("%s: layer%d: reqbufs failed %d", __func__, hl.id, errno); 446 return -1; 447 } 448 449 if (reqbuf.count != NUM_HDMI_BUFFERS) { 450 ALOGE("%s: layer%d: didn't get buffer", __func__, hl.id); 451 return -1; 452 } 453 454 if (hl.id == 1) { 455 if (exynos_v4l2_s_ctrl(hl.fd, V4L2_CID_TV_PIXEL_BLEND_ENABLE, 1) < 0) { 456 ALOGE("%s: layer%d: PIXEL_BLEND_ENABLE failed %d", __func__, 457 hl.id, errno); 458 return -1; 459 } 460 } 461 462 ALOGV("%s: layer%d enabled", __func__, hl.id); 463 hl.enabled = true; 464 return 0; 465} 466 467static void hdmi_disable_layer(struct exynos5_hwc_composer_device_1_t *dev, 468 hdmi_layer_t &hl) 469{ 470 if (!hl.enabled) 471 return; 472 473 if (hl.streaming) { 474 if (exynos_v4l2_streamoff(hl.fd, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) < 0) 475 ALOGE("%s: layer%d: streamoff failed %d", __func__, hl.id, errno); 476 hl.streaming = false; 477 } 478 479 struct v4l2_requestbuffers reqbuf; 480 memset(&reqbuf, 0, sizeof(reqbuf)); 481 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 482 reqbuf.memory = V4L2_MEMORY_DMABUF; 483 if (exynos_v4l2_reqbufs(hl.fd, &reqbuf) < 0) 484 ALOGE("%s: layer%d: reqbufs failed %d", __func__, hl.id, errno); 485 486 memset(&hl.cfg, 0, sizeof(hl.cfg)); 487 hl.current_buf = 0; 488 hl.queued_buf = 0; 489 hl.enabled = false; 490 491 ALOGV("%s: layer%d disabled", __func__, hl.id); 492} 493 494static int hdmi_enable(struct exynos5_hwc_composer_device_1_t *dev) 495{ 496 if (dev->hdmi_enabled) 497 return 0; 498 499 if (dev->hdmi_blanked) 500 return 0; 501 502 struct v4l2_subdev_format sd_fmt; 503 memset(&sd_fmt, 0, sizeof(sd_fmt)); 504 sd_fmt.pad = MIXER_G0_SUBDEV_PAD_SINK; 505 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 506 sd_fmt.format.width = dev->hdmi_w; 507 sd_fmt.format.height = dev->hdmi_h; 508 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 509 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 510 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 511 return -1; 512 } 513 514 struct v4l2_subdev_crop sd_crop; 515 memset(&sd_crop, 0, sizeof(sd_crop)); 516 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SINK; 517 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 518 sd_crop.rect.width = dev->hdmi_w; 519 sd_crop.rect.height = dev->hdmi_h; 520 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 521 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 522 return -1; 523 } 524 525 memset(&sd_fmt, 0, sizeof(sd_fmt)); 526 sd_fmt.pad = MIXER_G0_SUBDEV_PAD_SOURCE; 527 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 528 sd_fmt.format.width = dev->hdmi_w; 529 sd_fmt.format.height = dev->hdmi_h; 530 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 531 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 532 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 533 return -1; 534 } 535 536 memset(&sd_crop, 0, sizeof(sd_crop)); 537 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SOURCE; 538 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 539 sd_crop.rect.width = dev->hdmi_w; 540 sd_crop.rect.height = dev->hdmi_h; 541 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 542 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 543 return -1; 544 } 545 546 hdmi_enable_layer(dev, dev->hdmi_layers[1]); 547 548 dev->hdmi_enabled = true; 549 return 0; 550} 551 552static void hdmi_disable(struct exynos5_hwc_composer_device_1_t *dev) 553{ 554 if (!dev->hdmi_enabled) 555 return; 556 557 hdmi_disable_layer(dev, dev->hdmi_layers[0]); 558 hdmi_disable_layer(dev, dev->hdmi_layers[1]); 559 560 exynos5_cleanup_gsc_m2m(dev, HDMI_GSC_IDX); 561 dev->hdmi_enabled = false; 562} 563 564static int hdmi_output(struct exynos5_hwc_composer_device_1_t *dev, 565 hdmi_layer_t &hl, 566 hwc_layer_1_t &layer, 567 private_handle_t *h) 568{ 569 int ret = 0; 570 571 exynos_gsc_img cfg; 572 memset(&cfg, 0, sizeof(cfg)); 573 cfg.x = layer.displayFrame.left; 574 cfg.y = layer.displayFrame.top; 575 cfg.w = WIDTH(layer.displayFrame); 576 cfg.h = HEIGHT(layer.displayFrame); 577 578 if (gsc_src_cfg_changed(hl.cfg, cfg)) { 579 hdmi_disable_layer(dev, hl); 580 581 struct v4l2_format fmt; 582 memset(&fmt, 0, sizeof(fmt)); 583 fmt.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 584 fmt.fmt.pix_mp.width = cfg.w; 585 fmt.fmt.pix_mp.height = cfg.h; 586 fmt.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_BGR32; 587 fmt.fmt.pix_mp.field = V4L2_FIELD_ANY; 588 fmt.fmt.pix_mp.num_planes = 1; 589 ret = exynos_v4l2_s_fmt(hl.fd, &fmt); 590 if (ret < 0) { 591 ALOGE("%s: layer%d: s_fmt failed %d", __func__, hl.id, errno); 592 goto err; 593 } 594 595 struct v4l2_subdev_crop sd_crop; 596 memset(&sd_crop, 0, sizeof(sd_crop)); 597 if (hl.id == 0) 598 sd_crop.pad = MIXER_G0_SUBDEV_PAD_SOURCE; 599 else 600 sd_crop.pad = MIXER_G1_SUBDEV_PAD_SOURCE; 601 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 602 sd_crop.rect.left = cfg.x; 603 sd_crop.rect.top = cfg.y; 604 sd_crop.rect.width = cfg.w; 605 sd_crop.rect.height = cfg.h; 606 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 607 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 608 goto err; 609 } 610 611 hdmi_enable_layer(dev, hl); 612 613 ALOGV("HDMI layer%d configuration:", hl.id); 614 dump_gsc_img(cfg); 615 hl.cfg = cfg; 616 } 617 618 struct v4l2_buffer buffer; 619 struct v4l2_plane planes[1]; 620 621 if (hl.queued_buf == NUM_HDMI_BUFFERS) { 622 memset(&buffer, 0, sizeof(buffer)); 623 memset(planes, 0, sizeof(planes)); 624 buffer.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 625 buffer.memory = V4L2_MEMORY_DMABUF; 626 buffer.length = 1; 627 buffer.m.planes = planes; 628 ret = exynos_v4l2_dqbuf(hl.fd, &buffer); 629 if (ret < 0) { 630 ALOGE("%s: layer%d: dqbuf failed %d", __func__, hl.id, errno); 631 goto err; 632 } 633 hl.queued_buf--; 634 } 635 636 memset(&buffer, 0, sizeof(buffer)); 637 memset(planes, 0, sizeof(planes)); 638 buffer.index = hl.current_buf; 639 buffer.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 640 buffer.memory = V4L2_MEMORY_DMABUF; 641 buffer.flags = V4L2_BUF_FLAG_USE_SYNC; 642 buffer.reserved = layer.acquireFenceFd; 643 buffer.length = 1; 644 buffer.m.planes = planes; 645 buffer.m.planes[0].m.fd = h->fd; 646 if (exynos_v4l2_qbuf(hl.fd, &buffer) < 0) { 647 ALOGE("%s: layer%d: qbuf failed %d", __func__, hl.id, errno); 648 ret = -1; 649 goto err; 650 } 651 652 layer.releaseFenceFd = buffer.reserved; 653 654 hl.queued_buf++; 655 hl.current_buf = (hl.current_buf + 1) % NUM_HDMI_BUFFERS; 656 657 if (!hl.streaming) { 658 if (exynos_v4l2_streamon(hl.fd, buffer.type) < 0) { 659 ALOGE("%s: layer%d: streamon failed %d", __func__, hl.id, errno); 660 ret = -1; 661 goto err; 662 } 663 hl.streaming = true; 664 } 665 666err: 667 if (layer.acquireFenceFd >= 0) 668 close(layer.acquireFenceFd); 669 670 return ret; 671} 672 673bool exynos5_is_offscreen(hwc_layer_1_t &layer, 674 struct exynos5_hwc_composer_device_1_t *pdev) 675{ 676 return layer.sourceCrop.left > pdev->xres || 677 layer.sourceCrop.right < 0 || 678 layer.sourceCrop.top > pdev->yres || 679 layer.sourceCrop.bottom < 0; 680} 681 682size_t exynos5_visible_width(hwc_layer_1_t &layer, int format, 683 struct exynos5_hwc_composer_device_1_t *pdev) 684{ 685 int bpp; 686 if (exynos5_requires_gscaler(layer, format)) 687 bpp = 32; 688 else 689 bpp = exynos5_format_to_bpp(format); 690 int left = max(layer.displayFrame.left, 0); 691 int right = min(layer.displayFrame.right, pdev->xres); 692 693 return (right - left) * bpp / 8; 694} 695 696bool exynos5_supports_overlay(hwc_layer_1_t &layer, size_t i, 697 struct exynos5_hwc_composer_device_1_t *pdev) 698{ 699 if (layer.flags & HWC_SKIP_LAYER) { 700 ALOGV("\tlayer %u: skipping", i); 701 return false; 702 } 703 704 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 705 706 if (!handle) { 707 ALOGV("\tlayer %u: handle is NULL", i); 708 return false; 709 } 710 711 if (exynos5_requires_gscaler(layer, handle->format)) { 712 if (!exynos5_supports_gscaler(layer, handle->format, false)) { 713 ALOGV("\tlayer %u: gscaler required but not supported", i); 714 return false; 715 } 716 } else { 717 if (!exynos5_format_is_supported(handle->format)) { 718 ALOGV("\tlayer %u: pixel format %u not supported", i, handle->format); 719 return false; 720 } 721 } 722 if (!exynos5_blending_is_supported(layer.blending)) { 723 ALOGV("\tlayer %u: blending %d not supported", i, layer.blending); 724 return false; 725 } 726 if (CC_UNLIKELY(exynos5_is_offscreen(layer, pdev))) { 727 ALOGW("\tlayer %u: off-screen", i); 728 return false; 729 } 730 if (exynos5_visible_width(layer, handle->format, pdev) < BURSTLEN_BYTES) { 731 ALOGV("\tlayer %u: visible area is too narrow", i); 732 return false; 733 } 734 735 return true; 736} 737 738inline bool intersect(const hwc_rect &r1, const hwc_rect &r2) 739{ 740 return !(r1.left > r2.right || 741 r1.right < r2.left || 742 r1.top > r2.bottom || 743 r1.bottom < r2.top); 744} 745 746inline hwc_rect intersection(const hwc_rect &r1, const hwc_rect &r2) 747{ 748 hwc_rect i; 749 i.top = max(r1.top, r2.top); 750 i.bottom = min(r1.bottom, r2.bottom); 751 i.left = max(r1.left, r2.left); 752 i.right = min(r1.right, r2.right); 753 return i; 754} 755 756static int exynos5_prepare_fimd(exynos5_hwc_composer_device_1_t *pdev, 757 hwc_display_contents_1_t* contents) 758{ 759 ALOGV("preparing %u layers for FIMD", contents->numHwLayers); 760 761 memset(pdev->bufs.gsc_map, 0, sizeof(pdev->bufs.gsc_map)); 762 763 bool force_fb = pdev->force_gpu; 764 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 765 pdev->bufs.overlay_map[i] = -1; 766 767 bool fb_needed = false; 768 size_t first_fb = 0, last_fb = 0; 769 770 // find unsupported overlays 771 for (size_t i = 0; i < contents->numHwLayers; i++) { 772 hwc_layer_1_t &layer = contents->hwLayers[i]; 773 774 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 775 ALOGV("\tlayer %u: framebuffer target", i); 776 continue; 777 } 778 779 if (layer.compositionType == HWC_BACKGROUND && !force_fb) { 780 ALOGV("\tlayer %u: background supported", i); 781 dump_layer(&contents->hwLayers[i]); 782 continue; 783 } 784 785 if (exynos5_supports_overlay(contents->hwLayers[i], i, pdev) && 786 !force_fb) { 787 ALOGV("\tlayer %u: overlay supported", i); 788 layer.compositionType = HWC_OVERLAY; 789 dump_layer(&contents->hwLayers[i]); 790 continue; 791 } 792 793 if (!fb_needed) { 794 first_fb = i; 795 fb_needed = true; 796 } 797 last_fb = i; 798 layer.compositionType = HWC_FRAMEBUFFER; 799 800 dump_layer(&contents->hwLayers[i]); 801 } 802 803 // can't composite overlays sandwiched between framebuffers 804 if (fb_needed) 805 for (size_t i = first_fb; i < last_fb; i++) 806 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 807 808 // Incrementally try to add our supported layers to hardware windows. 809 // If adding a layer would violate a hardware constraint, force it 810 // into the framebuffer and try again. (Revisiting the entire list is 811 // necessary because adding a layer to the framebuffer can cause other 812 // windows to retroactively violate constraints.) 813 bool changed; 814 bool gsc_used; 815 do { 816 android::Vector<hwc_rect> rects; 817 android::Vector<hwc_rect> overlaps; 818 size_t pixels_left, windows_left; 819 820 gsc_used = false; 821 822 if (fb_needed) { 823 hwc_rect_t fb_rect; 824 fb_rect.top = fb_rect.left = 0; 825 fb_rect.right = pdev->xres - 1; 826 fb_rect.bottom = pdev->yres - 1; 827 pixels_left = MAX_PIXELS - pdev->xres * pdev->yres; 828 windows_left = NUM_HW_WINDOWS - 1; 829 rects.push_back(fb_rect); 830 } 831 else { 832 pixels_left = MAX_PIXELS; 833 windows_left = NUM_HW_WINDOWS; 834 } 835 836 changed = false; 837 838 for (size_t i = 0; i < contents->numHwLayers; i++) { 839 hwc_layer_1_t &layer = contents->hwLayers[i]; 840 if ((layer.flags & HWC_SKIP_LAYER) || 841 layer.compositionType == HWC_FRAMEBUFFER_TARGET) 842 continue; 843 844 private_handle_t *handle = private_handle_t::dynamicCast( 845 layer.handle); 846 847 // we've already accounted for the framebuffer above 848 if (layer.compositionType == HWC_FRAMEBUFFER) 849 continue; 850 851 // only layer 0 can be HWC_BACKGROUND, so we can 852 // unconditionally allow it without extra checks 853 if (layer.compositionType == HWC_BACKGROUND) { 854 windows_left--; 855 continue; 856 } 857 858 size_t pixels_needed = WIDTH(layer.displayFrame) * 859 HEIGHT(layer.displayFrame); 860 bool can_compose = windows_left && pixels_needed <= pixels_left; 861 bool gsc_required = exynos5_requires_gscaler(layer, handle->format); 862 if (gsc_required) 863 can_compose = can_compose && !gsc_used; 864 865 // hwc_rect_t right and bottom values are normally exclusive; 866 // the intersection logic is simpler if we make them inclusive 867 hwc_rect_t visible_rect = layer.displayFrame; 868 visible_rect.right--; visible_rect.bottom--; 869 870 // no more than 2 layers can overlap on a given pixel 871 for (size_t j = 0; can_compose && j < overlaps.size(); j++) { 872 if (intersect(visible_rect, overlaps.itemAt(j))) 873 can_compose = false; 874 } 875 876 if (!can_compose) { 877 layer.compositionType = HWC_FRAMEBUFFER; 878 if (!fb_needed) { 879 first_fb = last_fb = i; 880 fb_needed = true; 881 } 882 else { 883 first_fb = min(i, first_fb); 884 last_fb = max(i, last_fb); 885 } 886 changed = true; 887 break; 888 } 889 890 for (size_t j = 0; j < rects.size(); j++) { 891 const hwc_rect_t &other_rect = rects.itemAt(j); 892 if (intersect(visible_rect, other_rect)) 893 overlaps.push_back(intersection(visible_rect, other_rect)); 894 } 895 rects.push_back(visible_rect); 896 pixels_left -= pixels_needed; 897 windows_left--; 898 if (gsc_required) 899 gsc_used = true; 900 } 901 902 if (changed) 903 for (size_t i = first_fb; i < last_fb; i++) 904 contents->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 905 } while(changed); 906 907 unsigned int nextWindow = 0; 908 909 for (size_t i = 0; i < contents->numHwLayers; i++) { 910 hwc_layer_1_t &layer = contents->hwLayers[i]; 911 912 if (fb_needed && i == first_fb) { 913 ALOGV("assigning framebuffer to window %u\n", 914 nextWindow); 915 nextWindow++; 916 continue; 917 } 918 919 if (layer.compositionType != HWC_FRAMEBUFFER && 920 layer.compositionType != HWC_FRAMEBUFFER_TARGET) { 921 ALOGV("assigning layer %u to window %u", i, nextWindow); 922 pdev->bufs.overlay_map[nextWindow] = i; 923 if (layer.compositionType == HWC_OVERLAY) { 924 private_handle_t *handle = 925 private_handle_t::dynamicCast(layer.handle); 926 if (exynos5_requires_gscaler(layer, handle->format)) { 927 ALOGV("\tusing gscaler %u", AVAILABLE_GSC_UNITS[FIMD_GSC_IDX]); 928 pdev->bufs.gsc_map[nextWindow].mode = 929 exynos5_gsc_map_t::GSC_M2M; 930 pdev->bufs.gsc_map[nextWindow].idx = FIMD_GSC_IDX; 931 } 932 } 933 nextWindow++; 934 } 935 } 936 937 if (!gsc_used) 938 exynos5_cleanup_gsc_m2m(pdev, FIMD_GSC_IDX); 939 940 if (fb_needed) 941 pdev->bufs.fb_window = first_fb; 942 else 943 pdev->bufs.fb_window = NO_FB_NEEDED; 944 945 return 0; 946} 947 948static int exynos5_prepare_hdmi(exynos5_hwc_composer_device_1_t *pdev, 949 hwc_display_contents_1_t* contents) 950{ 951 ALOGV("preparing %u layers for HDMI", contents->numHwLayers); 952 hwc_layer_1_t *video_layer = NULL; 953 954 for (size_t i = 0; i < contents->numHwLayers; i++) { 955 hwc_layer_1_t &layer = contents->hwLayers[i]; 956 957 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 958 ALOGV("\tlayer %u: framebuffer target", i); 959 continue; 960 } 961 962 if (layer.compositionType == HWC_BACKGROUND) { 963 ALOGV("\tlayer %u: background layer", i); 964 dump_layer(&layer); 965 continue; 966 } 967 968 if (layer.handle) { 969 private_handle_t *h = private_handle_t::dynamicCast(layer.handle); 970 if (h->flags & GRALLOC_USAGE_PROTECTED) { 971 if (!video_layer) { 972 video_layer = &layer; 973 layer.compositionType = HWC_OVERLAY; 974 ALOGV("\tlayer %u: video layer", i); 975 dump_layer(&layer); 976 continue; 977 } 978 } 979 } 980 981 layer.compositionType = HWC_FRAMEBUFFER; 982 dump_layer(&layer); 983 } 984 985 return 0; 986} 987 988static int exynos5_prepare(hwc_composer_device_1_t *dev, 989 size_t numDisplays, hwc_display_contents_1_t** displays) 990{ 991 if (!numDisplays || !displays) 992 return 0; 993 994 exynos5_hwc_composer_device_1_t *pdev = 995 (exynos5_hwc_composer_device_1_t *)dev; 996 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 997 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 998 999 if (pdev->hdmi_hpd) { 1000 hdmi_enable(pdev); 1001 } else { 1002 hdmi_disable(pdev); 1003 } 1004 1005 if (fimd_contents) { 1006 int err = exynos5_prepare_fimd(pdev, fimd_contents); 1007 if (err) 1008 return err; 1009 } 1010 1011 if (hdmi_contents) { 1012 int err = exynos5_prepare_hdmi(pdev, hdmi_contents); 1013 if (err) 1014 return err; 1015 } 1016 1017 return 0; 1018} 1019 1020static int exynos5_config_gsc_m2m(hwc_layer_1_t &layer, 1021 alloc_device_t* alloc_device, exynos5_gsc_data_t *gsc_data, 1022 int gsc_idx, int dst_format) 1023{ 1024 ALOGV("configuring gscaler %u for memory-to-memory", AVAILABLE_GSC_UNITS[gsc_idx]); 1025 1026 private_handle_t *src_handle = private_handle_t::dynamicCast(layer.handle); 1027 buffer_handle_t dst_buf; 1028 private_handle_t *dst_handle; 1029 int ret = 0; 1030 1031 if (layer.acquireFenceFd != -1) { 1032 int err = sync_wait(layer.acquireFenceFd, 100); 1033 if (err != 0) 1034 ALOGW("fence didn't signal in 100 ms: %s", strerror(errno)); 1035 close(layer.acquireFenceFd); 1036 layer.acquireFenceFd = -1; 1037 } 1038 1039 exynos_gsc_img src_cfg, dst_cfg; 1040 memset(&src_cfg, 0, sizeof(src_cfg)); 1041 memset(&dst_cfg, 0, sizeof(dst_cfg)); 1042 1043 src_cfg.x = layer.sourceCrop.left; 1044 src_cfg.y = layer.sourceCrop.top; 1045 src_cfg.w = WIDTH(layer.sourceCrop); 1046 src_cfg.fw = src_handle->stride; 1047 src_cfg.h = HEIGHT(layer.sourceCrop); 1048 src_cfg.fh = src_handle->vstride; 1049 src_cfg.yaddr = src_handle->fd; 1050 if (exynos5_format_is_ycrcb(src_handle->format)) { 1051 src_cfg.uaddr = src_handle->fd2; 1052 src_cfg.vaddr = src_handle->fd1; 1053 } else { 1054 src_cfg.uaddr = src_handle->fd1; 1055 src_cfg.vaddr = src_handle->fd2; 1056 } 1057 src_cfg.format = src_handle->format; 1058 src_cfg.drmMode = !!(src_handle->flags & GRALLOC_USAGE_PROTECTED); 1059 1060 dst_cfg.x = 0; 1061 dst_cfg.y = 0; 1062 dst_cfg.w = WIDTH(layer.displayFrame); 1063 dst_cfg.h = HEIGHT(layer.displayFrame); 1064 dst_cfg.rot = layer.transform; 1065 dst_cfg.drmMode = src_cfg.drmMode; 1066 dst_cfg.format = dst_format; 1067 1068 ALOGV("source configuration:"); 1069 dump_gsc_img(src_cfg); 1070 1071 bool reconfigure = gsc_src_cfg_changed(src_cfg, gsc_data->src_cfg) || 1072 gsc_dst_cfg_changed(dst_cfg, gsc_data->dst_cfg); 1073 if (reconfigure) { 1074 int dst_stride; 1075 int usage = GRALLOC_USAGE_SW_READ_NEVER | 1076 GRALLOC_USAGE_SW_WRITE_NEVER | 1077 GRALLOC_USAGE_HW_COMPOSER; 1078 1079 if (src_handle->flags & GRALLOC_USAGE_PROTECTED) 1080 usage |= GRALLOC_USAGE_PROTECTED; 1081 1082 int w = ALIGN(WIDTH(layer.displayFrame), GSC_W_ALIGNMENT); 1083 int h = ALIGN(HEIGHT(layer.displayFrame), GSC_H_ALIGNMENT); 1084 1085 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1086 if (gsc_data->dst_buf[i]) { 1087 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1088 gsc_data->dst_buf[i] = NULL; 1089 } 1090 1091 int ret = alloc_device->alloc(alloc_device, w, h, 1092 HAL_PIXEL_FORMAT_RGBX_8888, usage, &gsc_data->dst_buf[i], 1093 &dst_stride); 1094 if (ret < 0) { 1095 ALOGE("failed to allocate destination buffer: %s", 1096 strerror(-ret)); 1097 goto err_alloc; 1098 } 1099 } 1100 1101 gsc_data->current_buf = 0; 1102 } 1103 1104 dst_buf = gsc_data->dst_buf[gsc_data->current_buf]; 1105 dst_handle = private_handle_t::dynamicCast(dst_buf); 1106 1107 dst_cfg.fw = dst_handle->stride; 1108 dst_cfg.fh = dst_handle->vstride; 1109 dst_cfg.yaddr = dst_handle->fd; 1110 1111 ALOGV("destination configuration:"); 1112 dump_gsc_img(dst_cfg); 1113 1114 if (gsc_data->gsc) { 1115 ALOGV("reusing open gscaler %u", AVAILABLE_GSC_UNITS[gsc_idx]); 1116 } else { 1117 ALOGV("opening gscaler %u", AVAILABLE_GSC_UNITS[gsc_idx]); 1118 gsc_data->gsc = exynos_gsc_create_exclusive( 1119 AVAILABLE_GSC_UNITS[gsc_idx], GSC_M2M_MODE, GSC_DUMMY); 1120 if (!gsc_data->gsc) { 1121 ALOGE("failed to create gscaler handle"); 1122 ret = -1; 1123 goto err_alloc; 1124 } 1125 } 1126 1127 if (reconfigure) { 1128 ret = exynos_gsc_config_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1129 if (ret < 0) { 1130 ALOGE("failed to configure gscaler %u", gsc_idx); 1131 goto err_gsc_config; 1132 } 1133 } 1134 1135 ret = exynos_gsc_run_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1136 if (ret < 0) { 1137 ALOGE("failed to run gscaler %u", gsc_idx); 1138 goto err_gsc_config; 1139 } 1140 1141 ret = exynos_gsc_wait_frame_done_exclusive(gsc_data->gsc); 1142 if (ret < 0) { 1143 ALOGE("failed to wait for gscaler %u", gsc_idx); 1144 goto err_gsc_config; 1145 } 1146 1147 gsc_data->src_cfg = src_cfg; 1148 gsc_data->dst_cfg = dst_cfg; 1149 1150 return 0; 1151 1152err_gsc_config: 1153 exynos_gsc_destroy(gsc_data->gsc); 1154 gsc_data->gsc = NULL; 1155err_alloc: 1156 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1157 if (gsc_data->dst_buf[i]) { 1158 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1159 gsc_data->dst_buf[i] = NULL; 1160 } 1161 } 1162 memset(&gsc_data->src_cfg, 0, sizeof(gsc_data->src_cfg)); 1163 memset(&gsc_data->dst_cfg, 0, sizeof(gsc_data->dst_cfg)); 1164 return ret; 1165} 1166 1167 1168static void exynos5_cleanup_gsc_m2m(exynos5_hwc_composer_device_1_t *pdev, 1169 size_t gsc_idx) 1170{ 1171 exynos5_gsc_data_t &gsc_data = pdev->gsc[gsc_idx]; 1172 if (!gsc_data.gsc) 1173 return; 1174 1175 ALOGV("closing gscaler %u", AVAILABLE_GSC_UNITS[gsc_idx]); 1176 1177 exynos_gsc_stop_exclusive(gsc_data.gsc); 1178 exynos_gsc_destroy(gsc_data.gsc); 1179 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) 1180 if (gsc_data.dst_buf[i]) 1181 pdev->alloc_device->free(pdev->alloc_device, gsc_data.dst_buf[i]); 1182 1183 memset(&gsc_data, 0, sizeof(gsc_data)); 1184} 1185 1186static void exynos5_config_handle(private_handle_t *handle, 1187 hwc_rect_t &sourceCrop, hwc_rect_t &displayFrame, 1188 int32_t blending, int fence_fd, s3c_fb_win_config &cfg, 1189 exynos5_hwc_composer_device_1_t *pdev) 1190{ 1191 uint32_t x, y; 1192 uint32_t w = WIDTH(displayFrame); 1193 uint32_t h = HEIGHT(displayFrame); 1194 uint8_t bpp = exynos5_format_to_bpp(handle->format); 1195 uint32_t offset = (sourceCrop.top * handle->stride + sourceCrop.left) * bpp / 8; 1196 1197 if (displayFrame.left < 0) { 1198 unsigned int crop = -displayFrame.left; 1199 ALOGV("layer off left side of screen; cropping %u pixels from left edge", 1200 crop); 1201 x = 0; 1202 w -= crop; 1203 offset += crop * bpp / 8; 1204 } else { 1205 x = displayFrame.left; 1206 } 1207 1208 if (displayFrame.right > pdev->xres) { 1209 unsigned int crop = displayFrame.right - pdev->xres; 1210 ALOGV("layer off right side of screen; cropping %u pixels from right edge", 1211 crop); 1212 w -= crop; 1213 } 1214 1215 if (displayFrame.top < 0) { 1216 unsigned int crop = -displayFrame.top; 1217 ALOGV("layer off top side of screen; cropping %u pixels from top edge", 1218 crop); 1219 y = 0; 1220 h -= crop; 1221 offset += handle->stride * crop * bpp / 8; 1222 } else { 1223 y = displayFrame.top; 1224 } 1225 1226 if (displayFrame.bottom > pdev->yres) { 1227 int crop = displayFrame.bottom - pdev->yres; 1228 ALOGV("layer off bottom side of screen; cropping %u pixels from bottom edge", 1229 crop); 1230 h -= crop; 1231 } 1232 1233 cfg.state = cfg.S3C_FB_WIN_STATE_BUFFER; 1234 cfg.fd = handle->fd; 1235 cfg.x = x; 1236 cfg.y = y; 1237 cfg.w = w; 1238 cfg.h = h; 1239 cfg.format = exynos5_format_to_s3c_format(handle->format); 1240 cfg.offset = offset; 1241 cfg.stride = handle->stride * bpp / 8; 1242 cfg.blending = exynos5_blending_to_s3c_blending(blending); 1243 cfg.fence_fd = fence_fd; 1244} 1245 1246static void exynos5_config_overlay(hwc_layer_1_t *layer, s3c_fb_win_config &cfg, 1247 exynos5_hwc_composer_device_1_t *pdev) 1248{ 1249 if (layer->compositionType == HWC_BACKGROUND) { 1250 hwc_color_t color = layer->backgroundColor; 1251 cfg.state = cfg.S3C_FB_WIN_STATE_COLOR; 1252 cfg.color = (color.r << 16) | (color.g << 8) | color.b; 1253 cfg.x = 0; 1254 cfg.y = 0; 1255 cfg.w = pdev->xres; 1256 cfg.h = pdev->yres; 1257 return; 1258 } 1259 1260 private_handle_t *handle = private_handle_t::dynamicCast(layer->handle); 1261 exynos5_config_handle(handle, layer->sourceCrop, layer->displayFrame, 1262 layer->blending, layer->acquireFenceFd, cfg, pdev); 1263} 1264 1265static int exynos5_post_fimd(exynos5_hwc_composer_device_1_t *pdev, 1266 hwc_display_contents_1_t* contents) 1267{ 1268 exynos5_hwc_post_data_t *pdata = &pdev->bufs; 1269 struct s3c_fb_win_config_data win_data; 1270 struct s3c_fb_win_config *config = win_data.config; 1271 1272 memset(config, 0, sizeof(win_data.config)); 1273 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 1274 config[i].fence_fd = -1; 1275 1276 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1277 int layer_idx = pdata->overlay_map[i]; 1278 if (layer_idx != -1) { 1279 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1280 private_handle_t *handle = 1281 private_handle_t::dynamicCast(layer.handle); 1282 1283 if (pdata->gsc_map[i].mode == exynos5_gsc_map_t::GSC_M2M) { 1284 int gsc_idx = pdata->gsc_map[i].idx; 1285 exynos5_gsc_data_t &gsc = pdev->gsc[gsc_idx]; 1286 1287 // RGBX8888 surfaces are already in the right color order from the GPU, 1288 // RGB565 and YUV surfaces need the Gscaler to swap R & B 1289 int dst_format = HAL_PIXEL_FORMAT_BGRA_8888; 1290 if (exynos5_format_is_rgb(handle->format) && 1291 handle->format != HAL_PIXEL_FORMAT_RGB_565) 1292 dst_format = HAL_PIXEL_FORMAT_RGBX_8888; 1293 1294 int err = exynos5_config_gsc_m2m(layer, pdev->alloc_device, &gsc, 1295 gsc_idx, dst_format); 1296 if (err < 0) { 1297 ALOGE("failed to configure gscaler %u for layer %u", 1298 gsc_idx, i); 1299 continue; 1300 } 1301 1302 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf]; 1303 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS; 1304 private_handle_t *dst_handle = 1305 private_handle_t::dynamicCast(dst_buf); 1306 hwc_rect_t sourceCrop = { 0, 0, 1307 WIDTH(layer.displayFrame), HEIGHT(layer.displayFrame) }; 1308 exynos5_config_handle(dst_handle, sourceCrop, 1309 layer.displayFrame, layer.blending, -1, config[i], 1310 pdev); 1311 } else { 1312 exynos5_config_overlay(&layer, config[i], pdev); 1313 } 1314 } 1315 if (i == 0 && config[i].blending != S3C_FB_BLENDING_NONE) { 1316 ALOGV("blending not supported on window 0; forcing BLENDING_NONE"); 1317 config[i].blending = S3C_FB_BLENDING_NONE; 1318 } 1319 1320 ALOGV("window %u configuration:", i); 1321 dump_config(config[i]); 1322 } 1323 1324 int ret = ioctl(pdev->fd, S3CFB_WIN_CONFIG, &win_data); 1325 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 1326 if (config[i].fence_fd != -1) 1327 close(config[i].fence_fd); 1328 if (ret < 0) { 1329 ALOGE("ioctl S3CFB_WIN_CONFIG failed: %s", strerror(errno)); 1330 return ret; 1331 } 1332 1333 memcpy(pdev->last_config, &win_data.config, sizeof(win_data.config)); 1334 memcpy(pdev->last_gsc_map, pdata->gsc_map, sizeof(pdata->gsc_map)); 1335 pdev->last_fb_window = pdata->fb_window; 1336 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1337 int layer_idx = pdata->overlay_map[i]; 1338 if (layer_idx != -1) { 1339 hwc_layer_1_t &layer = contents->hwLayers[layer_idx]; 1340 pdev->last_handles[i] = layer.handle; 1341 } 1342 } 1343 1344 return win_data.fence; 1345} 1346 1347static int exynos5_set_fimd(exynos5_hwc_composer_device_1_t *pdev, 1348 hwc_display_contents_1_t* contents) 1349{ 1350 if (!contents->dpy || !contents->sur) 1351 return 0; 1352 1353 hwc_layer_1_t *fb_layer = NULL; 1354 1355 if (pdev->bufs.fb_window != NO_FB_NEEDED) { 1356 for (size_t i = 0; i < contents->numHwLayers; i++) { 1357 if (contents->hwLayers[i].compositionType == 1358 HWC_FRAMEBUFFER_TARGET) { 1359 pdev->bufs.overlay_map[pdev->bufs.fb_window] = i; 1360 fb_layer = &contents->hwLayers[i]; 1361 break; 1362 } 1363 } 1364 1365 if (CC_UNLIKELY(!fb_layer)) { 1366 ALOGE("framebuffer target expected, but not provided"); 1367 return -EINVAL; 1368 } 1369 1370 ALOGV("framebuffer target buffer:"); 1371 dump_layer(fb_layer); 1372 } 1373 1374 int fence = exynos5_post_fimd(pdev, contents); 1375 if (fence < 0) 1376 return fence; 1377 1378 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1379 if (pdev->bufs.overlay_map[i] != -1) { 1380 hwc_layer_1_t &layer = 1381 contents->hwLayers[pdev->bufs.overlay_map[i]]; 1382 int dup_fd = dup(fence); 1383 if (dup_fd < 0) 1384 ALOGW("release fence dup failed: %s", strerror(errno)); 1385 layer.releaseFenceFd = dup_fd; 1386 } 1387 } 1388 close(fence); 1389 1390 return 0; 1391} 1392 1393static int exynos5_set_hdmi(exynos5_hwc_composer_device_1_t *pdev, 1394 hwc_display_contents_1_t* contents) 1395{ 1396 hwc_layer_1_t *fb_layer = NULL; 1397 hwc_layer_1_t *video_layer = NULL; 1398 1399 if (!pdev->hdmi_enabled) { 1400 for (size_t i = 0; i < contents->numHwLayers; i++) { 1401 hwc_layer_1_t &layer = contents->hwLayers[i]; 1402 if (layer.acquireFenceFd != -1) 1403 close(layer.acquireFenceFd); 1404 } 1405 return 0; 1406 } 1407 1408 for (size_t i = 0; i < contents->numHwLayers; i++) { 1409 hwc_layer_1_t &layer = contents->hwLayers[i]; 1410 1411 if (layer.flags & HWC_SKIP_LAYER) { 1412 ALOGV("HDMI skipping layer %d", i); 1413 continue; 1414 } 1415 1416 if (layer.compositionType == HWC_OVERLAY) { 1417 if (!layer.handle) 1418 continue; 1419 1420 ALOGV("HDMI video layer:"); 1421 dump_layer(&layer); 1422 1423 exynos5_gsc_data_t &gsc = pdev->gsc[HDMI_GSC_IDX]; 1424 exynos5_config_gsc_m2m(layer, pdev->alloc_device, &gsc, 1, 1425 HAL_PIXEL_FORMAT_RGBX_8888); 1426 1427 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf]; 1428 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS; 1429 private_handle_t *h = private_handle_t::dynamicCast(dst_buf); 1430 1431 hdmi_output(pdev, pdev->hdmi_layers[0], layer, h); 1432 video_layer = &layer; 1433 } 1434 1435 if (layer.compositionType == HWC_FRAMEBUFFER_TARGET) { 1436 if (!layer.handle) 1437 continue; 1438 1439 ALOGV("HDMI FB layer:"); 1440 dump_layer(&layer); 1441 1442 private_handle_t *h = private_handle_t::dynamicCast(layer.handle); 1443 hdmi_output(pdev, pdev->hdmi_layers[1], layer, h); 1444 fb_layer = &layer; 1445 } 1446 } 1447 1448 if (!video_layer) { 1449 hdmi_disable_layer(pdev, pdev->hdmi_layers[0]); 1450 exynos5_cleanup_gsc_m2m(pdev, HDMI_GSC_IDX); 1451 } 1452 if (!fb_layer) 1453 hdmi_disable_layer(pdev, pdev->hdmi_layers[1]); 1454 1455 return 0; 1456} 1457 1458static int exynos5_set(struct hwc_composer_device_1 *dev, 1459 size_t numDisplays, hwc_display_contents_1_t** displays) 1460{ 1461 if (!numDisplays || !displays) 1462 return 0; 1463 1464 exynos5_hwc_composer_device_1_t *pdev = 1465 (exynos5_hwc_composer_device_1_t *)dev; 1466 hwc_display_contents_1_t *fimd_contents = displays[HWC_DISPLAY_PRIMARY]; 1467 hwc_display_contents_1_t *hdmi_contents = displays[HWC_DISPLAY_EXTERNAL]; 1468 1469 if (fimd_contents) { 1470 int err = exynos5_set_fimd(pdev, fimd_contents); 1471 if (err) 1472 return err; 1473 } 1474 1475 if (hdmi_contents) { 1476 int err = exynos5_set_hdmi(pdev, hdmi_contents); 1477 if (err) 1478 return err; 1479 } 1480 1481 return 0; 1482} 1483 1484static void exynos5_registerProcs(struct hwc_composer_device_1* dev, 1485 hwc_procs_t const* procs) 1486{ 1487 struct exynos5_hwc_composer_device_1_t* pdev = 1488 (struct exynos5_hwc_composer_device_1_t*)dev; 1489 pdev->procs = procs; 1490} 1491 1492static int exynos5_query(struct hwc_composer_device_1* dev, int what, int *value) 1493{ 1494 struct exynos5_hwc_composer_device_1_t *pdev = 1495 (struct exynos5_hwc_composer_device_1_t *)dev; 1496 1497 switch (what) { 1498 case HWC_BACKGROUND_LAYER_SUPPORTED: 1499 // we support the background layer 1500 value[0] = 1; 1501 break; 1502 case HWC_VSYNC_PERIOD: 1503 // vsync period in nanosecond 1504 value[0] = pdev->vsync_period; 1505 break; 1506 default: 1507 // unsupported query 1508 return -EINVAL; 1509 } 1510 return 0; 1511} 1512 1513static int exynos5_eventControl(struct hwc_composer_device_1 *dev, int dpy, 1514 int event, int enabled) 1515{ 1516 struct exynos5_hwc_composer_device_1_t *pdev = 1517 (struct exynos5_hwc_composer_device_1_t *)dev; 1518 1519 switch (event) { 1520 case HWC_EVENT_VSYNC: 1521 __u32 val = !!enabled; 1522 int err = ioctl(pdev->fd, S3CFB_SET_VSYNC_INT, &val); 1523 if (err < 0) { 1524 ALOGE("vsync ioctl failed"); 1525 return -errno; 1526 } 1527 1528 return 0; 1529 } 1530 1531 return -EINVAL; 1532} 1533 1534static void handle_hdmi_uevent(struct exynos5_hwc_composer_device_1_t *pdev, 1535 const char *buff, int len) 1536{ 1537 const char *s = buff; 1538 s += strlen(s) + 1; 1539 1540 while (*s) { 1541 if (!strncmp(s, "SWITCH_STATE=", strlen("SWITCH_STATE="))) 1542 pdev->hdmi_hpd = atoi(s + strlen("SWITCH_STATE=")) == 1; 1543 1544 s += strlen(s) + 1; 1545 if (s - buff >= len) 1546 break; 1547 } 1548 1549 if (pdev->hdmi_hpd) { 1550 if (hdmi_get_config(pdev)) { 1551 ALOGE("Error reading HDMI configuration"); 1552 pdev->hdmi_hpd = false; 1553 return; 1554 } 1555 } 1556 1557 ALOGV("HDMI HPD changed to %s", pdev->hdmi_hpd ? "enabled" : "disabled"); 1558 if (pdev->hdmi_hpd) 1559 ALOGI("HDMI Resolution changed to %dx%d", pdev->hdmi_h, pdev->hdmi_w); 1560 1561 /* hwc_dev->procs is set right after the device is opened, but there is 1562 * still a race condition where a hotplug event might occur after the open 1563 * but before the procs are registered. */ 1564 if (pdev->procs) 1565 pdev->procs->hotplug(pdev->procs, HWC_DISPLAY_EXTERNAL, pdev->hdmi_hpd); 1566} 1567 1568static void handle_vsync_event(struct exynos5_hwc_composer_device_1_t *pdev) 1569{ 1570 if (!pdev->procs) 1571 return; 1572 1573 int err = lseek(pdev->vsync_fd, 0, SEEK_SET); 1574 if (err < 0) { 1575 ALOGE("error seeking to vsync timestamp: %s", strerror(errno)); 1576 return; 1577 } 1578 1579 char buf[4096]; 1580 err = read(pdev->vsync_fd, buf, sizeof(buf)); 1581 if (err < 0) { 1582 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1583 return; 1584 } 1585 buf[sizeof(buf) - 1] = '\0'; 1586 1587 errno = 0; 1588 uint64_t timestamp = strtoull(buf, NULL, 0); 1589 if (!errno) 1590 pdev->procs->vsync(pdev->procs, 0, timestamp); 1591} 1592 1593static void *hwc_vsync_thread(void *data) 1594{ 1595 struct exynos5_hwc_composer_device_1_t *pdev = 1596 (struct exynos5_hwc_composer_device_1_t *)data; 1597 char uevent_desc[4096]; 1598 memset(uevent_desc, 0, sizeof(uevent_desc)); 1599 1600 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY); 1601 1602 uevent_init(); 1603 1604 char temp[4096]; 1605 int err = read(pdev->vsync_fd, temp, sizeof(temp)); 1606 if (err < 0) { 1607 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1608 return NULL; 1609 } 1610 1611 struct pollfd fds[2]; 1612 fds[0].fd = pdev->vsync_fd; 1613 fds[0].events = POLLPRI; 1614 fds[1].fd = uevent_get_fd(); 1615 fds[1].events = POLLIN; 1616 1617 while (true) { 1618 int err = poll(fds, 2, -1); 1619 1620 if (err > 0) { 1621 if (fds[0].revents & POLLPRI) { 1622 handle_vsync_event(pdev); 1623 } 1624 else if (fds[1].revents & POLLIN) { 1625 int len = uevent_next_event(uevent_desc, 1626 sizeof(uevent_desc) - 2); 1627 1628 bool hdmi = !strcmp(uevent_desc, 1629 "change@/devices/virtual/switch/hdmi"); 1630 if (hdmi) 1631 handle_hdmi_uevent(pdev, uevent_desc, len); 1632 } 1633 } 1634 else if (err == -1) { 1635 if (errno == EINTR) 1636 break; 1637 ALOGE("error in vsync thread: %s", strerror(errno)); 1638 } 1639 } 1640 1641 return NULL; 1642} 1643 1644static int exynos5_blank(struct hwc_composer_device_1 *dev, int dpy, int blank) 1645{ 1646 struct exynos5_hwc_composer_device_1_t *pdev = 1647 (struct exynos5_hwc_composer_device_1_t *)dev; 1648 1649 int fb_blank = blank ? FB_BLANK_POWERDOWN : FB_BLANK_UNBLANK; 1650 int err = ioctl(pdev->fd, FBIOBLANK, fb_blank); 1651 if (err < 0) { 1652 if (errno == EBUSY) 1653 ALOGI("%sblank ioctl failed (display already %sblanked)", 1654 blank ? "" : "un", blank ? "" : "un"); 1655 else 1656 ALOGE("%sblank ioctl failed: %s", blank ? "" : "un", 1657 strerror(errno)); 1658 return -errno; 1659 } 1660 1661 if (pdev->hdmi_hpd) { 1662 if (blank && !pdev->hdmi_blanked) 1663 hdmi_disable(pdev); 1664 pdev->hdmi_blanked = !!blank; 1665 } 1666 1667 return 0; 1668} 1669 1670static void exynos5_dump(hwc_composer_device_1* dev, char *buff, int buff_len) 1671{ 1672 if (buff_len <= 0) 1673 return; 1674 1675 struct exynos5_hwc_composer_device_1_t *pdev = 1676 (struct exynos5_hwc_composer_device_1_t *)dev; 1677 1678 android::String8 result; 1679 1680 result.appendFormat(" hdmi_enabled=%u\n", pdev->hdmi_enabled); 1681 if (pdev->hdmi_enabled) 1682 result.appendFormat(" w=%u, h=%u\n", pdev->hdmi_w, pdev->hdmi_h); 1683 result.append( 1684 " type | handle | color | blend | format | position | size | gsc \n" 1685 "----------+----------|----------+-------+--------+---------------+---------------------\n"); 1686 // 8_______ | 8_______ | 8_______ | 5____ | 6_____ | [5____,5____] | [5____,5____] | 3__ \n" 1687 1688 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1689 struct s3c_fb_win_config &config = pdev->last_config[i]; 1690 if (config.state == config.S3C_FB_WIN_STATE_DISABLED) { 1691 result.appendFormat(" %8s | %8s | %8s | %5s | %6s | %13s | %13s", 1692 "DISABLED", "-", "-", "-", "-", "-", "-"); 1693 } 1694 else { 1695 if (config.state == config.S3C_FB_WIN_STATE_COLOR) 1696 result.appendFormat(" %8s | %8s | %8x | %5s | %6s", "COLOR", 1697 "-", config.color, "-", "-"); 1698 else 1699 result.appendFormat(" %8s | %8x | %8s | %5x | %6x", 1700 pdev->last_fb_window == i ? "FB" : "OVERLAY", 1701 intptr_t(pdev->last_handles[i]), 1702 "-", config.blending, config.format); 1703 1704 result.appendFormat(" | [%5d,%5d] | [%5u,%5u]", config.x, config.y, 1705 config.w, config.h); 1706 } 1707 if (pdev->last_gsc_map[i].mode == exynos5_gsc_map_t::GSC_NONE) 1708 result.appendFormat(" | %3s", "-"); 1709 else 1710 result.appendFormat(" | %3d", 1711 AVAILABLE_GSC_UNITS[pdev->last_gsc_map[i].idx]); 1712 result.append("\n"); 1713 } 1714 1715 strlcpy(buff, result.string(), buff_len); 1716} 1717 1718static int exynos5_getDisplayConfigs(struct hwc_composer_device_1 *dev, 1719 int disp, uint32_t *configs, size_t *numConfigs) 1720{ 1721 struct exynos5_hwc_composer_device_1_t *pdev = 1722 (struct exynos5_hwc_composer_device_1_t *)dev; 1723 1724 if (*numConfigs == 0) 1725 return 0; 1726 1727 if (disp == HWC_DISPLAY_PRIMARY) { 1728 configs[0] = 0; 1729 *numConfigs = 1; 1730 return 0; 1731 } else if (disp == HWC_DISPLAY_EXTERNAL) { 1732 if (!pdev->hdmi_hpd) { 1733 return -EINVAL; 1734 } 1735 1736 int err = hdmi_get_config(pdev); 1737 if (err) { 1738 return -EINVAL; 1739 } 1740 1741 configs[0] = 0; 1742 *numConfigs = 1; 1743 return 0; 1744 } 1745 1746 return -EINVAL; 1747} 1748 1749static int32_t exynos5_fimd_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1750 const uint32_t attribute) 1751{ 1752 switch(attribute) { 1753 case HWC_DISPLAY_VSYNC_PERIOD: 1754 return pdev->vsync_period; 1755 1756 case HWC_DISPLAY_WIDTH: 1757 return pdev->xres; 1758 1759 case HWC_DISPLAY_HEIGHT: 1760 return pdev->yres; 1761 1762 case HWC_DISPLAY_DPI_X: 1763 return pdev->xdpi; 1764 1765 case HWC_DISPLAY_DPI_Y: 1766 return pdev->ydpi; 1767 1768 default: 1769 ALOGE("unknown display attribute %u", attribute); 1770 return -EINVAL; 1771 } 1772} 1773 1774static int32_t exynos5_hdmi_attribute(struct exynos5_hwc_composer_device_1_t *pdev, 1775 const uint32_t attribute) 1776{ 1777 switch(attribute) { 1778 case HWC_DISPLAY_VSYNC_PERIOD: 1779 return pdev->vsync_period; 1780 1781 case HWC_DISPLAY_WIDTH: 1782 return pdev->hdmi_w; 1783 1784 case HWC_DISPLAY_HEIGHT: 1785 return pdev->hdmi_h; 1786 1787 case HWC_DISPLAY_DPI_X: 1788 case HWC_DISPLAY_DPI_Y: 1789 return 0; // unknown 1790 1791 default: 1792 ALOGE("unknown display attribute %u", attribute); 1793 return -EINVAL; 1794 } 1795} 1796 1797static int exynos5_getDisplayAttributes(struct hwc_composer_device_1 *dev, 1798 int disp, uint32_t config, const uint32_t *attributes, int32_t *values) 1799{ 1800 struct exynos5_hwc_composer_device_1_t *pdev = 1801 (struct exynos5_hwc_composer_device_1_t *)dev; 1802 1803 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; i++) { 1804 if (disp == HWC_DISPLAY_PRIMARY) 1805 values[i] = exynos5_fimd_attribute(pdev, attributes[i]); 1806 else if (disp == HWC_DISPLAY_EXTERNAL) 1807 values[i] = exynos5_hdmi_attribute(pdev, attributes[i]); 1808 else { 1809 ALOGE("unknown display type %u", disp); 1810 return -EINVAL; 1811 } 1812 } 1813 1814 return 0; 1815} 1816 1817static int exynos5_close(hw_device_t* device); 1818 1819static int exynos5_open(const struct hw_module_t *module, const char *name, 1820 struct hw_device_t **device) 1821{ 1822 int ret; 1823 int refreshRate; 1824 int sw_fd; 1825 1826 if (strcmp(name, HWC_HARDWARE_COMPOSER)) { 1827 return -EINVAL; 1828 } 1829 1830 struct exynos5_hwc_composer_device_1_t *dev; 1831 dev = (struct exynos5_hwc_composer_device_1_t *)malloc(sizeof(*dev)); 1832 memset(dev, 0, sizeof(*dev)); 1833 1834 if (hw_get_module(GRALLOC_HARDWARE_MODULE_ID, 1835 (const struct hw_module_t **)&dev->gralloc_module)) { 1836 ALOGE("failed to get gralloc hw module"); 1837 ret = -EINVAL; 1838 goto err_get_module; 1839 } 1840 1841 if (gralloc_open((const hw_module_t *)dev->gralloc_module, 1842 &dev->alloc_device)) { 1843 ALOGE("failed to open gralloc"); 1844 ret = -EINVAL; 1845 goto err_get_module; 1846 } 1847 1848 dev->fd = open("/dev/graphics/fb0", O_RDWR); 1849 if (dev->fd < 0) { 1850 ALOGE("failed to open framebuffer"); 1851 ret = dev->fd; 1852 goto err_open_fb; 1853 } 1854 1855 struct fb_var_screeninfo info; 1856 if (ioctl(dev->fd, FBIOGET_VSCREENINFO, &info) == -1) { 1857 ALOGE("FBIOGET_VSCREENINFO ioctl failed: %s", strerror(errno)); 1858 ret = -errno; 1859 goto err_ioctl; 1860 } 1861 1862 refreshRate = 1000000000000LLU / 1863 ( 1864 uint64_t( info.upper_margin + info.lower_margin + info.yres ) 1865 * ( info.left_margin + info.right_margin + info.xres ) 1866 * info.pixclock 1867 ); 1868 1869 if (refreshRate == 0) { 1870 ALOGW("invalid refresh rate, assuming 60 Hz"); 1871 refreshRate = 60; 1872 } 1873 1874 dev->xres = 2560; 1875 dev->yres = 1600; 1876 dev->xdpi = 1000 * (info.xres * 25.4f) / info.width; 1877 dev->ydpi = 1000 * (info.yres * 25.4f) / info.height; 1878 dev->vsync_period = 1000000000 / refreshRate; 1879 1880 ALOGV("using\n" 1881 "xres = %d px\n" 1882 "yres = %d px\n" 1883 "width = %d mm (%f dpi)\n" 1884 "height = %d mm (%f dpi)\n" 1885 "refresh rate = %d Hz\n", 1886 dev->xres, dev->yres, info.width, dev->xdpi / 1000.0, 1887 info.height, dev->ydpi / 1000.0, refreshRate); 1888 1889 dev->hdmi_mixer0 = open("/dev/v4l-subdev7", O_RDWR); 1890 if (dev->hdmi_mixer0 < 0) { 1891 ALOGE("failed to open hdmi mixer0 subdev"); 1892 ret = dev->hdmi_mixer0; 1893 goto err_ioctl; 1894 } 1895 1896 dev->hdmi_layers[0].id = 0; 1897 dev->hdmi_layers[0].fd = open("/dev/video16", O_RDWR); 1898 if (dev->hdmi_layers[0].fd < 0) { 1899 ALOGE("failed to open hdmi layer0 device"); 1900 ret = dev->hdmi_layers[0].fd; 1901 goto err_mixer0; 1902 } 1903 1904 dev->hdmi_layers[1].id = 1; 1905 dev->hdmi_layers[1].fd = open("/dev/video17", O_RDWR); 1906 if (dev->hdmi_layers[1].fd < 0) { 1907 ALOGE("failed to open hdmi layer1 device"); 1908 ret = dev->hdmi_layers[1].fd; 1909 goto err_hdmi0; 1910 } 1911 1912 dev->vsync_fd = open("/sys/devices/platform/exynos5-fb.1/vsync", O_RDONLY); 1913 if (dev->vsync_fd < 0) { 1914 ALOGE("failed to open vsync attribute"); 1915 ret = dev->vsync_fd; 1916 goto err_hdmi1; 1917 } 1918 1919 sw_fd = open("/sys/class/switch/hdmi/state", O_RDONLY); 1920 if (sw_fd) { 1921 char val; 1922 if (read(sw_fd, &val, 1) == 1 && val == '1') { 1923 dev->hdmi_hpd = true; 1924 if (hdmi_get_config(dev)) { 1925 ALOGE("Error reading HDMI configuration"); 1926 dev->hdmi_hpd = false; 1927 } 1928 } 1929 } 1930 1931 dev->base.common.tag = HARDWARE_DEVICE_TAG; 1932 dev->base.common.version = HWC_DEVICE_API_VERSION_1_1; 1933 dev->base.common.module = const_cast<hw_module_t *>(module); 1934 dev->base.common.close = exynos5_close; 1935 1936 dev->base.prepare = exynos5_prepare; 1937 dev->base.set = exynos5_set; 1938 dev->base.eventControl = exynos5_eventControl; 1939 dev->base.blank = exynos5_blank; 1940 dev->base.query = exynos5_query; 1941 dev->base.registerProcs = exynos5_registerProcs; 1942 dev->base.dump = exynos5_dump; 1943 dev->base.getDisplayConfigs = exynos5_getDisplayConfigs; 1944 dev->base.getDisplayAttributes = exynos5_getDisplayAttributes; 1945 1946 *device = &dev->base.common; 1947 1948 ret = pthread_create(&dev->vsync_thread, NULL, hwc_vsync_thread, dev); 1949 if (ret) { 1950 ALOGE("failed to start vsync thread: %s", strerror(ret)); 1951 ret = -ret; 1952 goto err_vsync; 1953 } 1954 1955 char value[PROPERTY_VALUE_MAX]; 1956 property_get("debug.hwc.force_gpu", value, "0"); 1957 dev->force_gpu = atoi(value); 1958 1959 return 0; 1960 1961err_vsync: 1962 close(dev->vsync_fd); 1963err_mixer0: 1964 close(dev->hdmi_mixer0); 1965err_hdmi1: 1966 close(dev->hdmi_layers[0].fd); 1967err_hdmi0: 1968 close(dev->hdmi_layers[1].fd); 1969err_ioctl: 1970 close(dev->fd); 1971err_open_fb: 1972 gralloc_close(dev->alloc_device); 1973err_get_module: 1974 free(dev); 1975 return ret; 1976} 1977 1978static int exynos5_close(hw_device_t *device) 1979{ 1980 struct exynos5_hwc_composer_device_1_t *dev = 1981 (struct exynos5_hwc_composer_device_1_t *)device; 1982 pthread_kill(dev->vsync_thread, SIGTERM); 1983 pthread_join(dev->vsync_thread, NULL); 1984 for (size_t i = 0; i < NUM_GSC_UNITS; i++) 1985 exynos5_cleanup_gsc_m2m(dev, i); 1986 gralloc_close(dev->alloc_device); 1987 close(dev->vsync_fd); 1988 close(dev->hdmi_mixer0); 1989 close(dev->hdmi_layers[0].fd); 1990 close(dev->hdmi_layers[1].fd); 1991 close(dev->fd); 1992 return 0; 1993} 1994 1995static struct hw_module_methods_t exynos5_hwc_module_methods = { 1996 open: exynos5_open, 1997}; 1998 1999hwc_module_t HAL_MODULE_INFO_SYM = { 2000 common: { 2001 tag: HARDWARE_MODULE_TAG, 2002 module_api_version: HWC_MODULE_API_VERSION_0_1, 2003 hal_api_version: HARDWARE_HAL_API_VERSION, 2004 id: HWC_HARDWARE_MODULE_ID, 2005 name: "Samsung exynos5 hwcomposer module", 2006 author: "Google", 2007 methods: &exynos5_hwc_module_methods, 2008 } 2009}; 2010