hwc.cpp revision f3416d3fd62de43b5f15076957d94282e13b30ba
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16#include <errno.h> 17#include <fcntl.h> 18#include <poll.h> 19#include <pthread.h> 20#include <stdio.h> 21#include <stdlib.h> 22 23#include <sys/ioctl.h> 24#include <sys/mman.h> 25#include <sys/time.h> 26#include <sys/resource.h> 27 28#include <s3c-fb.h> 29 30#include <EGL/egl.h> 31 32#define HWC_REMOVE_DEPRECATED_VERSIONS 1 33 34#include <cutils/log.h> 35#include <hardware/gralloc.h> 36#include <hardware/hardware.h> 37#include <hardware/hwcomposer.h> 38#include <hardware_legacy/uevent.h> 39#include <utils/String8.h> 40#include <utils/Vector.h> 41 42#include <sync/sync.h> 43 44#include "ion.h" 45#include "gralloc_priv.h" 46#include "exynos_gscaler.h" 47#include "exynos_format.h" 48#include "exynos_v4l2.h" 49#include "s5p_tvout_v4l2.h" 50 51struct hwc_callback_entry { 52 void (*callback)(void *, private_handle_t *); 53 void *data; 54}; 55typedef android::Vector<struct hwc_callback_entry> hwc_callback_queue_t; 56 57const size_t NUM_HW_WINDOWS = 5; 58const size_t NO_FB_NEEDED = NUM_HW_WINDOWS + 1; 59const size_t MAX_PIXELS = 2560 * 1600 * 2; 60const size_t GSC_W_ALIGNMENT = 16; 61const size_t GSC_H_ALIGNMENT = 16; 62const int AVAILABLE_GSC_UNITS[] = { 0, 3 }; 63const size_t NUM_GSC_UNITS = sizeof(AVAILABLE_GSC_UNITS) / 64 sizeof(AVAILABLE_GSC_UNITS[0]); 65 66struct exynos5_hwc_composer_device_1_t; 67 68struct exynos5_gsc_map_t { 69 enum { 70 GSC_NONE = 0, 71 GSC_M2M, 72 // TODO: GSC_LOCAL_PATH 73 } mode; 74 int idx; 75}; 76 77struct exynos5_hwc_post_data_t { 78 exynos5_hwc_composer_device_1_t *pdev; 79 int overlay_map[NUM_HW_WINDOWS]; 80 exynos5_gsc_map_t gsc_map[NUM_HW_WINDOWS]; 81 hwc_layer_1_t overlays[NUM_HW_WINDOWS]; 82 int num_overlays; 83 size_t fb_window; 84 int fence; 85 pthread_mutex_t completion_lock; 86 pthread_cond_t completion; 87}; 88 89const size_t NUM_GSC_DST_BUFS = 2; 90struct exynos5_gsc_data_t { 91 void *gsc; 92 exynos_gsc_img src_cfg; 93 exynos_gsc_img dst_cfg; 94 buffer_handle_t dst_buf[NUM_GSC_DST_BUFS]; 95 size_t current_buf; 96}; 97 98struct exynos5_hwc_composer_device_1_t { 99 hwc_composer_device_1_t base; 100 101 int fd; 102 int vsync_fd; 103 exynos5_hwc_post_data_t bufs; 104 105 const private_module_t *gralloc_module; 106 alloc_device_t *alloc_device; 107 const hwc_procs_t *procs; 108 pthread_t vsync_thread; 109 110 int hdmi_mixer0; 111 int hdmi_layer0; 112 int hdmi_layer1; 113 bool hdmi_hpd; 114 bool hdmi_enabled; 115 bool hdmi_blanked; 116 void *hdmi_gsc; 117 int hdmi_w; 118 int hdmi_h; 119 exynos_gsc_img hdmi_src; 120 exynos_gsc_img hdmi_dst; 121 122 exynos5_gsc_data_t gsc[NUM_GSC_UNITS]; 123 124 struct s3c_fb_win_config last_config[NUM_HW_WINDOWS]; 125 const void *last_handles[NUM_HW_WINDOWS]; 126 exynos5_gsc_map_t last_gsc_map[NUM_HW_WINDOWS]; 127}; 128 129static void dump_handle(private_handle_t *h) 130{ 131 ALOGV("\t\tformat = %d, width = %u, height = %u, stride = %u, vstride = %u", 132 h->format, h->width, h->height, h->stride, h->vstride); 133} 134 135static void dump_layer(hwc_layer_1_t const *l) 136{ 137 ALOGV("\ttype=%d, flags=%08x, handle=%p, tr=%02x, blend=%04x, " 138 "{%d,%d,%d,%d}, {%d,%d,%d,%d}", 139 l->compositionType, l->flags, l->handle, l->transform, 140 l->blending, 141 l->sourceCrop.left, 142 l->sourceCrop.top, 143 l->sourceCrop.right, 144 l->sourceCrop.bottom, 145 l->displayFrame.left, 146 l->displayFrame.top, 147 l->displayFrame.right, 148 l->displayFrame.bottom); 149 150 if(l->handle && !(l->flags & HWC_SKIP_LAYER)) 151 dump_handle(private_handle_t::dynamicCast(l->handle)); 152} 153 154static void dump_config(s3c_fb_win_config &c) 155{ 156 ALOGV("\tstate = %u", c.state); 157 if (c.state == c.S3C_FB_WIN_STATE_BUFFER) { 158 ALOGV("\t\tfd = %d, offset = %u, stride = %u, " 159 "x = %d, y = %d, w = %u, h = %u, " 160 "format = %u, blending = %u", 161 c.fd, c.offset, c.stride, 162 c.x, c.y, c.w, c.h, 163 c.format, c.blending); 164 } 165 else if (c.state == c.S3C_FB_WIN_STATE_COLOR) { 166 ALOGV("\t\tcolor = %u", c.color); 167 } 168} 169 170static void dump_gsc_img(exynos_gsc_img &c) 171{ 172 ALOGV("\tx = %u, y = %u, w = %u, h = %u, fw = %u, fh = %u", 173 c.x, c.y, c.w, c.h, c.fw, c.fh); 174 ALOGV("\taddr = {%u, %u, %u}, rot = %u, cacheable = %u, drmMode = %u", 175 c.yaddr, c.uaddr, c.vaddr, c.rot, c.cacheable, c.drmMode); 176} 177 178inline int WIDTH(const hwc_rect &rect) { return rect.right - rect.left; } 179inline int HEIGHT(const hwc_rect &rect) { return rect.bottom - rect.top; } 180template<typename T> inline T max(T a, T b) { return (a > b) ? a : b; } 181template<typename T> inline T min(T a, T b) { return (a < b) ? a : b; } 182 183static bool is_transformed(const hwc_layer_1_t &layer) 184{ 185 return layer.transform != 0; 186} 187 188static bool is_rotated(const hwc_layer_1_t &layer) 189{ 190 return (layer.transform & HAL_TRANSFORM_ROT_90) || 191 (layer.transform & HAL_TRANSFORM_ROT_180); 192} 193 194static bool is_scaled(const hwc_layer_1_t &layer) 195{ 196 return WIDTH(layer.displayFrame) != WIDTH(layer.sourceCrop) || 197 HEIGHT(layer.displayFrame) != HEIGHT(layer.sourceCrop); 198} 199 200static inline bool gsc_dst_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 201{ 202 return c1.x != c2.x || 203 c1.y != c2.y || 204 c1.w != c2.w || 205 c1.h != c2.h || 206 c1.format != c2.format || 207 c1.rot != c2.rot || 208 c1.cacheable != c2.cacheable || 209 c1.drmMode != c2.drmMode; 210} 211 212static inline bool gsc_src_cfg_changed(exynos_gsc_img &c1, exynos_gsc_img &c2) 213{ 214 return gsc_dst_cfg_changed(c1, c2) || 215 c1.fw != c2.fw || 216 c1.fh != c2.fh; 217} 218 219static enum s3c_fb_pixel_format exynos5_format_to_s3c_format(int format) 220{ 221 switch (format) { 222 case HAL_PIXEL_FORMAT_RGBA_8888: 223 return S3C_FB_PIXEL_FORMAT_RGBA_8888; 224 case HAL_PIXEL_FORMAT_RGBX_8888: 225 return S3C_FB_PIXEL_FORMAT_RGBX_8888; 226 case HAL_PIXEL_FORMAT_RGBA_5551: 227 return S3C_FB_PIXEL_FORMAT_RGBA_5551; 228 229 default: 230 return S3C_FB_PIXEL_FORMAT_MAX; 231 } 232} 233 234static bool exynos5_format_is_supported(int format) 235{ 236 return exynos5_format_to_s3c_format(format) < S3C_FB_PIXEL_FORMAT_MAX; 237} 238 239static bool exynos5_format_is_rgb(int format) 240{ 241 switch (format) { 242 case HAL_PIXEL_FORMAT_RGBA_8888: 243 case HAL_PIXEL_FORMAT_RGBX_8888: 244 case HAL_PIXEL_FORMAT_RGB_888: 245 case HAL_PIXEL_FORMAT_RGB_565: 246 case HAL_PIXEL_FORMAT_BGRA_8888: 247 case HAL_PIXEL_FORMAT_RGBA_5551: 248 case HAL_PIXEL_FORMAT_RGBA_4444: 249 return true; 250 251 default: 252 return false; 253 } 254} 255 256static bool exynos5_format_is_supported_by_gscaler(int format) 257{ 258 switch (format) { 259 case HAL_PIXEL_FORMAT_RGBX_8888: 260 case HAL_PIXEL_FORMAT_RGB_565: 261 case HAL_PIXEL_FORMAT_EXYNOS_YV12: 262 case HAL_PIXEL_FORMAT_YCbCr_420_SP: 263 case HAL_PIXEL_FORMAT_YCbCr_420_SP_TILED: 264 return true; 265 266 default: 267 return false; 268 } 269} 270 271static bool exynos5_format_is_ycrcb(int format) 272{ 273 return format == HAL_PIXEL_FORMAT_EXYNOS_YV12; 274} 275 276static bool exynos5_format_requires_gscaler(int format) 277{ 278 return exynos5_format_is_supported_by_gscaler(format) && 279 format != HAL_PIXEL_FORMAT_RGBX_8888; 280} 281 282static uint8_t exynos5_format_to_bpp(int format) 283{ 284 switch (format) { 285 case HAL_PIXEL_FORMAT_RGBA_8888: 286 case HAL_PIXEL_FORMAT_RGBX_8888: 287 return 32; 288 289 case HAL_PIXEL_FORMAT_RGBA_5551: 290 case HAL_PIXEL_FORMAT_RGBA_4444: 291 return 16; 292 293 default: 294 ALOGW("unrecognized pixel format %u", format); 295 return 0; 296 } 297} 298 299static bool exynos5_supports_gscaler(hwc_layer_1_t &layer, int format, 300 bool local_path) 301{ 302 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 303 304 exynos_gsc_img src_cfg, dst_cfg; 305 src_cfg.x = layer.sourceCrop.left; 306 src_cfg.y = layer.sourceCrop.top; 307 src_cfg.w = WIDTH(layer.sourceCrop); 308 src_cfg.h = HEIGHT(layer.sourceCrop); 309 src_cfg.fw = handle->stride; 310 src_cfg.fh = handle->vstride; 311 src_cfg.format = format; 312 dst_cfg.x = 0; 313 dst_cfg.y = 0; 314 dst_cfg.w = WIDTH(layer.displayFrame); 315 dst_cfg.h = HEIGHT(layer.displayFrame); 316 dst_cfg.format = HAL_PIXEL_FORMAT_BGRA_8888; 317 dst_cfg.rot = layer.transform; 318 319 if (!exynos5_format_is_supported_by_gscaler(format)) 320 return false; 321 322 if (!exynos_gsc_cfg_valid(&src_cfg, &dst_cfg, local_path, false)) 323 return false; 324 325 if (exynos5_format_is_rgb(format) && 326 !exynos_gsc_cfg_aligned(&src_cfg, &dst_cfg)) 327 return false; 328 329 return true; 330} 331 332static bool exynos5_requires_gscaler(hwc_layer_1_t &layer, int format) 333{ 334 return exynos5_format_requires_gscaler(format) || 335 is_scaled(layer) || is_transformed(layer); 336} 337 338int hdmi_get_config(struct exynos5_hwc_composer_device_1_t *dev) 339{ 340 struct v4l2_dv_preset preset; 341 struct v4l2_dv_enum_preset enum_preset; 342 int index = 0; 343 bool found = false; 344 int ret; 345 346 if (ioctl(dev->hdmi_layer0, VIDIOC_G_DV_PRESET, &preset) < 0) { 347 ALOGE("%s: g_dv_preset error, %d", __func__, errno); 348 return -1; 349 } 350 351 while (true) { 352 enum_preset.index = index++; 353 ret = ioctl(dev->hdmi_layer0, VIDIOC_ENUM_DV_PRESETS, &enum_preset); 354 355 if (ret < 0) { 356 if (errno == EINVAL) 357 break; 358 ALOGE("%s: enum_dv_presets error, %d", __func__, errno); 359 return -1; 360 } 361 362 ALOGV("%s: %d preset=%02d width=%d height=%d name=%s", 363 __func__, enum_preset.index, enum_preset.preset, 364 enum_preset.width, enum_preset.height, enum_preset.name); 365 366 if (preset.preset == enum_preset.preset) { 367 dev->hdmi_w = enum_preset.width; 368 dev->hdmi_h = enum_preset.height; 369 found = true; 370 } 371 } 372 373 return found ? 0 : -1; 374} 375 376static enum s3c_fb_blending exynos5_blending_to_s3c_blending(int32_t blending) 377{ 378 switch (blending) { 379 case HWC_BLENDING_NONE: 380 return S3C_FB_BLENDING_NONE; 381 case HWC_BLENDING_PREMULT: 382 return S3C_FB_BLENDING_PREMULT; 383 case HWC_BLENDING_COVERAGE: 384 return S3C_FB_BLENDING_COVERAGE; 385 386 default: 387 return S3C_FB_BLENDING_MAX; 388 } 389} 390 391static bool exynos5_blending_is_supported(int32_t blending) 392{ 393 return exynos5_blending_to_s3c_blending(blending) < S3C_FB_BLENDING_MAX; 394} 395 396static int hdmi_start_background(struct exynos5_hwc_composer_device_1_t *dev) 397{ 398 struct v4l2_requestbuffers reqbuf; 399 struct v4l2_subdev_format sd_fmt; 400 struct v4l2_subdev_crop sd_crop; 401 struct v4l2_format fmt; 402 struct v4l2_buffer buffer; 403 struct v4l2_plane planes[1]; 404 405 memset(&reqbuf, 0, sizeof(reqbuf)); 406 memset(&sd_fmt, 0, sizeof(sd_fmt)); 407 memset(&sd_crop, 0, sizeof(sd_crop)); 408 memset(&fmt, 0, sizeof(fmt)); 409 memset(&buffer, 0, sizeof(buffer)); 410 memset(planes, 0, sizeof(planes)); 411 412 sd_fmt.pad = MIXER_G1_SUBDEV_PAD_SINK; 413 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 414 sd_fmt.format.width = 1; 415 sd_fmt.format.height = 1; 416 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 417 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 418 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 419 return -1; 420 } 421 422 sd_crop.pad = MIXER_G1_SUBDEV_PAD_SINK; 423 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 424 sd_crop.rect.left = 0; 425 sd_crop.rect.top = 0; 426 sd_crop.rect.width = 1; 427 sd_crop.rect.height = 1; 428 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 429 ALOGE("%s: set_crop failed pad=%d", __func__, sd_crop.pad); 430 return -1; 431 } 432 433 sd_fmt.pad = MIXER_G1_SUBDEV_PAD_SOURCE; 434 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 435 sd_fmt.format.width = dev->hdmi_w; 436 sd_fmt.format.height = dev->hdmi_h; 437 sd_fmt.format.code = V4L2_MBUS_FMT_XRGB8888_4X8_LE; 438 if (exynos_subdev_s_fmt(dev->hdmi_mixer0, &sd_fmt) < 0) { 439 ALOGE("%s: s_fmt failed pad=%d", __func__, sd_fmt.pad); 440 return -1; 441 } 442 443 sd_crop.pad = MIXER_G1_SUBDEV_PAD_SOURCE; 444 sd_crop.which = V4L2_SUBDEV_FORMAT_ACTIVE; 445 sd_crop.rect.left = 0; 446 sd_crop.rect.top = 0; 447 sd_crop.rect.width = 1; 448 sd_crop.rect.height = 1; 449 if (exynos_subdev_s_crop(dev->hdmi_mixer0, &sd_crop) < 0) { 450 ALOGE("%s: s_crop failed pad=%d", __func__, sd_crop.pad); 451 return -1; 452 } 453 454 fmt.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 455 fmt.fmt.pix_mp.width = 1; 456 fmt.fmt.pix_mp.height = 1; 457 fmt.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_BGR32; 458 fmt.fmt.pix_mp.field = V4L2_FIELD_ANY; 459 fmt.fmt.pix_mp.num_planes = 1; 460 if (exynos_v4l2_s_fmt(dev->hdmi_layer1, &fmt) < 0) { 461 ALOGE("%s::videodev set format failed", __func__); 462 return -1; 463 } 464 465 reqbuf.count = 1; 466 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 467 reqbuf.memory = V4L2_MEMORY_MMAP; 468 469 if (exynos_v4l2_reqbufs(dev->hdmi_layer1, &reqbuf) < 0) { 470 ALOGE("%s: exynos_v4l2_reqbufs failed %d", __func__, errno); 471 return -1; 472 } 473 474 if (reqbuf.count != 1) { 475 ALOGE("%s: didn't get buffer", __func__); 476 return -1; 477 } 478 479 memset(&buffer, 0, sizeof(buffer)); 480 buffer.type = reqbuf.type; 481 buffer.memory = V4L2_MEMORY_MMAP; 482 buffer.length = 1; 483 buffer.m.planes = planes; 484 if (exynos_v4l2_querybuf(dev->hdmi_layer1, &buffer) < 0) { 485 ALOGE("%s: exynos_v4l2_querybuf failed %d", __func__, errno); 486 return -1; 487 } 488 489 void *start = mmap(NULL, planes[0].length, PROT_READ | PROT_WRITE, 490 MAP_SHARED, dev->hdmi_layer1, planes[0].m.mem_offset); 491 if (start == MAP_FAILED) { 492 ALOGE("%s: mmap failed %d", __func__, errno); 493 return -1; 494 } 495 496 memset(start, 0, planes[0].length); 497 498 munmap(start, planes[0].length); 499 500 if (exynos_v4l2_qbuf(dev->hdmi_layer1, &buffer) < 0) { 501 ALOGE("%s: exynos_v4l2_qbuf failed %d", __func__, errno); 502 return -1; 503 } 504 505 if (exynos_v4l2_streamon(dev->hdmi_layer1, buffer.type) < 0) { 506 ALOGE("%s:stream on failed", __func__); 507 return -1; 508 } 509 510 if (exynos_v4l2_s_ctrl(dev->hdmi_layer1, V4L2_CID_TV_LAYER_PRIO, 0) < 0) { 511 ALOGE("%s: s_ctrl LAYER_PRIO failed", __func__); 512 return -1; 513 } 514 515 return 0; 516} 517 518static int hdmi_stop_background(struct exynos5_hwc_composer_device_1_t *dev) 519{ 520 struct v4l2_requestbuffers reqbuf; 521 522 if (exynos_v4l2_streamoff(dev->hdmi_layer1, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) < 0) { 523 ALOGE("%s:stream off failed", __func__); 524 return -1; 525 } 526 527 memset(&reqbuf, 0, sizeof(reqbuf)); 528 reqbuf.count = 0; 529 reqbuf.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 530 reqbuf.memory = V4L2_MEMORY_MMAP; 531 if (exynos_v4l2_reqbufs(dev->hdmi_layer1, &reqbuf) < 0) { 532 ALOGE("%s: exynos_v4l2_reqbufs failed %d", __func__, errno); 533 return -1; 534 } 535 536 return 0; 537} 538 539static int hdmi_enable(struct exynos5_hwc_composer_device_1_t *dev) 540{ 541 if (dev->hdmi_enabled) 542 return 0; 543 544 if (dev->hdmi_blanked) 545 return 0; 546 547 dev->hdmi_gsc = exynos_gsc_create_exclusive(3, GSC_OUTPUT_MODE, GSC_OUT_TV); 548 if (!dev->hdmi_gsc) { 549 ALOGE("%s: exynos_gsc_create_exclusive failed", __func__); 550 return -ENODEV; 551 } 552 553 memset(&dev->hdmi_src, 0, sizeof(dev->hdmi_src)); 554 555 if (hdmi_start_background(dev) < 0) { 556 ALOGE("%s: hdmi_start_background failed", __func__); 557 return -1; 558 } 559 560 dev->hdmi_enabled = true; 561 return 0; 562} 563 564static void hdmi_disable(struct exynos5_hwc_composer_device_1_t *dev) 565{ 566 if (!dev->hdmi_enabled) 567 return; 568 exynos_gsc_destroy(dev->hdmi_gsc); 569 hdmi_stop_background(dev); 570 dev->hdmi_gsc = NULL; 571 dev->hdmi_enabled = false; 572} 573 574static int hdmi_configure(struct exynos5_hwc_composer_device_1_t *dev, 575 exynos_gsc_img &src_cfg, 576 exynos_gsc_img &dst_cfg) 577{ 578 if (!gsc_src_cfg_changed(src_cfg, dev->hdmi_src) 579 && !gsc_dst_cfg_changed(dst_cfg, dev->hdmi_dst)) 580 return 0; 581 582 ALOGV("HDMI source config:"); 583 dump_gsc_img(src_cfg); 584 ALOGV("HDMI dest config:"); 585 dump_gsc_img(dst_cfg); 586 587 exynos_gsc_stop_exclusive(dev->hdmi_gsc); 588 589 int ret = exynos_gsc_config_exclusive(dev->hdmi_gsc, &src_cfg, &dst_cfg); 590 if (ret < 0) { 591 ALOGE("%s: exynos_gsc_config_exclusive failed %d", __func__, ret); 592 return ret; 593 } 594 595 dev->hdmi_src = src_cfg; 596 dev->hdmi_dst = dst_cfg; 597 return ret; 598} 599 600static int hdmi_configure_handle(struct exynos5_hwc_composer_device_1_t *dev, private_handle_t *h) 601{ 602 exynos_gsc_img src_cfg, dst_cfg; 603 memset(&src_cfg, 0, sizeof(src_cfg)); 604 memset(&dst_cfg, 0, sizeof(dst_cfg)); 605 606 src_cfg.w = src_cfg.fw = h->width; 607 src_cfg.h = src_cfg.fh = h->height; 608 src_cfg.format = HAL_PIXEL_FORMAT_BGRA_8888; 609 610 dst_cfg.w = dst_cfg.fw = dev->hdmi_w; 611 dst_cfg.h = dst_cfg.fh = dev->hdmi_h; 612 dst_cfg.format = HAL_PIXEL_FORMAT_EXYNOS_YV12; 613 614 return hdmi_configure(dev, src_cfg, dst_cfg); 615} 616 617static int hdmi_configure_layer(struct exynos5_hwc_composer_device_1_t *dev, hwc_layer_1_t &layer) 618{ 619 exynos_gsc_img src_cfg, dst_cfg; 620 memset(&src_cfg, 0, sizeof(src_cfg)); 621 memset(&dst_cfg, 0, sizeof(dst_cfg)); 622 private_handle_t *src_handle = private_handle_t::dynamicCast(layer.handle); 623 624 src_cfg.x = layer.sourceCrop.left; 625 src_cfg.y = layer.sourceCrop.top; 626 src_cfg.w = WIDTH(layer.sourceCrop); 627 src_cfg.fw = src_handle->stride; 628 src_cfg.h = HEIGHT(layer.sourceCrop); 629 src_cfg.fh = src_handle->vstride; 630 src_cfg.format = src_handle->format; 631 632 if (dev->hdmi_w * src_cfg.h < dev->hdmi_h * src_cfg.w) { 633 dst_cfg.w = dev->hdmi_w; 634 dst_cfg.fw = dev->hdmi_w; 635 dst_cfg.fh = dev->hdmi_h; 636 dst_cfg.h = dev->hdmi_w * src_cfg.h / src_cfg.w; 637 dst_cfg.y = (dev->hdmi_h - dst_cfg.h) / 2; 638 } 639 else { 640 dst_cfg.w = dev->hdmi_h * src_cfg.w / src_cfg.h; 641 dst_cfg.fw = dev->hdmi_w; 642 dst_cfg.h = dev->hdmi_h; 643 dst_cfg.fh = dev->hdmi_h; 644 dst_cfg.x = (dev->hdmi_w - dst_cfg.w) / 2; 645 } 646 dst_cfg.format = HAL_PIXEL_FORMAT_EXYNOS_YV12; 647 dst_cfg.rot = layer.transform; 648 649 return hdmi_configure(dev, src_cfg, dst_cfg); 650} 651 652static int hdmi_output(struct exynos5_hwc_composer_device_1_t *dev, private_handle_t *h) 653{ 654 exynos_gsc_img src_info; 655 exynos_gsc_img dst_info; 656 657 memset(&src_info, 0, sizeof(src_info)); 658 memset(&dst_info, 0, sizeof(dst_info)); 659 660 src_info.yaddr = h->fd; 661 if (exynos5_format_is_ycrcb(h->format)) { 662 src_info.uaddr = h->fd2; 663 src_info.vaddr = h->fd1; 664 } else { 665 src_info.uaddr = h->fd1; 666 src_info.vaddr = h->fd2; 667 } 668 669 int ret = exynos_gsc_run_exclusive(dev->hdmi_gsc, &src_info, &dst_info); 670 if (ret < 0) { 671 ALOGE("%s: exynos_gsc_run_exclusive failed %d", __func__, ret); 672 return ret; 673 } 674 675 return 0; 676} 677 678bool exynos5_supports_overlay(hwc_layer_1_t &layer, size_t i) 679{ 680 if (layer.flags & HWC_SKIP_LAYER) { 681 ALOGV("\tlayer %u: skipping", i); 682 return false; 683 } 684 685 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 686 687 if (!handle) { 688 ALOGV("\tlayer %u: handle is NULL", i); 689 return false; 690 } 691 if (!exynos5_format_is_rgb(handle->format) && 692 !exynos5_format_is_supported_by_gscaler(handle->format)) { 693 ALOGW("\tlayer %u: unexpected format %u", i, handle->format); 694 return false; 695 } 696 697 if (exynos5_requires_gscaler(layer, handle->format)) { 698 if (!exynos5_supports_gscaler(layer, handle->format, false)) { 699 ALOGV("\tlayer %u: gscaler required but not supported", i); 700 return false; 701 } 702 } else { 703 if (!exynos5_format_is_supported(handle->format)) { 704 ALOGV("\tlayer %u: pixel format %u not supported", i, handle->format); 705 return false; 706 } 707 } 708 if (!exynos5_blending_is_supported(layer.blending)) { 709 ALOGV("\tlayer %u: blending %d not supported", i, layer.blending); 710 return false; 711 } 712 713 return true; 714} 715 716inline bool intersect(const hwc_rect &r1, const hwc_rect &r2) 717{ 718 return !(r1.left > r2.right || 719 r1.right < r2.left || 720 r1.top > r2.bottom || 721 r1.bottom < r2.top); 722} 723 724inline hwc_rect intersection(const hwc_rect &r1, const hwc_rect &r2) 725{ 726 hwc_rect i; 727 i.top = max(r1.top, r2.top); 728 i.bottom = min(r1.bottom, r2.bottom); 729 i.left = max(r1.left, r2.left); 730 i.right = min(r1.right, r2.right); 731 return i; 732} 733 734static int exynos5_prepare(hwc_composer_device_1_t *dev, 735 size_t numDisplays, hwc_display_contents_1_t** displays) 736{ 737 if (!numDisplays || !displays) 738 return 0; 739 740 ALOGV("preparing %u layers", displays[0]->numHwLayers); 741 742 exynos5_hwc_composer_device_1_t *pdev = 743 (exynos5_hwc_composer_device_1_t *)dev; 744 memset(pdev->bufs.overlays, 0, sizeof(pdev->bufs.overlays)); 745 memset(pdev->bufs.gsc_map, 0, sizeof(pdev->bufs.gsc_map)); 746 747 bool force_fb = false; 748 if (pdev->hdmi_hpd) { 749 hdmi_enable(pdev); 750 force_fb = true; 751 for (size_t i = 0; i < displays[0]->numHwLayers; i++) { 752 hwc_layer_1_t &layer = displays[0]->hwLayers[i]; 753 if (layer.flags & HWC_SKIP_LAYER) 754 continue; 755 private_handle_t *handle = private_handle_t::dynamicCast(layer.handle); 756 if (handle->flags & GRALLOC_USAGE_EXTERNAL_DISP) { 757 force_fb = false; 758 break; 759 } 760 } 761 } else { 762 hdmi_disable(pdev); 763 } 764 765 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) 766 pdev->bufs.overlay_map[i] = -1; 767 768 bool fb_needed = false; 769 size_t first_fb = 0, last_fb = 0; 770 771 // find unsupported overlays 772 for (size_t i = 0; i < displays[0]->numHwLayers; i++) { 773 hwc_layer_1_t &layer = displays[0]->hwLayers[i]; 774 775 if (layer.compositionType == HWC_BACKGROUND && !force_fb) { 776 ALOGV("\tlayer %u: background supported", i); 777 dump_layer(&displays[0]->hwLayers[i]); 778 continue; 779 } 780 781 if (exynos5_supports_overlay(displays[0]->hwLayers[i], i) && !force_fb) { 782 ALOGV("\tlayer %u: overlay supported", i); 783 layer.compositionType = HWC_OVERLAY; 784 dump_layer(&displays[0]->hwLayers[i]); 785 continue; 786 } 787 788 if (!fb_needed) { 789 first_fb = i; 790 fb_needed = true; 791 } 792 last_fb = i; 793 layer.compositionType = HWC_FRAMEBUFFER; 794 795 dump_layer(&displays[0]->hwLayers[i]); 796 } 797 798 // can't composite overlays sandwiched between framebuffers 799 if (fb_needed) 800 for (size_t i = first_fb; i < last_fb; i++) 801 displays[0]->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 802 803 // Incrementally try to add our supported layers to hardware windows. 804 // If adding a layer would violate a hardware constraint, force it 805 // into the framebuffer and try again. (Revisiting the entire list is 806 // necessary because adding a layer to the framebuffer can cause other 807 // windows to retroactively violate constraints.) 808 bool changed; 809 do { 810 android::Vector<hwc_rect> rects; 811 android::Vector<hwc_rect> overlaps; 812 size_t pixels_left, windows_left, gsc_left = NUM_GSC_UNITS; 813 814 if (fb_needed) { 815 hwc_rect_t fb_rect; 816 fb_rect.top = fb_rect.left = 0; 817 fb_rect.right = pdev->gralloc_module->xres - 1; 818 fb_rect.bottom = pdev->gralloc_module->yres - 1; 819 pixels_left = MAX_PIXELS - pdev->gralloc_module->xres * 820 pdev->gralloc_module->yres; 821 windows_left = NUM_HW_WINDOWS - 1; 822 rects.push_back(fb_rect); 823 } 824 else { 825 pixels_left = MAX_PIXELS; 826 windows_left = NUM_HW_WINDOWS; 827 } 828 if (pdev->hdmi_enabled) 829 gsc_left--; 830 831 changed = false; 832 833 for (size_t i = 0; i < displays[0]->numHwLayers; i++) { 834 hwc_layer_1_t &layer = displays[0]->hwLayers[i]; 835 if (layer.flags & HWC_SKIP_LAYER) 836 continue; 837 838 private_handle_t *handle = private_handle_t::dynamicCast( 839 layer.handle); 840 841 // we've already accounted for the framebuffer above 842 if (layer.compositionType == HWC_FRAMEBUFFER) 843 continue; 844 845 // only layer 0 can be HWC_BACKGROUND, so we can 846 // unconditionally allow it without extra checks 847 if (layer.compositionType == HWC_BACKGROUND) { 848 windows_left--; 849 continue; 850 } 851 852 size_t pixels_needed = WIDTH(layer.displayFrame) * 853 HEIGHT(layer.displayFrame); 854 bool can_compose = windows_left && pixels_needed <= pixels_left; 855 bool gsc_required = exynos5_requires_gscaler(layer, handle->format); 856 if (gsc_required) 857 can_compose = can_compose && gsc_left; 858 859 // hwc_rect_t right and bottom values are normally exclusive; 860 // the intersection logic is simpler if we make them inclusive 861 hwc_rect_t visible_rect = layer.displayFrame; 862 visible_rect.right--; visible_rect.bottom--; 863 864 // no more than 2 layers can overlap on a given pixel 865 for (size_t j = 0; can_compose && j < overlaps.size(); j++) { 866 if (intersect(visible_rect, overlaps.itemAt(j))) 867 can_compose = false; 868 } 869 870 if (!can_compose) { 871 layer.compositionType = HWC_FRAMEBUFFER; 872 if (!fb_needed) { 873 first_fb = last_fb = i; 874 fb_needed = true; 875 } 876 else { 877 first_fb = min(i, first_fb); 878 last_fb = max(i, last_fb); 879 } 880 changed = true; 881 break; 882 } 883 884 for (size_t j = 0; j < rects.size(); j++) { 885 const hwc_rect_t &other_rect = rects.itemAt(j); 886 if (intersect(visible_rect, other_rect)) 887 overlaps.push_back(intersection(visible_rect, other_rect)); 888 } 889 rects.push_back(visible_rect); 890 pixels_left -= pixels_needed; 891 windows_left--; 892 if (gsc_required) 893 gsc_left--; 894 } 895 896 if (changed) 897 for (size_t i = first_fb; i < last_fb; i++) 898 displays[0]->hwLayers[i].compositionType = HWC_FRAMEBUFFER; 899 } while(changed); 900 901 unsigned int nextWindow = 0; 902 int nextGsc = 0; 903 904 for (size_t i = 0; i < displays[0]->numHwLayers; i++) { 905 hwc_layer_1_t &layer = displays[0]->hwLayers[i]; 906 907 if (fb_needed && i == first_fb) { 908 ALOGV("assigning framebuffer to window %u\n", 909 nextWindow); 910 nextWindow++; 911 continue; 912 } 913 914 if (layer.compositionType != HWC_FRAMEBUFFER) { 915 ALOGV("assigning layer %u to window %u", i, nextWindow); 916 pdev->bufs.overlay_map[nextWindow] = i; 917 if (layer.compositionType == HWC_OVERLAY) { 918 private_handle_t *handle = 919 private_handle_t::dynamicCast(layer.handle); 920 if (exynos5_requires_gscaler(layer, handle->format)) { 921 ALOGV("\tusing gscaler %u", AVAILABLE_GSC_UNITS[nextGsc]); 922 pdev->bufs.gsc_map[i].mode = 923 exynos5_gsc_map_t::GSC_M2M; 924 pdev->bufs.gsc_map[i].idx = nextGsc++; 925 } 926 } 927 nextWindow++; 928 } 929 } 930 931 for (size_t i = nextGsc; i < NUM_GSC_UNITS; i++) { 932 for (size_t j = 0; j < NUM_GSC_DST_BUFS; j++) 933 if (pdev->gsc[i].dst_buf[j]) 934 pdev->alloc_device->free(pdev->alloc_device, 935 pdev->gsc[i].dst_buf[j]); 936 memset(&pdev->gsc[i], 0, sizeof(pdev->gsc[i])); 937 } 938 939 if (fb_needed) 940 pdev->bufs.fb_window = first_fb; 941 else 942 pdev->bufs.fb_window = NO_FB_NEEDED; 943 944 return 0; 945} 946 947static int exynos5_config_gsc_m2m(hwc_layer_1_t &layer, 948 alloc_device_t* alloc_device, exynos5_gsc_data_t *gsc_data, 949 int gsc_idx) 950{ 951 ALOGV("configuring gscaler %u for memory-to-memory", gsc_idx); 952 953 private_handle_t *src_handle = private_handle_t::dynamicCast(layer.handle); 954 buffer_handle_t dst_buf; 955 private_handle_t *dst_handle; 956 int ret = 0; 957 958 exynos_gsc_img src_cfg, dst_cfg; 959 memset(&src_cfg, 0, sizeof(src_cfg)); 960 memset(&dst_cfg, 0, sizeof(dst_cfg)); 961 962 src_cfg.x = layer.sourceCrop.left; 963 src_cfg.y = layer.sourceCrop.top; 964 src_cfg.w = WIDTH(layer.sourceCrop); 965 src_cfg.fw = src_handle->stride; 966 src_cfg.h = HEIGHT(layer.sourceCrop); 967 src_cfg.fh = src_handle->vstride; 968 src_cfg.yaddr = src_handle->fd; 969 if (exynos5_format_is_ycrcb(src_handle->format)) { 970 src_cfg.uaddr = src_handle->fd2; 971 src_cfg.vaddr = src_handle->fd1; 972 } else { 973 src_cfg.uaddr = src_handle->fd1; 974 src_cfg.vaddr = src_handle->fd2; 975 } 976 src_cfg.format = src_handle->format; 977 src_cfg.drmMode = !!(src_handle->flags & GRALLOC_USAGE_PROTECTED); 978 979 dst_cfg.x = 0; 980 dst_cfg.y = 0; 981 dst_cfg.w = WIDTH(layer.displayFrame); 982 dst_cfg.h = HEIGHT(layer.displayFrame); 983 dst_cfg.format = HAL_PIXEL_FORMAT_BGRA_8888; 984 dst_cfg.rot = layer.transform; 985 dst_cfg.drmMode = src_cfg.drmMode; 986 987 ALOGV("source configuration:"); 988 dump_gsc_img(src_cfg); 989 990 if (gsc_src_cfg_changed(src_cfg, gsc_data->src_cfg) || 991 gsc_dst_cfg_changed(dst_cfg, gsc_data->dst_cfg)) { 992 int dst_stride; 993 int usage = GRALLOC_USAGE_SW_READ_NEVER | 994 GRALLOC_USAGE_SW_WRITE_NEVER | 995 GRALLOC_USAGE_HW_COMPOSER; 996 997 if (src_handle->flags & GRALLOC_USAGE_PROTECTED) 998 usage |= GRALLOC_USAGE_PROTECTED; 999 1000 int w = ALIGN(WIDTH(layer.displayFrame), GSC_W_ALIGNMENT); 1001 int h = ALIGN(HEIGHT(layer.displayFrame), GSC_H_ALIGNMENT); 1002 1003 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1004 if (gsc_data->dst_buf[i]) { 1005 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1006 gsc_data->dst_buf[i] = NULL; 1007 } 1008 1009 int ret = alloc_device->alloc(alloc_device, w, h, 1010 HAL_PIXEL_FORMAT_RGBX_8888, usage, &gsc_data->dst_buf[i], 1011 &dst_stride); 1012 if (ret < 0) { 1013 ALOGE("failed to allocate destination buffer: %s", 1014 strerror(-ret)); 1015 goto err_alloc; 1016 } 1017 } 1018 1019 gsc_data->current_buf = 0; 1020 } 1021 1022 dst_buf = gsc_data->dst_buf[gsc_data->current_buf]; 1023 dst_handle = private_handle_t::dynamicCast(dst_buf); 1024 1025 dst_cfg.fw = dst_handle->stride; 1026 dst_cfg.fh = dst_handle->vstride; 1027 dst_cfg.yaddr = dst_handle->fd; 1028 1029 ALOGV("destination configuration:"); 1030 dump_gsc_img(dst_cfg); 1031 1032 gsc_data->gsc = exynos_gsc_create_exclusive(AVAILABLE_GSC_UNITS[gsc_idx], 1033 GSC_M2M_MODE, GSC_DUMMY); 1034 if (!gsc_data->gsc) { 1035 ALOGE("failed to create gscaler handle"); 1036 ret = -1; 1037 goto err_alloc; 1038 } 1039 1040 ret = exynos_gsc_config_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1041 if (ret < 0) { 1042 ALOGE("failed to configure gscaler %u", gsc_idx); 1043 goto err_gsc_config; 1044 } 1045 1046 ret = exynos_gsc_run_exclusive(gsc_data->gsc, &src_cfg, &dst_cfg); 1047 if (ret < 0) { 1048 ALOGE("failed to run gscaler %u", gsc_idx); 1049 goto err_gsc_config; 1050 } 1051 1052 gsc_data->src_cfg = src_cfg; 1053 gsc_data->dst_cfg = dst_cfg; 1054 1055 return 0; 1056 1057err_gsc_config: 1058 exynos_gsc_destroy(gsc_data->gsc); 1059 gsc_data->gsc = NULL; 1060err_alloc: 1061 for (size_t i = 0; i < NUM_GSC_DST_BUFS; i++) { 1062 if (gsc_data->dst_buf[i]) { 1063 alloc_device->free(alloc_device, gsc_data->dst_buf[i]); 1064 gsc_data->dst_buf[i] = NULL; 1065 } 1066 } 1067 return ret; 1068} 1069 1070static void exynos5_config_handle(private_handle_t *handle, 1071 hwc_rect_t &sourceCrop, hwc_rect_t &displayFrame, 1072 int32_t blending, s3c_fb_win_config &cfg) 1073{ 1074 cfg.state = cfg.S3C_FB_WIN_STATE_BUFFER; 1075 cfg.fd = handle->fd; 1076 cfg.x = displayFrame.left; 1077 cfg.y = displayFrame.top; 1078 cfg.w = WIDTH(displayFrame); 1079 cfg.h = HEIGHT(displayFrame); 1080 cfg.format = exynos5_format_to_s3c_format(handle->format); 1081 uint8_t bpp = exynos5_format_to_bpp(handle->format); 1082 cfg.offset = (sourceCrop.top * handle->stride + sourceCrop.left) * bpp / 8; 1083 cfg.stride = handle->stride * bpp / 8; 1084 cfg.blending = exynos5_blending_to_s3c_blending(blending); 1085} 1086 1087static void exynos5_config_overlay(hwc_layer_1_t *layer, s3c_fb_win_config &cfg, 1088 const private_module_t *gralloc_module) 1089{ 1090 if (layer->compositionType == HWC_BACKGROUND) { 1091 hwc_color_t color = layer->backgroundColor; 1092 cfg.state = cfg.S3C_FB_WIN_STATE_COLOR; 1093 cfg.color = (color.r << 16) | (color.g << 8) | color.b; 1094 cfg.x = 0; 1095 cfg.y = 0; 1096 cfg.w = gralloc_module->xres; 1097 cfg.h = gralloc_module->yres; 1098 return; 1099 } 1100 1101 private_handle_t *handle = private_handle_t::dynamicCast(layer->handle); 1102 exynos5_config_handle(handle, layer->sourceCrop, layer->displayFrame, 1103 layer->blending, cfg); 1104} 1105 1106static void exynos5_post_callback(void *data, private_handle_t *fb) 1107{ 1108 hwc_layer_1_t *hdmi_layer = NULL; 1109 exynos5_hwc_post_data_t *pdata = (exynos5_hwc_post_data_t *)data; 1110 1111 struct s3c_fb_win_config_data win_data; 1112 struct s3c_fb_win_config *config = win_data.config; 1113 memset(config, 0, sizeof(win_data.config)); 1114 1115 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1116 if ( pdata->overlay_map[i] != -1) { 1117 hwc_layer_1_t &layer = pdata->overlays[i]; 1118 private_handle_t *handle = 1119 private_handle_t::dynamicCast(layer.handle); 1120 1121 if (layer.acquireFenceFd != -1) { 1122 int err = sync_wait(layer.acquireFenceFd, 100); 1123 if (err != 0) 1124 ALOGW("fence for layer %zu didn't signal in 100 ms: %s", 1125 i, strerror(errno)); 1126 close(layer.acquireFenceFd); 1127 } 1128 1129 if (pdata->gsc_map[i].mode == exynos5_gsc_map_t::GSC_M2M) { 1130 int gsc_idx = pdata->gsc_map[i].idx; 1131 exynos5_config_gsc_m2m(layer, pdata->pdev->alloc_device, 1132 &pdata->pdev->gsc[gsc_idx], gsc_idx); 1133 } 1134 } 1135 } 1136 1137 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1138 if (i == pdata->fb_window) { 1139 hwc_rect_t rect = { 0, 0, fb->width, fb->height }; 1140 int32_t blending = (i == 0) ? HWC_BLENDING_NONE : 1141 HWC_BLENDING_PREMULT; 1142 exynos5_config_handle(fb, rect, rect, blending, config[i]); 1143 } else if ( pdata->overlay_map[i] != -1) { 1144 hwc_layer_1_t &layer = pdata->overlays[i]; 1145 private_handle_t *handle = 1146 private_handle_t::dynamicCast(layer.handle); 1147 1148 if (pdata->gsc_map[i].mode == exynos5_gsc_map_t::GSC_M2M) { 1149 int gsc_idx = pdata->gsc_map[i].idx; 1150 exynos5_gsc_data_t &gsc = pdata->pdev->gsc[gsc_idx]; 1151 1152 if (!gsc.gsc) { 1153 ALOGE("failed to queue gscaler %u input for layer %u", 1154 gsc_idx, i); 1155 continue; 1156 } 1157 1158 int err = exynos_gsc_stop_exclusive(gsc.gsc); 1159 exynos_gsc_destroy(gsc.gsc); 1160 gsc.gsc = NULL; 1161 if (err < 0) { 1162 ALOGE("failed to dequeue gscaler output for layer %u", i); 1163 continue; 1164 } 1165 1166 buffer_handle_t dst_buf = gsc.dst_buf[gsc.current_buf]; 1167 gsc.current_buf = (gsc.current_buf + 1) % NUM_GSC_DST_BUFS; 1168 private_handle_t *dst_handle = 1169 private_handle_t::dynamicCast(dst_buf); 1170 hwc_rect_t sourceCrop = { 0, 0, 1171 WIDTH(layer.displayFrame), HEIGHT(layer.displayFrame) }; 1172 exynos5_config_handle(dst_handle, sourceCrop, 1173 layer.displayFrame, layer.blending, config[i]); 1174 1175 if (handle->flags & GRALLOC_USAGE_EXTERNAL_DISP) 1176 hdmi_layer = &layer; 1177 } 1178 else { 1179 exynos5_config_overlay(&layer, config[i], 1180 pdata->pdev->gralloc_module); 1181 } 1182 } 1183 if (i == 0 && config[i].blending != S3C_FB_BLENDING_NONE) { 1184 ALOGV("blending not supported on window 0; forcing BLENDING_NONE"); 1185 config[i].blending = S3C_FB_BLENDING_NONE; 1186 } 1187 1188 ALOGV("window %u configuration:", i); 1189 dump_config(config[i]); 1190 } 1191 1192 int ret = ioctl(pdata->pdev->fd, S3CFB_WIN_CONFIG, &win_data); 1193 if (ret < 0) 1194 ALOGE("ioctl S3CFB_WIN_CONFIG failed: %d", errno); 1195 else { 1196 memcpy(pdata->pdev->last_config, &win_data.config, 1197 sizeof(win_data.config)); 1198 memcpy(pdata->pdev->last_gsc_map, pdata->gsc_map, 1199 sizeof(pdata->gsc_map)); 1200 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1201 if (i == pdata->fb_window) { 1202 pdata->pdev->last_handles[i] = NULL; 1203 } else if (pdata->overlay_map[i] != -1) { 1204 hwc_layer_1_t &layer = pdata->overlays[i]; 1205 pdata->pdev->last_handles[i] = layer.handle; 1206 } 1207 } 1208 } 1209 1210 if (pdata->pdev->hdmi_enabled) { 1211 if (hdmi_layer) { 1212 private_handle_t *handle = 1213 private_handle_t::dynamicCast(hdmi_layer->handle); 1214 hdmi_configure_layer(pdata->pdev, *hdmi_layer); 1215 hdmi_output(pdata->pdev, handle); 1216 } else { 1217 hdmi_configure_handle(pdata->pdev, fb); 1218 hdmi_output(pdata->pdev, fb); 1219 } 1220 } 1221 1222 pthread_mutex_lock(&pdata->completion_lock); 1223 pdata->fence = win_data.fence; 1224 pthread_cond_signal(&pdata->completion); 1225 pthread_mutex_unlock(&pdata->completion_lock); 1226} 1227 1228static int exynos5_set(struct hwc_composer_device_1 *dev, 1229 size_t numDisplays, hwc_display_contents_1_t** displays) 1230{ 1231 exynos5_hwc_composer_device_1_t *pdev = 1232 (exynos5_hwc_composer_device_1_t *)dev; 1233 1234 if (!numDisplays || !displays || !displays[0] || !displays[0]->dpy || !displays[0]->sur) 1235 return 0; 1236 1237 hwc_callback_queue_t *queue = NULL; 1238 pthread_mutex_t *lock = NULL; 1239 exynos5_hwc_post_data_t *data = NULL; 1240 1241 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1242 if (pdev->bufs.overlay_map[i] != -1) { 1243 pdev->bufs.overlays[i] = 1244 displays[0]->hwLayers[pdev->bufs.overlay_map[i]]; 1245 } 1246 } 1247 1248 data = (exynos5_hwc_post_data_t *) 1249 malloc(sizeof(exynos5_hwc_post_data_t)); 1250 memcpy(data, &pdev->bufs, sizeof(pdev->bufs)); 1251 1252 data->fence = -1; 1253 pthread_mutex_init(&data->completion_lock, NULL); 1254 pthread_cond_init(&data->completion, NULL); 1255 1256 if (displays[0]->numHwLayers && pdev->bufs.fb_window == NO_FB_NEEDED) { 1257 exynos5_post_callback(data, NULL); 1258 } else { 1259 1260 struct hwc_callback_entry entry; 1261 entry.callback = exynos5_post_callback; 1262 entry.data = data; 1263 1264 queue = reinterpret_cast<hwc_callback_queue_t *>( 1265 pdev->gralloc_module->queue); 1266 lock = const_cast<pthread_mutex_t *>( 1267 &pdev->gralloc_module->queue_lock); 1268 1269 pthread_mutex_lock(lock); 1270 queue->push_front(entry); 1271 pthread_mutex_unlock(lock); 1272 1273 EGLBoolean success = eglSwapBuffers((EGLDisplay)displays[0]->dpy, 1274 (EGLSurface)displays[0]->sur); 1275 if (!success) { 1276 ALOGE("HWC_EGL_ERROR"); 1277 if (displays[0]) { 1278 pthread_mutex_lock(lock); 1279 queue->removeAt(0); 1280 pthread_mutex_unlock(lock); 1281 free(data); 1282 } 1283 return HWC_EGL_ERROR; 1284 } 1285 } 1286 1287 1288 pthread_mutex_lock(&data->completion_lock); 1289 while (data->fence == -1) 1290 pthread_cond_wait(&data->completion, &data->completion_lock); 1291 pthread_mutex_unlock(&data->completion_lock); 1292 1293 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1294 if (pdev->bufs.overlay_map[i] != -1) { 1295 int dup_fd = dup(data->fence); 1296 if (dup_fd < 0) 1297 ALOGW("release fence dup failed: %s", strerror(errno)); 1298 displays[0]->hwLayers[pdev->bufs.overlay_map[i]].releaseFenceFd = dup_fd; 1299 } 1300 } 1301 close(data->fence); 1302 free(data); 1303 return 0; 1304} 1305 1306static void exynos5_registerProcs(struct hwc_composer_device_1* dev, 1307 hwc_procs_t const* procs) 1308{ 1309 struct exynos5_hwc_composer_device_1_t* pdev = 1310 (struct exynos5_hwc_composer_device_1_t*)dev; 1311 pdev->procs = procs; 1312} 1313 1314static int exynos5_query(struct hwc_composer_device_1* dev, int what, int *value) 1315{ 1316 struct exynos5_hwc_composer_device_1_t *pdev = 1317 (struct exynos5_hwc_composer_device_1_t *)dev; 1318 1319 switch (what) { 1320 case HWC_BACKGROUND_LAYER_SUPPORTED: 1321 // we support the background layer 1322 value[0] = 1; 1323 break; 1324 case HWC_VSYNC_PERIOD: 1325 // vsync period in nanosecond 1326 value[0] = 1000000000.0 / pdev->gralloc_module->fps; 1327 break; 1328 default: 1329 // unsupported query 1330 return -EINVAL; 1331 } 1332 return 0; 1333} 1334 1335static int exynos5_eventControl(struct hwc_composer_device_1 *dev, int dpy, 1336 int event, int enabled) 1337{ 1338 struct exynos5_hwc_composer_device_1_t *pdev = 1339 (struct exynos5_hwc_composer_device_1_t *)dev; 1340 1341 switch (event) { 1342 case HWC_EVENT_VSYNC: 1343 __u32 val = !!enabled; 1344 int err = ioctl(pdev->fd, S3CFB_SET_VSYNC_INT, &val); 1345 if (err < 0) { 1346 ALOGE("vsync ioctl failed"); 1347 return -errno; 1348 } 1349 1350 return 0; 1351 } 1352 1353 return -EINVAL; 1354} 1355 1356static void handle_hdmi_uevent(struct exynos5_hwc_composer_device_1_t *pdev, 1357 const char *buff, int len) 1358{ 1359 const char *s = buff; 1360 s += strlen(s) + 1; 1361 1362 while (*s) { 1363 if (!strncmp(s, "SWITCH_STATE=", strlen("SWITCH_STATE="))) 1364 pdev->hdmi_hpd = atoi(s + strlen("SWITCH_STATE=")) == 1; 1365 1366 s += strlen(s) + 1; 1367 if (s - buff >= len) 1368 break; 1369 } 1370 1371 if (pdev->hdmi_hpd) { 1372 if (hdmi_get_config(pdev)) { 1373 ALOGE("Error reading HDMI configuration"); 1374 pdev->hdmi_hpd = false; 1375 return; 1376 } 1377 } 1378 1379 ALOGV("HDMI HPD changed to %s", pdev->hdmi_hpd ? "enabled" : "disabled"); 1380 if (pdev->hdmi_hpd) 1381 ALOGI("HDMI Resolution changed to %dx%d", pdev->hdmi_h, pdev->hdmi_w); 1382 1383 /* hwc_dev->procs is set right after the device is opened, but there is 1384 * still a race condition where a hotplug event might occur after the open 1385 * but before the procs are registered. */ 1386 if (pdev->procs) 1387 pdev->procs->invalidate(pdev->procs); 1388} 1389 1390static void handle_vsync_event(struct exynos5_hwc_composer_device_1_t *pdev) 1391{ 1392 if (!pdev->procs) 1393 return; 1394 1395 int err = lseek(pdev->vsync_fd, 0, SEEK_SET); 1396 if (err < 0) { 1397 ALOGE("error seeking to vsync timestamp: %s", strerror(errno)); 1398 return; 1399 } 1400 1401 char buf[4096]; 1402 err = read(pdev->vsync_fd, buf, sizeof(buf)); 1403 if (err < 0) { 1404 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1405 return; 1406 } 1407 buf[sizeof(buf) - 1] = '\0'; 1408 1409 errno = 0; 1410 uint64_t timestamp = strtoull(buf, NULL, 0); 1411 if (!errno) 1412 pdev->procs->vsync(pdev->procs, 0, timestamp); 1413} 1414 1415static void *hwc_vsync_thread(void *data) 1416{ 1417 struct exynos5_hwc_composer_device_1_t *pdev = 1418 (struct exynos5_hwc_composer_device_1_t *)data; 1419 char uevent_desc[4096]; 1420 memset(uevent_desc, 0, sizeof(uevent_desc)); 1421 1422 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY); 1423 1424 uevent_init(); 1425 1426 char temp[4096]; 1427 int err = read(pdev->vsync_fd, temp, sizeof(temp)); 1428 if (err < 0) { 1429 ALOGE("error reading vsync timestamp: %s", strerror(errno)); 1430 return NULL; 1431 } 1432 1433 struct pollfd fds[2]; 1434 fds[0].fd = pdev->vsync_fd; 1435 fds[0].events = POLLPRI; 1436 fds[1].fd = uevent_get_fd(); 1437 fds[1].events = POLLIN; 1438 1439 while (true) { 1440 int err = poll(fds, 2, -1); 1441 1442 if (err > 0) { 1443 if (fds[0].revents & POLLPRI) { 1444 handle_vsync_event(pdev); 1445 } 1446 else if (fds[1].revents & POLLIN) { 1447 int len = uevent_next_event(uevent_desc, 1448 sizeof(uevent_desc) - 2); 1449 1450 bool hdmi = !strcmp(uevent_desc, 1451 "change@/devices/virtual/switch/hdmi"); 1452 if (hdmi) 1453 handle_hdmi_uevent(pdev, uevent_desc, len); 1454 } 1455 } 1456 else if (err == -1) { 1457 if (errno == EINTR) 1458 break; 1459 ALOGE("error in vsync thread: %s", strerror(errno)); 1460 } 1461 } 1462 1463 return NULL; 1464} 1465 1466static int exynos5_blank(struct hwc_composer_device_1 *dev, int dpy, int blank) 1467{ 1468 struct exynos5_hwc_composer_device_1_t *pdev = 1469 (struct exynos5_hwc_composer_device_1_t *)dev; 1470 1471 int fb_blank = blank ? FB_BLANK_POWERDOWN : FB_BLANK_UNBLANK; 1472 int err = ioctl(pdev->fd, FBIOBLANK, fb_blank); 1473 if (err < 0) { 1474 ALOGE("%sblank ioctl failed", blank ? "" : "un"); 1475 return -errno; 1476 } 1477 1478 if (pdev->hdmi_hpd) { 1479 if (blank && !pdev->hdmi_blanked) 1480 hdmi_disable(pdev); 1481 pdev->hdmi_blanked = !!blank; 1482 } 1483 1484 return 0; 1485} 1486 1487static void exynos5_dump(hwc_composer_device_1* dev, char *buff, int buff_len) 1488{ 1489 if (buff_len <= 0) 1490 return; 1491 1492 struct exynos5_hwc_composer_device_1_t *pdev = 1493 (struct exynos5_hwc_composer_device_1_t *)dev; 1494 1495 android::String8 result; 1496 1497 result.appendFormat(" hdmi_enabled=%u\n", pdev->hdmi_enabled); 1498 if (pdev->hdmi_enabled) 1499 result.appendFormat(" w=%u, h=%u\n", pdev->hdmi_w, pdev->hdmi_h); 1500 result.append( 1501 " type | handle | color | blend | format | position | size | gsc \n" 1502 "----------+----------|----------+-------+--------+---------------+---------------------\n"); 1503 // 8_______ | 8_______ | 8_______ | 5____ | 6_____ | [5____,5____] | [5____,5____] | 3__ \n" 1504 1505 for (size_t i = 0; i < NUM_HW_WINDOWS; i++) { 1506 struct s3c_fb_win_config &config = pdev->last_config[i]; 1507 if (config.state == config.S3C_FB_WIN_STATE_DISABLED) { 1508 result.appendFormat(" %8s | %8s | %8s | %5s | %6s | %13s | %13s", 1509 "DISABLED", "-", "-", "-", "-", "-", "-"); 1510 } 1511 else { 1512 if (config.state == config.S3C_FB_WIN_STATE_COLOR) 1513 result.appendFormat(" %8s | %8s | %8x | %5s | %6s", "COLOR", 1514 "-", config.color, "-", "-"); 1515 else { 1516 if (pdev->last_handles[i]) 1517 result.appendFormat(" %8s | %8x", "OVERLAY", intptr_t(pdev->last_handles[i])); 1518 else 1519 result.appendFormat(" %8s | %8s", "FB", "-"); 1520 1521 result.appendFormat(" | %8s | %5x | %6x", "-", config.blending, 1522 config.format); 1523 } 1524 1525 result.appendFormat(" | [%5d,%5d] | [%5u,%5u]", config.x, config.y, 1526 config.w, config.h); 1527 } 1528 if (pdev->last_gsc_map[i].mode == exynos5_gsc_map_t::GSC_NONE) 1529 result.appendFormat(" | %3s", "-"); 1530 else 1531 result.appendFormat(" | %3d", 1532 AVAILABLE_GSC_UNITS[pdev->last_gsc_map[i].idx]); 1533 result.append("\n"); 1534 } 1535 1536 strlcpy(buff, result.string(), buff_len); 1537} 1538 1539static int exynos5_close(hw_device_t* device); 1540 1541static int exynos5_open(const struct hw_module_t *module, const char *name, 1542 struct hw_device_t **device) 1543{ 1544 int ret; 1545 int sw_fd; 1546 1547 if (strcmp(name, HWC_HARDWARE_COMPOSER)) { 1548 return -EINVAL; 1549 } 1550 1551 struct exynos5_hwc_composer_device_1_t *dev; 1552 dev = (struct exynos5_hwc_composer_device_1_t *)malloc(sizeof(*dev)); 1553 memset(dev, 0, sizeof(*dev)); 1554 1555 if (hw_get_module(GRALLOC_HARDWARE_MODULE_ID, 1556 (const struct hw_module_t **)&dev->gralloc_module)) { 1557 ALOGE("failed to get gralloc hw module"); 1558 ret = -EINVAL; 1559 goto err_get_module; 1560 } 1561 1562 if (gralloc_open((const hw_module_t *)dev->gralloc_module, 1563 &dev->alloc_device)) { 1564 ALOGE("failed to open gralloc"); 1565 ret = -EINVAL; 1566 goto err_get_module; 1567 } 1568 1569 dev->fd = open("/dev/graphics/fb0", O_RDWR); 1570 if (dev->fd < 0) { 1571 ALOGE("failed to open framebuffer"); 1572 ret = dev->fd; 1573 goto err_open_fb; 1574 } 1575 1576 dev->hdmi_mixer0 = open("/dev/v4l-subdev7", O_RDWR); 1577 if (dev->hdmi_layer0 < 0) { 1578 ALOGE("failed to open hdmi mixer0 subdev"); 1579 ret = dev->hdmi_layer0; 1580 goto err_ioctl; 1581 } 1582 1583 dev->hdmi_layer0 = open("/dev/video16", O_RDWR); 1584 if (dev->hdmi_layer0 < 0) { 1585 ALOGE("failed to open hdmi layer0 device"); 1586 ret = dev->hdmi_layer0; 1587 goto err_mixer0; 1588 } 1589 1590 dev->hdmi_layer1 = open("/dev/video17", O_RDWR); 1591 if (dev->hdmi_layer1 < 0) { 1592 ALOGE("failed to open hdmi layer1 device"); 1593 ret = dev->hdmi_layer1; 1594 goto err_hdmi0; 1595 } 1596 1597 dev->vsync_fd = open("/sys/devices/platform/exynos5-fb.1/vsync", O_RDONLY); 1598 if (dev->vsync_fd < 0) { 1599 ALOGE("failed to open vsync attribute"); 1600 ret = dev->vsync_fd; 1601 goto err_hdmi1; 1602 } 1603 1604 sw_fd = open("/sys/class/switch/hdmi/state", O_RDONLY); 1605 if (sw_fd) { 1606 char val; 1607 if (read(sw_fd, &val, 1) == 1 && val == '1') { 1608 dev->hdmi_hpd = true; 1609 if (hdmi_get_config(dev)) { 1610 ALOGE("Error reading HDMI configuration"); 1611 dev->hdmi_hpd = false; 1612 } 1613 } 1614 } 1615 1616 dev->base.common.tag = HARDWARE_DEVICE_TAG; 1617 dev->base.common.version = HWC_DEVICE_API_VERSION_1_0; 1618 dev->base.common.module = const_cast<hw_module_t *>(module); 1619 dev->base.common.close = exynos5_close; 1620 1621 dev->base.prepare = exynos5_prepare; 1622 dev->base.set = exynos5_set; 1623 dev->base.eventControl = exynos5_eventControl; 1624 dev->base.blank = exynos5_blank; 1625 dev->base.query = exynos5_query; 1626 dev->base.registerProcs = exynos5_registerProcs; 1627 dev->base.dump = exynos5_dump; 1628 1629 dev->bufs.pdev = dev; 1630 1631 *device = &dev->base.common; 1632 1633 ret = pthread_create(&dev->vsync_thread, NULL, hwc_vsync_thread, dev); 1634 if (ret) { 1635 ALOGE("failed to start vsync thread: %s", strerror(ret)); 1636 ret = -ret; 1637 goto err_vsync; 1638 } 1639 1640 return 0; 1641 1642err_vsync: 1643 close(dev->vsync_fd); 1644err_mixer0: 1645 close(dev->hdmi_mixer0); 1646err_hdmi1: 1647 close(dev->hdmi_layer0); 1648err_hdmi0: 1649 close(dev->hdmi_layer1); 1650err_ioctl: 1651 close(dev->fd); 1652err_open_fb: 1653 gralloc_close(dev->alloc_device); 1654err_get_module: 1655 free(dev); 1656 return ret; 1657} 1658 1659static int exynos5_close(hw_device_t *device) 1660{ 1661 struct exynos5_hwc_composer_device_1_t *dev = 1662 (struct exynos5_hwc_composer_device_1_t *)device; 1663 pthread_kill(dev->vsync_thread, SIGTERM); 1664 pthread_join(dev->vsync_thread, NULL); 1665 for (size_t i = 0; i < NUM_GSC_UNITS; i++) { 1666 if (dev->gsc[i].gsc) 1667 exynos_gsc_destroy(dev->gsc[i].gsc); 1668 for (size_t j = 0; i < NUM_GSC_DST_BUFS; j++) 1669 if (dev->gsc[i].dst_buf[j]) 1670 dev->alloc_device->free(dev->alloc_device, dev->gsc[i].dst_buf[j]); 1671 } 1672 gralloc_close(dev->alloc_device); 1673 close(dev->vsync_fd); 1674 close(dev->hdmi_mixer0); 1675 close(dev->hdmi_layer0); 1676 close(dev->hdmi_layer1); 1677 close(dev->fd); 1678 return 0; 1679} 1680 1681static struct hw_module_methods_t exynos5_hwc_module_methods = { 1682 open: exynos5_open, 1683}; 1684 1685hwc_module_t HAL_MODULE_INFO_SYM = { 1686 common: { 1687 tag: HARDWARE_MODULE_TAG, 1688 module_api_version: HWC_MODULE_API_VERSION_0_1, 1689 hal_api_version: HARDWARE_HAL_API_VERSION, 1690 id: HWC_HARDWARE_MODULE_ID, 1691 name: "Samsung exynos5 hwcomposer module", 1692 author: "Google", 1693 methods: &exynos5_hwc_module_methods, 1694 } 1695}; 1696