Lines Matching refs:SSE
786 // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1083 SSE,
1106 /// final MEMORY or SSE classes when necessary.
1359 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
1363 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
1375 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
1377 if (Hi == SSEUp && Lo != SSE)
1378 Hi = SSE;
1401 // (f) Otherwise class SSE is used.
1418 return SSE;
1449 Current = SSE;
1454 // FIXME: _Decimal32 and _Decimal64 are SSE.
1455 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
1503 Current = SSE;
1511 // least significant one belongs to class SSE and all the others to class
1521 Lo = SSE;
1537 Current = SSE;
1541 Lo = Hi = SSE;
1594 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
1945 /// low 8 bytes of an XMM register, corresponding to the SSE class.
2095 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2104 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2135 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
2136 // available SSE register of the sequence %xmm0, %xmm1 is used.
2137 case SSE:
2175 case SSE:
2185 // SSEUP should always be preceded by SSE, just widen.
2187 assert(Lo == SSE && "Unexpected SSEUp classification.");
2197 // extra bits in an SSE reg.
2226 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2237 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2280 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
2281 // available SSE register is used, the registers are taken in the
2283 case SSE: {
2315 case SSE:
2325 // eightbyte is passed in the upper half of the last used SSE
2328 assert(Lo == SSE && "Unexpected SSEUp classification");
2553 // SSE registers are spaced 16 bytes apart in the register save